History log of /openbmc/qemu/include/hw/ (Results 1 – 25 of 8163)
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72e40f0a30-Mar-2023 Joe Komlodi <komlodi@google.com>

hw/i3c: remote_i3c: Add model

Adds a model to communicate to remote I3C devices over chardev. This
allows QEMU to communicate to I3C targets that exist outside of QEMU.

The remote I3C protocol is a

hw/i3c: remote_i3c: Add model

Adds a model to communicate to remote I3C devices over chardev. This
allows QEMU to communicate to I3C targets that exist outside of QEMU.

The remote I3C protocol is as follows:
On an I3C private and CCC TX (controller -> target)
- 1-byte opcode
- 4-byte number of bytes in the packet as a LE uint32
- n-byte payload

On an I3C private and CCC RX (target -> controller)
Controller to target:
- 1-byte opcode
- 4-byte number of bytes to read as a LE uint32
Remote target response:
- 4-byte number of bytes in the packet as a LE uint32
- n-byte payload

IBI (target -> controller, initiated by target)
- 1-byte opcode
- 1-byte IBI address
- 1-byte RnW boolean
- 4-byte length of IBI payload from target as a LE uint32 (can be 0)
- n-byte IBI payload

Signed-off-by: Joe Komlodi <komlodi@google.com>

Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Stephen Longfield <slongfield@google.com>

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48f3efa930-Mar-2023 Joe Komlodi <komlodi@google.com>

hw/i3c: Add Mock target

Adds a simple i3c device to be used for testing in lieu of a real
device.

The mock target supports the following features:
- A buffer that users can read and write to.
- CCC

hw/i3c: Add Mock target

Adds a simple i3c device to be used for testing in lieu of a real
device.

The mock target supports the following features:
- A buffer that users can read and write to.
- CCC support for commonly used CCCs when probing devices on an I3C bus.
- IBI sending upon receiving a user-defined byte.

Signed-off-by: Joe Komlodi <komlodi@google.com>

Reviewed-by: Titus Rwantare <titusr@google.com>
Reviewed-by: Patrick Venture <venture@google.com>

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f171f1c830-Mar-2023 Joe Komlodi <komlodi@google.com>

hw/i3c/aspeed_i3c: Add IBI handling

Adds handling for different IBI events that the controller can receive.
This includes:
- Handling a hot-join from a target
- Handling a secondary controller on th

hw/i3c/aspeed_i3c: Add IBI handling

Adds handling for different IBI events that the controller can receive.
This includes:
- Handling a hot-join from a target
- Handling a secondary controller on the bus requesting to be the
primary bus controller
- Handling an interrupt request from a target.

When receiving an IBI, the controller sets an interrupt to notify
software about what happened.
When the IBI is finished being serviced, the controller pushes the
result of the IBI and any data received from the target into the IBI
queue.

Signed-off-by: Joe Komlodi <komlodi@google.com>

Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Stephen Longfield <slongfield@google.com>

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3fee972b30-Mar-2023 Joe Komlodi <komlodi@google.com>

hw/i3c/aspeed_i3c: Add data TX and RX

This adds data and CCC transmission, reception, and the associated
queues required for data transmission and reception to happen.

The I3C controller transmits

hw/i3c/aspeed_i3c: Add data TX and RX

This adds data and CCC transmission, reception, and the associated
queues required for data transmission and reception to happen.

The I3C controller transmits data by the user writing into a command
queue. When the queue has a command and an argument in it, the
controller starts executing the command.

The controller can execute 1 of 3 ways:
1. A larger data transfer that involves using the TX and RX queues. This
is the most common way the controller does transactions.

2. A small data transfer that involves sending a couple bytes passed
into the command queue argument.

3. An address assignment command. This is how the controller does
ENTDAA. When ENTDAA succeeds in assigning an address to a target, it
updates the controller's char table with the target's PID, BCR, and
DCR.

The controller determines what addresses to send by looking at the index
in the device address table specified by the argument in the command
queue. ENTDAA also uses these addresses to assign to targets on the bus.

When the controller is done executing a command, it puts a response in
the response queue indicating how command execution went.

In order for the user to send and receive data to/from the controller,
the user reads/writes to a bidirectional TX/RX port.

Signed-off-by: Joe Komlodi <komlodi@google.com>

Reviewed-by: Stephen Longfield <slongfield@google.com>
Reviewed-by: Patrick Venture <venture@google.com>

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1d0a979030-Mar-2023 Joe Komlodi <komlodi@google.com>

hw/i3c: Add bus support

Adds an I3C bus and a target class.
The bus supports:
- I3C data transmission and reception
- CCCs (including ENTDAA)
- IBIs
- legacy I2C transactions

General usage of the b

hw/i3c: Add bus support

Adds an I3C bus and a target class.
The bus supports:
- I3C data transmission and reception
- CCCs (including ENTDAA)
- IBIs
- legacy I2C transactions

General usage of the bus is similar to I2C. Users are expected to
initialize a bus via i3c_init_bus, and use the bus returned from the
init function to do transactions on the bus.

In order to handle IBIs, the controller provides callbacks to handle
receiving an IBI from a target, receiving (optional) additional IBI
bytes from a target, and handling when a target is done with its IBI.

Similarly, target creation is done via i3c_target_create_simple and
users use the provided I3CTarget to handle transactions.
The target has functions provided that it can use to invoke an IBI and
send additional bytes.

Along with the expected, send, recv, and event callbacks that is
expected of an I3C target, which are similar to I2C, there is a separate
callback for CCC handling.
This is to help encapsulate CCC handling and keep it separate from
target-specific read/write functionality.

To avoid repition for required CCCs among I3C targets, there is some
class-level CCC handling added. The CCC is then passed to the target in
case it needs to handle it in some way.

Signed-off-by: Joe Komlodi <komlodi@google.com>

Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Titus Rwantare <titusr@google.com>

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c894493430-Mar-2023 Joe Komlodi <komlodi@google.com>

hw/misc/aspeed_i3c: Move to i3c directory

Moves the Aspeed I3C model and traces into hw/i3c and create I3C build
files.

Signed-off-by: Joe Komlodi <komlodi@google.com>

Reviewed-by: Patrick Venture

hw/misc/aspeed_i3c: Move to i3c directory

Moves the Aspeed I3C model and traces into hw/i3c and create I3C build
files.

Signed-off-by: Joe Komlodi <komlodi@google.com>

Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Titus Rwantare <titusr@google.com>
[ clg: - replaced softmmu_ss with system_ss in meson.build files
- local variable renames in aspeed_i3c_realize() ]

show more ...

1b9844d602-Apr-2019 Cédric Le Goater <clg@kaod.org>

i2c: Add a IBM CFF Power Supply device

Simple model of a PSU device of the witherspoon.

TODO:
- generate "real" values
- implement property visitors to generate faults.

Signed-off-by: Cédric

i2c: Add a IBM CFF Power Supply device

Simple model of a PSU device of the witherspoon.

TODO:
- generate "real" values
- implement property visitors to generate faults.

Signed-off-by: Cédric Le Goater <clg@kaod.org>

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7e1e49d711-Aug-2022 Cédric Le Goater <clg@kaod.org>

pci: Add Aspeed host bridge (WIP)

IRQ:

167 AHB to PCIe Bus bridge L
168 AHB to PCIe Bus bridge H

MEM:

1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge)
1E6E:D200-1E6E:D3FF PCIe Host Co

pci: Add Aspeed host bridge (WIP)

IRQ:

167 AHB to PCIe Bus bridge L
168 AHB to PCIe Bus bridge H

MEM:

1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge)
1E6E:D200-1E6E:D3FF PCIe Host Controller (RC)
1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller
6000:0000-7FFF:FFFF PCIe memory window.

Signed-off-by: Cédric Le Goater <clg@kaod.org>

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cf4d96e907-Apr-2021 Cédric Le Goater <clg@kaod.org>

hw/misc: Add an iBT device model

Implement an IPMI BT interface model using a chardev backend to
communicate with an external PowerNV machine. It uses the OpenIPMI
simulator protocol for virtual mac

hw/misc: Add an iBT device model

Implement an IPMI BT interface model using a chardev backend to
communicate with an external PowerNV machine. It uses the OpenIPMI
simulator protocol for virtual machines described in :

https://github.com/cminyard/openipmi/blob/master/lanserv/README.vm

and implemented by the 'ipmi-bmc-extern' model on the host side.

To use, start the Aspeed BMC machine with :

-chardev socket,id=ipmi0,host=localhost,port=9002,ipv4,server,nowait \
-global driver=aspeed.ibt,property=chardev,value=ipmi0

and the PowerNV machine with :

-chardev socket,id=ipmi0,host=localhost,port=9002,reconnect=10 \
-device ipmi-bmc-extern,id=bmc0,chardev=ipmi0 \
-device isa-ipmi-bt,bmc=bmc0,irq=10 -nodefaults

Cc: Hao Wu <wuhaotsh@google.com>
Cc: Corey Minyard <cminyard@mvista.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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0084c02627-Nov-2017 Cédric Le Goater <clg@kaod.org>

hw/misc: Add basic Aspeed PWM model

Just enough to quiet down the output when running with the logs.

Signed-off-by: Cédric Le Goater <clg@kaod.org>

2e7de8b319-Jan-2023 Joel Stanley <joel@jms.id.au>

hw/misc: Add basic Aspeed GFX model

Enough model to capture the pinmux writes to enable correct operation of
the parts of pinmux that depend on GFX registers.

Signed-off-by: Joel Stanley <joel@jms.

hw/misc: Add basic Aspeed GFX model

Enough model to capture the pinmux writes to enable correct operation of
the parts of pinmux that depend on GFX registers.

Signed-off-by: Joel Stanley <joel@jms.id.au>

show more ...

428cd2e918-Oct-2021 Cédric Le Goater <clg@kaod.org>

aspeed/smc: Improve support for the alternate boot function

Map the WDT2 registers in the AST2600 FMC memory region by creating a
local address space on top of WDT2 memory region.

The model only im

aspeed/smc: Improve support for the alternate boot function

Map the WDT2 registers in the AST2600 FMC memory region by creating a
local address space on top of WDT2 memory region.

The model only implements the enable bit of the control register. The
reload register uses a 0.1s unit instead of a 1us. Values are
converted on the fly when doing the accesses. The restart register is
the same.

TODO: This needs a rework since the FMC WDT2 device is an independent
watchdog logic embedded in the FMC device.

Cc: Peter Delevoryas <pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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7d58932918-Oct-2021 Cédric Le Goater <clg@kaod.org>

aspeed/wdt: Introduce a container for the MMIO region

On the AST2600, the 2nd watchdog timer can be controlled through the
FMC controller to disable the alternate boot function. Next changes
will ma

aspeed/wdt: Introduce a container for the MMIO region

On the AST2600, the 2nd watchdog timer can be controlled through the
FMC controller to disable the alternate boot function. Next changes
will map the WDT2 registers in the AST2600 FMC memory region. Add a
container on top of the register region for this purpose.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>

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ba14252512-Nov-2024 Guenter Roeck <linux@roeck-us.net>

aspeed: Add uhci support for ast2600

Add UHCI support for the ast2600 SoC. With this patch, UHCI support
is successfully enabled on the rainier-bmc and ast2600-evb machines.

Signed-off-by: Guenter

aspeed: Add uhci support for ast2600

Add UHCI support for the ast2600 SoC. With this patch, UHCI support
is successfully enabled on the rainier-bmc and ast2600-evb machines.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>

show more ...

3fdd8e5412-Nov-2024 Guenter Roeck <linux@roeck-us.net>

usb/uhci: Move PCI-related code into a separate file

Some machines (like Aspeed ARM) only have a sysbus UHCI controller.
The current UHCI implementation only supports PCI based UHCI controllers.
Mov

usb/uhci: Move PCI-related code into a separate file

Some machines (like Aspeed ARM) only have a sysbus UHCI controller.
The current UHCI implementation only supports PCI based UHCI controllers.
Move the UHCI-PCI device code into a separate file so that it is possible
to create a sysbus UHCI device without PCI dependency.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>

show more ...

0ece3ebe12-Nov-2024 Guenter Roeck <linux@roeck-us.net>

usb/uhci: Introduce and use register defines

Introduce defines for UHCI registers to simplify adding register access
in subsequent patches of the series.

No functional change.

Reviewed-by: Cédric

usb/uhci: Introduce and use register defines

Introduce defines for UHCI registers to simplify adding register access
in subsequent patches of the series.

No functional change.

Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>

show more ...

5260077914-Nov-2024 Jamin Lin <jamin_lin@aspeedtech.com>

hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVB

The Write Protect pin of SDHCI model is default active low to match the SDHCI
spec. So, write enable the bit 19 should be 1 and write

hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVB

The Write Protect pin of SDHCI model is default active low to match the SDHCI
spec. So, write enable the bit 19 should be 1 and write protected the bit 19
should be 0 at the Present State Register (0x24).

According to the design of AST2600 EVB, the Write Protected pin is active
high by default. To support it, introduces a new "sdhci_wp_inverted"
property in ASPEED MACHINE State and set it true for AST2600 EVB
and set "wp_inverted" property true of sdhci-generic model.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>

show more ...

04d21fc814-Nov-2024 Jamin Lin <jamin_lin@aspeedtech.com>

hw/sd/sdhci: Introduce a new Write Protected pin inverted property

The Write Protect pin of SDHCI model is default active low to match the SDHCI
spec. So, write enable the bit 19 should be 1 and wri

hw/sd/sdhci: Introduce a new Write Protected pin inverted property

The Write Protect pin of SDHCI model is default active low to match the SDHCI
spec. So, write enable the bit 19 should be 1 and write protected the bit 19
should be 0 at the Present State Register (0x24). However, some boards are
design Write Protected pin active high. In other words, write enable the bit 19
should be 0 and write protected the bit 19 should be 1 at the
Present State Register (0x24). To support it, introduces a new "wp-inverted"
property and set it false by default.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Acked-by: Cédric Le Goater <clg@redhat.com>

show more ...

4cd7b25304-Dec-2024 Jamin Lin <jamin_lin@aspeedtech.com>

hw/sd/aspeed_sdhci: Add AST2700 Support

Introduce a new ast2700 class to support AST2700. Add a new ast2700 SDHCI class
init function and set the value of capability register to "0x0000000719f80080"

hw/sd/aspeed_sdhci: Add AST2700 Support

Introduce a new ast2700 class to support AST2700. Add a new ast2700 SDHCI class
init function and set the value of capability register to "0x0000000719f80080".

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>

show more ...

9dada52404-Dec-2024 Jamin Lin <jamin_lin@aspeedtech.com>

hw:sdhci: Introduce a new "capareg" class member to set the different Capability Registers

Currently, it set the hardcode value of capability registers to all ASPEED SOCs
However, the value of capab

hw:sdhci: Introduce a new "capareg" class member to set the different Capability Registers

Currently, it set the hardcode value of capability registers to all ASPEED SOCs
However, the value of capability registers should be different for all ASPEED
SOCs. For example: the bit 28 of the Capability Register 1 should be 1 for
64-bits System Bus support for AST2700.

Introduce a new "capareg" class member whose data type is uint_64 to set the
different Capability Registers to all ASPEED SOCs.

The value of Capability Register is "0x0000000001e80080" for AST2400 and
AST2500. The value of Capability Register is "0x0000000701f80080" for AST2600.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>

show more ...


/openbmc/qemu/.mailmap
/openbmc/qemu/MAINTAINERS
/openbmc/qemu/VERSION
/openbmc/qemu/accel/kvm/kvm-all.c
/openbmc/qemu/accel/tcg/plugin-gen.c
/openbmc/qemu/backends/cryptodev-vhost-user.c
/openbmc/qemu/chardev/char-mux.c
/openbmc/qemu/chardev/char.c
/openbmc/qemu/configs/targets/i386-softmmu.mak
/openbmc/qemu/configs/targets/x86_64-softmmu.mak
/openbmc/qemu/crypto/pbkdf.c
/openbmc/qemu/docs/about/deprecated.rst
/openbmc/qemu/docs/about/removed-features.rst
/openbmc/qemu/docs/system/arm/aspeed.rst
/openbmc/qemu/gdbstub/user-target.c
/openbmc/qemu/hw/9pfs/9p-util.h
/openbmc/qemu/hw/9pfs/9p.c
/openbmc/qemu/hw/9pfs/9p.h
/openbmc/qemu/hw/arm/aspeed.c
/openbmc/qemu/hw/arm/aspeed_ast2400.c
/openbmc/qemu/hw/arm/aspeed_ast2600.c
/openbmc/qemu/hw/core/machine.c
/openbmc/qemu/hw/display/vga.c
/openbmc/qemu/hw/i386/acpi-build.c
/openbmc/qemu/hw/i386/amd_iommu.c
/openbmc/qemu/hw/i386/x86-common.c
/openbmc/qemu/hw/intc/arm_gicv3_its.c
/openbmc/qemu/hw/intc/riscv_aplic.c
/openbmc/qemu/hw/mem/cxl_type3.c
/openbmc/qemu/hw/nvme/ctrl.c
/openbmc/qemu/hw/openrisc/cputimer.c
/openbmc/qemu/hw/openrisc/openrisc_sim.c
/openbmc/qemu/hw/pci/msix.c
/openbmc/qemu/hw/pci/pcie.c
/openbmc/qemu/hw/s390x/s390-virtio-ccw.c
/openbmc/qemu/hw/scsi/megasas.c
/openbmc/qemu/hw/sd/aspeed_sdhci.c
/openbmc/qemu/hw/ufs/ufs.c
/openbmc/qemu/hw/usb/canokey.c
/openbmc/qemu/hw/usb/canokey.h
/openbmc/qemu/hw/usb/hcd-xhci-pci.c
/openbmc/qemu/hw/virtio/virtio-balloon.c
sd/aspeed_sdhci.h
/openbmc/qemu/include/sysemu/kvm.h
/openbmc/qemu/include/tcg/tcg-temp-internal.h
/openbmc/qemu/meson.build
/openbmc/qemu/migration/migration.h
/openbmc/qemu/migration/multifd-nocomp.c
/openbmc/qemu/migration/multifd-qatzip.c
/openbmc/qemu/migration/multifd-qpl.c
/openbmc/qemu/migration/multifd-uadk.c
/openbmc/qemu/migration/multifd.c
/openbmc/qemu/migration/vmstate-types.c
/openbmc/qemu/migration/vmstate.c
/openbmc/qemu/net/dump.c
/openbmc/qemu/net/net.c
/openbmc/qemu/pc-bios/descriptors/60-edk2-riscv64.json
/openbmc/qemu/pc-bios/descriptors/meson.build
/openbmc/qemu/roms/Makefile
/openbmc/qemu/scripts/analyze-migration.py
/openbmc/qemu/scripts/checkpatch.pl
/openbmc/qemu/scripts/make-release
/openbmc/qemu/stubs/meson.build
/openbmc/qemu/system/physmem.c
/openbmc/qemu/system/vl.c
/openbmc/qemu/target/arm/helper.c
/openbmc/qemu/target/i386/cpu.c
/openbmc/qemu/target/i386/hvf/x86_mmu.c
/openbmc/qemu/target/i386/kvm/kvm.c
/openbmc/qemu/target/loongarch/tcg/insn_trans/trans_vec.c.inc
/openbmc/qemu/target/riscv/cpu_helper.c
/openbmc/qemu/target/s390x/tcg/mem_helper.c
/openbmc/qemu/tcg/riscv/tcg-target.c.inc
/openbmc/qemu/tcg/tcg.c
/openbmc/qemu/tests/data/acpi/x86/pc/DSDT
/openbmc/qemu/tests/data/acpi/x86/pc/DSDT.acpierst
/openbmc/qemu/tests/data/acpi/x86/pc/DSDT.acpihmat
/openbmc/qemu/tests/data/acpi/x86/pc/DSDT.bridge
/openbmc/qemu/tests/data/acpi/x86/pc/DSDT.cphp
/openbmc/qemu/tests/data/acpi/x86/pc/DSDT.dimmpxm
/openbmc/qemu/tests/data/acpi/x86/pc/DSDT.hpbridge
/openbmc/qemu/tests/data/acpi/x86/pc/DSDT.ipmikcs
/openbmc/qemu/tests/data/acpi/x86/pc/DSDT.memhp
/openbmc/qemu/tests/data/acpi/x86/pc/DSDT.nohpet
/openbmc/qemu/tests/data/acpi/x86/pc/DSDT.numamem
/openbmc/qemu/tests/data/acpi/x86/pc/DSDT.roothp
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.acpierst
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.acpihmat
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.acpihmat-generic-x
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.applesmc
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.bridge
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.core-count
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.core-count2
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.cphp
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.cxl
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.dimmpxm
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.ipmibt
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.ipmismbus
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.ivrs
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.memhp
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.mmio64
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.multi-bridge
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.nohpet
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.numamem
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.pvpanic-isa
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.thread-count
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.thread-count2
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.tis.tpm12
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.tis.tpm2
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.type4-count
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.viot
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.xapic
/openbmc/qemu/tests/functional/test_acpi_bits.py
/openbmc/qemu/tests/functional/test_arm_sx1.py
/openbmc/qemu/tests/functional/test_rx_gdbsim.py
/openbmc/qemu/tests/functional/test_virtio_version.py
/openbmc/qemu/tests/qtest/boot-serial-test.c
/openbmc/qemu/tests/qtest/libqos/virtio-9p-client.c
/openbmc/qemu/tests/qtest/meson.build
/openbmc/qemu/tests/qtest/ufs-test.c
/openbmc/qemu/tests/qtest/virtio-9p-test.c
/openbmc/qemu/tests/qtest/virtio-balloon-test.c
/openbmc/qemu/ui/cocoa.m
24602b7728-Nov-2024 Peter Maydell <peter.maydell@linaro.org>

Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging

virtio,pc,pci: bug fixes, new test

Some small bug fixes, notably a fix for a regression
in cpu hotplug afte

Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging

virtio,pc,pci: bug fixes, new test

Some small bug fixes, notably a fix for a regression
in cpu hotplug after migration. I also included a
new test, just to help make sure we don't regress cxl.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

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* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu:
vhost: fail device start if iotlb update fails
bios-tables-test: Add data for complex numa test (GI, GP etc)
bios-tables-test: Add complex SRAT / HMAT test for GI GP
bios-tables-test: Allow for new acpihmat-generic-x test data.
qapi/qom: Change Since entry for AcpiGenericPortProperties to 9.2
hw/acpi: Fix size of HID in build_append_srat_acpi_device_handle()
qapi: fix device-sync-config since-version
hw/cxl: Check for zero length features in cmd_features_set_feature()
tests/acpi: update expected blobs
Revert "hw/acpi: Make CPUs ACPI `presence` conditional during vCPU hot-unplug"
Revert "hw/acpi: Update ACPI `_STA` method with QOM vCPU ACPI Hotplug states"
qtest: allow ACPI DSDT Table changes
vhost_net: fix assertion triggered by batch of host notifiers processing

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...


/openbmc/qemu/hw/acpi/aml-build.c
/openbmc/qemu/hw/acpi/cpu.c
/openbmc/qemu/hw/cxl/cxl-mailbox-utils.c
/openbmc/qemu/hw/net/vhost_net.c
/openbmc/qemu/hw/virtio/vhost.c
core/cpu.h
/openbmc/qemu/qapi/qdev.json
/openbmc/qemu/qapi/qom.json
/openbmc/qemu/tests/data/acpi/x86/pc/DSDT
/openbmc/qemu/tests/data/acpi/x86/pc/DSDT.acpierst
/openbmc/qemu/tests/data/acpi/x86/pc/DSDT.acpihmat
/openbmc/qemu/tests/data/acpi/x86/pc/DSDT.bridge
/openbmc/qemu/tests/data/acpi/x86/pc/DSDT.cphp
/openbmc/qemu/tests/data/acpi/x86/pc/DSDT.dimmpxm
/openbmc/qemu/tests/data/acpi/x86/pc/DSDT.hpbridge
/openbmc/qemu/tests/data/acpi/x86/pc/DSDT.hpbrroot
/openbmc/qemu/tests/data/acpi/x86/pc/DSDT.ipmikcs
/openbmc/qemu/tests/data/acpi/x86/pc/DSDT.memhp
/openbmc/qemu/tests/data/acpi/x86/pc/DSDT.nohpet
/openbmc/qemu/tests/data/acpi/x86/pc/DSDT.numamem
/openbmc/qemu/tests/data/acpi/x86/pc/DSDT.roothp
/openbmc/qemu/tests/data/acpi/x86/q35/APIC.acpihmat-generic-x
/openbmc/qemu/tests/data/acpi/x86/q35/CEDT.acpihmat-generic-x
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.acpierst
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.acpihmat
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.acpihmat-generic-x
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.applesmc
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.bridge
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.core-count
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.core-count2
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.cphp
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.cxl
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.dimmpxm
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.ipmibt
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.ipmismbus
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.ivrs
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.memhp
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.mmio64
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.multi-bridge
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.noacpihp
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.nohpet
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.numamem
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.pvpanic-isa
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.thread-count
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.thread-count2
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.tis.tpm12
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.tis.tpm2
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.type4-count
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.viot
/openbmc/qemu/tests/data/acpi/x86/q35/DSDT.xapic
/openbmc/qemu/tests/data/acpi/x86/q35/HMAT.acpihmat-generic-x
/openbmc/qemu/tests/data/acpi/x86/q35/SRAT.acpihmat-generic-x
/openbmc/qemu/tests/qtest/bios-tables-test.c
ef45f46f22-Nov-2024 Philippe Mathieu-Daudé <philmd@linaro.org>

hw/pci: Remove unused pci_irq_pulse() method

Last use of pci_irq_pulse() was removed 7 years ago in commit
5e9aa92eb1 ("hw/block: Fix pin-based interrupt behaviour of NVMe").

Signed-off-by: Philipp

hw/pci: Remove unused pci_irq_pulse() method

Last use of pci_irq_pulse() was removed 7 years ago in commit
5e9aa92eb1 ("hw/block: Fix pin-based interrupt behaviour of NVMe").

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20241122103418.539-1-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...


/openbmc/qemu/.gitlab-ci.d/check-dco.py
/openbmc/qemu/.gitlab-ci.d/cirrus.yml
/openbmc/qemu/MAINTAINERS
/openbmc/qemu/VERSION
/openbmc/qemu/block/parallels.c
/openbmc/qemu/block/ssh.c
/openbmc/qemu/docs/about/build-platforms.rst
/openbmc/qemu/docs/devel/submitting-a-patch.rst
/openbmc/qemu/docs/devel/testing/functional.rst
/openbmc/qemu/docs/system/arm/aspeed.rst
/openbmc/qemu/docs/system/arm/emulation.rst
/openbmc/qemu/docs/system/arm/fby35.rst
/openbmc/qemu/hw/core/qdev-properties-system.c
/openbmc/qemu/hw/pci-host/mv64361.c
/openbmc/qemu/hw/ppc/pegasos2.c
/openbmc/qemu/hw/ppc/pnv_core.c
/openbmc/qemu/hw/ppc/pnv_nest_pervasive.c
/openbmc/qemu/hw/ppc/spapr.c
/openbmc/qemu/hw/ppc/spapr_cpu_core.c
pci/pci.h
/openbmc/qemu/include/qemu/qemu-plugin.h
/openbmc/qemu/meson.build
/openbmc/qemu/migration/fd.c
/openbmc/qemu/migration/savevm.c
/openbmc/qemu/plugins/meson.build
/openbmc/qemu/python/scripts/mkvenv.py
/openbmc/qemu/python/setup.cfg
/openbmc/qemu/rust/hw/char/pl011/src/device.rs
/openbmc/qemu/scripts/qemu-plugin-symbols.py
/openbmc/qemu/system/qdev-monitor.c
/openbmc/qemu/system/vl.c
/openbmc/qemu/target/arm/tcg/cpu32.c
/openbmc/qemu/target/ppc/cpu.h
/openbmc/qemu/target/ppc/excp_helper.c
/openbmc/qemu/tests/avocado/hotplug_blk.py
/openbmc/qemu/tests/functional/meson.build
/openbmc/qemu/tests/functional/qemu_test/cmd.py
/openbmc/qemu/tests/functional/qemu_test/testcase.py
/openbmc/qemu/tests/functional/qemu_test/tuxruntest.py
/openbmc/qemu/tests/functional/test_aarch64_aspeed.py
/openbmc/qemu/tests/functional/test_aarch64_tuxrun.py
/openbmc/qemu/tests/functional/test_acpi_bits.py
/openbmc/qemu/tests/functional/test_arm_aspeed.py
/openbmc/qemu/tests/functional/test_arm_bpim2u.py
/openbmc/qemu/tests/functional/test_arm_orangepi.py
/openbmc/qemu/tests/functional/test_loongarch64_virt.py
/openbmc/qemu/tests/functional/test_m68k_nextcube.py
/openbmc/qemu/tests/functional/test_mips64el_malta.py
/openbmc/qemu/tests/functional/test_sh4_tuxrun.py
/openbmc/qemu/tests/functional/test_virtio_gpu.py
/openbmc/qemu/tests/qemu-iotests/iotests.py
/openbmc/qemu/tests/qemu-iotests/pylintrc
f2ba6ab612-Nov-2024 Igor Mammedov <imammedo@redhat.com>

Revert "hw/acpi: Make CPUs ACPI `presence` conditional during vCPU hot-unplug"

This reverts commit 2d6cfbaf174b91dfa9a50065f7494634afb39c23.

The patch is supposed to be part of ARM CPU hotplug seri

Revert "hw/acpi: Make CPUs ACPI `presence` conditional during vCPU hot-unplug"

This reverts commit 2d6cfbaf174b91dfa9a50065f7494634afb39c23.

The patch is supposed to be part of ARM CPU hotplug series and has not value
on its own without it. The series however is still in RFC stage and outside
of scope 9.2 release.

On top of that it introduces not needed callback that pokes directly into
CPU state without any need for that. Instead properties and AML generator
option should be used to configure static platform depended vCPU presence
state.

Drop the patch so that corrected version could be posted along with
ARM CPU hotplug series and properly reviewed in relevant context.
That also helps us to keep history cleaner with new patch being
against original code vs a string of fixups on top of current mess.

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20241112170258.2996640-4-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

show more ...

cb36e25712-Nov-2024 Igor Mammedov <imammedo@redhat.com>

Revert "hw/acpi: Update ACPI `_STA` method with QOM vCPU ACPI Hotplug states"

This reverts commit bf1ecc8dad6061914730a2a2d57af6b37c3a4f8d
which broke cpu hotplug in x86 after migration to older QEM

Revert "hw/acpi: Update ACPI `_STA` method with QOM vCPU ACPI Hotplug states"

This reverts commit bf1ecc8dad6061914730a2a2d57af6b37c3a4f8d
which broke cpu hotplug in x86 after migration to older QEMU

Fixes: bf1ecc8dad606 (w/acpi: Update ACPI `_STA` method with QOM vCPU ACPI Hotplug states)
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20241112170258.2996640-3-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

show more ...

9379ea9d22-Oct-2024 Akihiko Odaki <akihiko.odaki@daynix.com>

virtio-net: Add queues before loading them

Call virtio_net_set_multiqueue() to add queues before loading their
states. Otherwise the loaded queues will not have handlers and elements
in them will no

virtio-net: Add queues before loading them

Call virtio_net_set_multiqueue() to add queues before loading their
states. Otherwise the loaded queues will not have handlers and elements
in them will not be processed.

Cc: qemu-stable@nongnu.org
Fixes: 8c49756825da ("virtio-net: Add only one queue pair when realizing")
Reported-by: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>

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