| a22acbb2 | 23-Jan-2025 | Jamin Lin <jamin_lin@aspeedtech.com> | aspeed/wdt: Support software reset mode for AST2600
 On the AST2400 and AST2500 platforms, the system can only be reset by enabling
 the WDT (Watchdog Timer) and waiting for the WDT timeout. However,
 aspeed/wdt: Support software reset mode for AST2600
 On the AST2400 and AST2500 platforms, the system can only be reset by enabling
 the WDT (Watchdog Timer) and waiting for the WDT timeout. However, starting
 from the AST2600 platform, the reset event can be triggered directly and
 intentionally by software, without relying on the WDT timeout.
 
 This mechanism, referred to as "software restart", is implemented in hardware.
 When using the software restart mechanism, the WDT counter is not enabled.
 
 To trigger a reset generation in software mode, write 0xAEEDF123 to register
 0x24 and software mode reset only support SOC reset mode.
 
 A new function, "aspeed_wdt_is_soc_reset_mode", is introduced to determine
 whether the SoC reset mode is active.
 
 Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
 Reviewed-by: Cédric Le Goater <clg@redhat.com>
 Link: https://lore.kernel.org/qemu-devel/20250124030249.1706996-3-jamin_lin@aspeedtech.com
 Signed-off-by: Cédric Le Goater <clg@redhat.com>
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| eff9dc56 | 19-Nov-2024 | Roque Arcudia Hernandez <roqueh@google.com> | hw/watchdog/cmsdk_apb_watchdog: Fix INTEN issues
 Current watchdog is free running out of reset, this combined with the
 fact that current implementation also ensures the counter is running
 when progr
 hw/watchdog/cmsdk_apb_watchdog: Fix INTEN issues
 Current watchdog is free running out of reset, this combined with the
 fact that current implementation also ensures the counter is running
 when programing WDOGLOAD creates issues when the firmware defer the
 programing of WDOGCONTROL.INTEN much later after WDOGLOAD. Arm
 Programmer's Model documentation states that INTEN is also the
 counter enable:
 
 > INTEN
 >
 > Enable the interrupt event, WDOGINT. Set HIGH to enable the counter
 > and the interrupt, or LOW to disable the counter and interrupt.
 > Reloads the counter from the value in WDOGLOAD when the interrupt
 > is enabled, after previously being disabled.
 
 Source of the time of writing:
 
 https://developer.arm.com/documentation/ddi0479/d/apb-components/apb-watchdog/programmers-model
 
 Signed-off-by: Roque Arcudia Hernandez <roqueh@google.com>
 Reviewed-by: Stephen Longfield <slongfield@google.com>
 Reviewed-by: Joe Komlodi <komlodi@google.com>
 Message-id: 20241115160328.1650269-3-roqueh@google.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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| 88a9973e | 28-Oct-2023 | Bernhard Beschow <shentey@gmail.com> | hw/watchdog/wdt_imx2: Trace timer activity
 Signed-off-by: Bernhard Beschow <shentey@gmail.com>
 Message-id: 20231028122415.14869-3-shentey@gmail.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.o
 hw/watchdog/wdt_imx2: Trace timer activity
 Signed-off-by: Bernhard Beschow <shentey@gmail.com>
 Message-id: 20231028122415.14869-3-shentey@gmail.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 show more ...  |