Merge tag 'hw-misc-20240806' of https://github.com/philmd/qemu into staging

Misc HW & UI patches

- Replace Loongson IPI with LoongArch IPI on LoongArch Virt machine (Bibo)
- SD card: Do not abort w

Merge tag 'hw-misc-20240806' of https://github.com/philmd/qemu into staging

Misc HW & UI patches

- Replace Loongson IPI with LoongArch IPI on LoongArch Virt machine (Bibo)
- SD card: Do not abort when reading DAT lines on invalid cmd state (Phil)
- SDHCI: Reset @data_count index on invalid ADMA transfers (Phil)
- Don't decrement PFlash counter below 0 (Peter)
- Explicit a 8bit truncate on IDE ATAPI (Peter)
- Silent Coverity warning in ISA FDC (Peter)
- Remove dead code in PCI IDE bmdma_prepare_buf (Peter)
- Improve OpenGL and related display error messages (Peter)
- Set PCI base address register write mask on GC64120 host bridge (Phil)
- List PCIe Root Port and PCIe-to-PCI bridge in QEMU PCI IDs list (George)

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# gpg: Signature made Wed 07 Aug 2024 12:25:30 AM AEST
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]

* tag 'hw-misc-20240806' of https://github.com/philmd/qemu: (28 commits)
docs/specs/pci-ids: Fix markup
docs/specs/pci-ids: Add missing devices
hw/pci-host/gt64120: Reset config registers during RESET phase
hw/pci-host/gt64120: Set PCI base address register write mask
ui/console: Note in '-display help' that some backends support suboptions
system/vl.c: Expand OpenGL related errors
hw/display/virtio-gpu: Improve "opengl is not available" error message
hw/ide/pci: Remove dead code from bmdma_prepare_buf()
hw/block/fdc-isa: Assert that isa_fdc_get_drive_max_chs() found something
hw/ide/atapi: Be explicit that assigning to s->lcyl truncates
hw/block/pflash_cfi01: Don't decrement pfl->counter below 0
hw/sd/sdhci: Reset @data_count index on invalid ADMA transfers
hw/sd/sdcard: Do not abort when reading DAT lines on invalid cmd state
hw/sd/sdcard: Explicit dummy byte value
hw/intc/loongson_ipi: Restrict to MIPS
hw/loongarch/virt: Replace Loongson IPI with LoongArch IPI
hw/intc/loongarch_ipi: Add loongarch IPI support
hw/intc/loongson_ipi: Move common code to loongson_ipi_common.c
hw/intc/loongson_ipi: Expose loongson_ipi_core_read/write helpers
hw/intc/loongson_ipi: Add LoongsonIPICommonClass::cpu_by_arch_id handler
...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

hw/intc/loongarch_ipi: Add loongarch IPI support

Loongarch IPI is added here, it inherits from class
TYPE_LOONGSON_IPI_COMMON, and two interfaces get_iocsr_as() and
cpu_by_arch_id() are added for Lo

hw/intc/loongarch_ipi: Add loongarch IPI support

Loongarch IPI is added here, it inherits from class
TYPE_LOONGSON_IPI_COMMON, and two interfaces get_iocsr_as() and
cpu_by_arch_id() are added for Loongarch 3A5000 machine. It can
be used when ipi is emulated in userspace with KVM mode.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
[PMD: Rebased and simplified]
Co-Developed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Tested-by: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20240805180622.21001-13-philmd@linaro.org>

show more ...

hw/intc/loongson_ipi: Add TYPE_LOONGSON_IPI_COMMON stub

Introduce LOONGSON_IPI_COMMON stubs, QDev parent of LOONGSON_IPI.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
[PMD: Extracted from bigger c

hw/intc/loongson_ipi: Add TYPE_LOONGSON_IPI_COMMON stub

Introduce LOONGSON_IPI_COMMON stubs, QDev parent of LOONGSON_IPI.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Tested-by: Bibo Mao <maobibo@loongson.cn>
Acked-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20240805180622.21001-4-philmd@linaro.org>

show more ...

Merge tag 'hw-misc-20240508' of https://github.com/philmd/qemu into staging

Misc HW patches

- Few more g_memdup() replaced by safer g_memdup2() wrapper (Phil)
- Endianness access fixed in vfio-user

Merge tag 'hw-misc-20240508' of https://github.com/philmd/qemu into staging

Misc HW patches

- Few more g_memdup() replaced by safer g_memdup2() wrapper (Phil)
- Endianness access fixed in vfio-user config space (Mattias)
- Replace qemu_mutex_lock() -> QEMU_LOCK_GUARD in system/physmem (Phil)
- Per-AddressSpace bounce buffering (Mattias)
- Allow to compile x86 PC machines without Floppy Controller (Thomas)
- Cleanups around i386 "isa-bios" memory regions (Bernhard)
- Remove unused usb rndis_config_parameter structure (David)
- Migrate missing clock in STM32L4x5 GPIOs (Inès)
- Deprecate PPC 'ref405ep' machine and 405 CPUs (Cédric)
- Memory leak fixed in Loongarch Virt machine (Song Gao)
- hw/loongarch/ code moved around (Paolo & Bibo Mao)
- Emulate S3 suspend in loongson3_virt machine (Jiaxun)
- Implement IOCSR address space in Loongson IPI (Jiaxun)
- Use QEMU header path relative to include/ directory (Phil)

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# gpg: Signature made Thu 09 May 2024 12:12:40 AM CEST
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]

* tag 'hw-misc-20240508' of https://github.com/philmd/qemu: (28 commits)
misc: Use QEMU header path relative to include/ directory
hw/intc/loongson_ipi: Implement IOCSR address space for MIPS
hw/intc/loongarch_ipi: Rename as loongson_ipi
hw/intc/loongarch_ipi: Remove pointless MAX_CPU check
hw/mips/loongson3_virt: Emulate suspend function
hw/loongarch: Rename LoongArchMachineState with LoongArchVirtMachineState
hw/loongarch: Rename LOONGARCH_MACHINE with LOONGARCH_VIRT_MACHINE
hw/loongarch/virt: Fix memory leak
hw/loongarch: move memory map to boot.c
hw/ppc: Deprecate 'ref405ep' machine and 405 CPUs
hw/gpio: Handle clock migration in STM32L4x5 gpios
hw/usb/dev-network: Remove unused struct 'rndis_config_parameter'
hw/i386/x86: Extract x86_isa_bios_init() from x86_bios_rom_init()
hw/i386/x86: Don't leak "pc.bios" memory region
hw/i386/x86: Don't leak "isa-bios" memory regions
hw/i386: Have x86_bios_rom_init() take X86MachineState rather than MachineState
hw/i386/x86: Eliminate two if statements in x86_bios_rom_init()
hw/i386: Add the possibility to use i440fx and isapc without FDC
hw/i386/Kconfig: Allow to compile Q35 without FDC_ISA
hw/i386/pc: Allow to compile without CONFIG_FDC_ISA
...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

hw/intc/loongarch_ipi: Rename as loongson_ipi

This device will be shared among LoongArch and MIPS
based Loongson machine, rename it as loongson_ipi
to reflect this nature.

Signed-off-by: Jiaxun Yan

hw/intc/loongarch_ipi: Rename as loongson_ipi

This device will be shared among LoongArch and MIPS
based Loongson machine, rename it as loongson_ipi
to reflect this nature.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240508-loongson3-ipi-v1-2-1a7b67704664@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

show more ...

Merge tag 'housekeeping-20240424' of https://github.com/philmd/qemu into staging

Removal of deprecated code

- Remove the Nios II target and hardware
- Remove pvrdma device and rdmacm-mux helper
- R

Merge tag 'housekeeping-20240424' of https://github.com/philmd/qemu into staging

Removal of deprecated code

- Remove the Nios II target and hardware
- Remove pvrdma device and rdmacm-mux helper
- Remove GlusterFS RDMA protocol handling
- Update Sriram Yagnaraman mail address

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# gpg: Signature made Wed 24 Apr 2024 07:12:22 AM PDT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]

* tag 'housekeeping-20240424' of https://github.com/philmd/qemu:
block/gluster: Remove deprecated RDMA protocol handling
hw/rdma: Remove deprecated pvrdma device and rdmacm-mux helper
hw/timer: Remove the ALTERA_TIMER model
target/nios2: Remove the deprecated Nios II target
MAINTAINERS: Update Sriram Yagnaraman mail address

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

target/nios2: Remove the deprecated Nios II target

The Nios II target is deprecated since v8.2 in commit 9997771bc1
("target/nios2: Deprecate the Nios II architecture").

Remove:
- Buildsys / CI inf

target/nios2: Remove the deprecated Nios II target

The Nios II target is deprecated since v8.2 in commit 9997771bc1
("target/nios2: Deprecate the Nios II architecture").

Remove:
- Buildsys / CI infra
- User emulation
- System emulation (10m50-ghrd & nios2-generic-nommu machines)
- Tests

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Marek Vasut <marex@denx.de>
Message-Id: <20240327144806.11319-3-philmd@linaro.org>

show more ...

hw/intc/Kconfig: Fix GIC settings when using "--without-default-devices"

When using "--without-default-devices", the ARM_GICV3_TCG and ARM_GIC_KVM
settings currently get disabled, though the arm vir

hw/intc/Kconfig: Fix GIC settings when using "--without-default-devices"

When using "--without-default-devices", the ARM_GICV3_TCG and ARM_GIC_KVM
settings currently get disabled, though the arm virt machine is only of
very limited use in that case. This also causes the migration-test to
fail in such builds. Let's make sure that we always keep the GIC switches
enabled in the --without-default-devices builds, too.

Message-ID: <20240221110059.152665-1-thuth@redhat.com>
Tested-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Thomas Huth <thuth@redhat.com>
(cherry picked from commit 8bd3f84d1f6fba0edebc450be6fa2c7630584df9)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>

show more ...

Merge tag 'pull-request-2024-03-01' of https://gitlab.com/thuth/qemu into staging

* Fix some bugs in the vring setup of libqos
* Fix GIC settings when using --without-default-devices
* Fix USB PCAP

Merge tag 'pull-request-2024-03-01' of https://gitlab.com/thuth/qemu into staging

* Fix some bugs in the vring setup of libqos
* Fix GIC settings when using --without-default-devices
* Fix USB PCAP streams on Windows
* Remove temporary files from test-util-sockets
* Fix TLS io channels sending too much data to the backend

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# gpg: Signature made Fri 01 Mar 2024 08:04:39 GMT
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5

* tag 'pull-request-2024-03-01' of https://gitlab.com/thuth/qemu:
chardev/char-socket: Fix TLS io channels sending too much data to the backend
tests/unit/test-util-sockets: Remove temporary file after test
hw/usb/bus.c: PCAP adding 0xA in Windows version
hw/intc/Kconfig: Fix GIC settings when using "--without-default-devices"
libqos/virtio.c: fix 'avail_event' offset in qvring_init()
libqos/virtio.c: init all elems in qvring_indirect_desc_setup()

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

hw/intc/Kconfig: Fix GIC settings when using "--without-default-devices"

When using "--without-default-devices", the ARM_GICV3_TCG and ARM_GIC_KVM
settings currently get disabled, though the arm vir

hw/intc/Kconfig: Fix GIC settings when using "--without-default-devices"

When using "--without-default-devices", the ARM_GICV3_TCG and ARM_GIC_KVM
settings currently get disabled, though the arm virt machine is only of
very limited use in that case. This also causes the migration-test to
fail in such builds. Let's make sure that we always keep the GIC switches
enabled in the --without-default-devices builds, too.

Message-ID: <20240221110059.152665-1-thuth@redhat.com>
Tested-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

Merge tag 'pull-request-2023-07-18' of https://gitlab.com/thuth/qemu into staging

* Fix s390x KVM guests when compiling with --without-default-devices
* Fix /proc/cpuinfo features list in s390x linu

Merge tag 'pull-request-2023-07-18' of https://gitlab.com/thuth/qemu into staging

* Fix s390x KVM guests when compiling with --without-default-devices
* Fix /proc/cpuinfo features list in s390x linux-user emulation
* Generate FreeBSD VM package list via lcitool
* Disable the flaky test_sbsaref_edk2_firmware avocado test by default

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# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 18 Jul 2023 10:29:02 BST
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5

* tag 'pull-request-2023-07-18' of https://gitlab.com/thuth/qemu:
tests/avocado: Disable the test_sbsaref_edk2_firmware by default
tests/vm/freebsd: Get up-to-date package list from lcitool vars file
tests/vm: Introduce get_qemu_packages_from_lcitool_json() helper
tests/lcitool: Refresh generated files
tests/lcitool: Generate distribution packages list in JSON format
tests/qtest: Fix typo in multifd cancel test
linux-user/elfload: Fix /proc/cpuinfo features: on s390x
s390x: Fix QEMU abort by selecting S390_FLIC_KVM

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

s390x: Fix QEMU abort by selecting S390_FLIC_KVM

If QEMU is built with --without-default-devices, the s390-flic-kvm
device is missing and QEMU aborts when started with the KVM accelerator.
Make sure

s390x: Fix QEMU abort by selecting S390_FLIC_KVM

If QEMU is built with --without-default-devices, the s390-flic-kvm
device is missing and QEMU aborts when started with the KVM accelerator.
Make sure it's available by selecting S390_FLIC_KVM in Kconfig.

Consequently, this also fixes an abort in tests/qtest/migration-test.

Signed-off-by: Cédric Le Goater <clg@redhat.com>
Message-Id: <20230711151440.716822-1-clg@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

Merge tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qemu into staging

First RISC-V PR for QEMU 8.0

* Fix PMP propagation for tlb
* Collection of bug fixes
* Bump the OpenTitan

Merge tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qemu into staging

First RISC-V PR for QEMU 8.0

* Fix PMP propagation for tlb
* Collection of bug fixes
* Bump the OpenTitan supported version
* Add smstateen support
* Support native debug icount trigger
* Remove the redundant ipi-id property in the virt machine
* Support cache-related PMU events in virtual mode
* Add some missing PolarFire SoC io regions
* Fix mret exception cause when no pmp rule is configured
* Fix bug where disabling compressed instructions would crash QEMU
* Add Zawrs ISA extension support
* A range of code refactoring and cleanups

# gpg: Signature made Fri 06 Jan 2023 00:47:23 GMT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qemu: (43 commits)
hw/intc: sifive_plic: Fix the pending register range check
hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization
hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0
hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb
hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"
hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC
hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC
hw/intc: sifive_plic: Update "num-sources" property default value
hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize()
hw/intc: sifive_plic: Improve robustness of the PLIC config parser
hw/intc: sifive_plic: Drop PLICMode_H
hw/riscv: spike: Remove misleading comments
hw/riscv: Sort machines Kconfig options in alphabetical order
hw/riscv: Fix opentitan dependency to SIFIVE_PLIC
hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers
hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC
RISC-V: Add Zawrs ISA extension support
target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+
target/riscv: Simplify helper_sret() a little bit
target/riscv: Set pc_succ_insn for !rvc illegal insn
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers

hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt
controllers regardless of how MSI is implemented. msi_nonbroken is

hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers

hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt
controllers regardless of how MSI is implemented. msi_nonbroken is
initialized to true in both riscv_aplic_realize() and
riscv_imsic_realize().

Select MSI_NONBROKEN in RISCV_APLIC and RISCV_IMSIC.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221211030829.802437-2-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

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hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC

hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt
controllers regardless of how MSI is implemented. msi_nonbroken is
initialized to true

hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC

hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt
controllers regardless of how MSI is implemented. msi_nonbroken is
initialized to true in sifive_plic_realize().

Let SIFIVE_PLIC select MSI_NONBROKEN and drop the selection from
RISC-V machines.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Message-Id: <20221211030829.802437-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

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Merge tag 'pull-la-20220606' of https://gitlab.com/rth7680/qemu into staging

Initial LoongArch support.

# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmKeiRYdHHJpY

Merge tag 'pull-la-20220606' of https://gitlab.com/rth7680/qemu into staging

Initial LoongArch support.

# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmKeiRYdHHJpY2hhcmQu
# aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV85Kgf/buBy5+0y51NKOpTI
# zwFzvuQoWyMwb1nz1ag3i0Sk5fk72zmQI13fwfCgyUZckT165qISa2hohnzl4zVZ
# CO0uZl44makET+uqJn5h2VXSM7Wf+jv0UzbCElVQuEFt0t1bIPbco0pTx/TojBb+
# +YKN4jobvJiLVhD1wDVJqp/2r9gcnX11EWZk+ZC+pIiEqYZpWRcQdEGVh4Ymhig8
# 0LK/8HRSyw0AecX/01hcGWvYCC0ldFicwN69AD42BqM+7WD+3jnV8FJL8qqq766G
# xuCNHz0eDcVgfw9bCEyhFmhgiBFvOXNCtyDOV0qVn7eee9nIrFZcsGyBqeI/T1el
# e7uz8Q==
# =l8TD
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 06 Jun 2022 04:09:10 PM PDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]

* tag 'pull-la-20220606' of https://gitlab.com/rth7680/qemu: (43 commits)
target/loongarch: 'make check-tcg' support
tests/tcg/loongarch64: Add hello/memory test in loongarch64 system
target/loongarch: Add gdb support.
hw/loongarch: Add LoongArch virt power manager support.
hw/loongarch: Add LoongArch load elf function.
hw/loongarch: Add LoongArch ls7a rtc device support
hw/loongarch: Add some devices support for 3A5000.
Enable common virtio pci support for LoongArch
hw/loongarch: Add irq hierarchy for the system
hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)
hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI)
hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)
hw/loongarch: Add LoongArch ipi interrupt support(IPI)
hw/loongarch: Add support loongson3 virt machine type.
target/loongarch: Add timer related instructions support.
target/loongarch: Add other core instructions support
target/loongarch: Add TLB instruction support
target/loongarch: Add LoongArch IOCSR instruction
target/loongarch: Add LoongArch CSR instruction
target/loongarch: Add constant timer support
...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)

This patch realize the EIOINTC interrupt controller.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gao

hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)

This patch realize the EIOINTC interrupt controller.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-35-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI)

This patch realize PCH-MSI interrupt controller.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Ga

hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI)

This patch realize PCH-MSI interrupt controller.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-34-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)

This patch realize the PCH-PIC interrupt controller.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Ga

hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)

This patch realize the PCH-PIC interrupt controller.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-33-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

hw/loongarch: Add LoongArch ipi interrupt support(IPI)

This patch realize the IPI interrupt controller.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loon

hw/loongarch: Add LoongArch ipi interrupt support(IPI)

This patch realize the IPI interrupt controller.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-32-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge tag 'pull-nios2-20220426' of https://gitlab.com/rth7680/qemu into staging

Fix nios2-linux-user syscalls.
Fix nios2-linux-user sigreturn.
Enable tests for nios2-linux-user.
Remove special handl

Merge tag 'pull-nios2-20220426' of https://gitlab.com/rth7680/qemu into staging

Fix nios2-linux-user syscalls.
Fix nios2-linux-user sigreturn.
Enable tests for nios2-linux-user.
Remove special handling of SIGSEGV.
Check supervisor for eret, bret.
Split special registers out of env->regs[].
Clean up interrupt processing.
Raise unaligned data and destination exceptions.
Set TLBMISC fields correctly on exceptions.
Prevent writes to read-only or reserved control fields.
Use tcg_constant_tl().
Implement shadow register sets.
Implement external interrupt controller interface.
Implement vectored interrupt controller.
Enable semihosting tests for nios2-softmmu.

# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmJoNuQdHHJpY2hhcmQu
# aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+a0ggAhawc3tod4OTHRlRq
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# TMV0sbNDeA2OB98QzX6JTbCRtEfQAB7pyjpFvg6oXhYYSfwwhWbTR9QsYTHjq157
# ZKOprafoSlmDlgWJhlAikLdvJb07/5jgmvsLbBzu8/G/HiJ4HhHyjZxL1wNz1t/+
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# CCz42Q==
# =MHar
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 26 Apr 2022 11:16:04 AM PDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]

* tag 'pull-nios2-20220426' of https://gitlab.com/rth7680/qemu: (68 commits)
tests/tcg/nios2: Add test-shadow-1
tests/tcg/nios2: Add semihosting multiarch tests
hw/nios2: Machine with a Vectored Interrupt Controller
hw/nios2: Move memory regions into Nios2Machine
hw/nios2: Introduce Nios2MachineState
hw/intc: Vectored Interrupt Controller (VIC)
linux-user/nios2: Handle various SIGILL exceptions
target/nios2: Advance pc when raising exceptions
target/nios2: Implement EIC interrupt processing
target/nios2: Update helper_eret for shadow registers
target/nios2: Implement rdprs, wrprs
target/nios2: Introduce shadow register sets
target/nios2: Implement Misaligned destination exception
target/nios2: Use tcg_gen_lookup_and_goto_ptr
target/nios2: Use gen_goto_tb for DISAS_TOO_MANY
target/nios2: Hoist set of is_jmp into gen_goto_tb
target/nios2: Create gen_jumpr
target/nios2: Enable unaligned traps for system mode
target/nios2: Drop CR_STATUS_EH from tb->flags
target/nios2: Introduce dest_gpr
...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

hw/intc: Vectored Interrupt Controller (VIC)

Implement nios2 Vectored Interrupt Controller (VIC).
VIC is connected to EIC. It needs to update rha, ril, rrs and rnmi
fields on Nios2CPU before raising

hw/intc: Vectored Interrupt Controller (VIC)

Implement nios2 Vectored Interrupt Controller (VIC).
VIC is connected to EIC. It needs to update rha, ril, rrs and rnmi
fields on Nios2CPU before raising an IRQ.
For that purpose, VIC has a "cpu" property which should refer to the
nios2 cpu and set by the board that connects VIC.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Amir Gonnen <amir.gonnen@neuroblade.ai>
Message-Id: <20220303153906.2024748-5-amir.gonnen@neuroblade.ai>
[rth: Split out nios2_vic.h]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220421151735.31996-60-richard.henderson@linaro.org>

show more ...

Merge tag 'pull-target-arm-20220318' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
* Fix sve2 ldnt1 and stnt1
* Fix pauth_check_trap vs SEL2
* Fix handling of

Merge tag 'pull-target-arm-20220318' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
* Fix sve2 ldnt1 and stnt1
* Fix pauth_check_trap vs SEL2
* Fix handling of LPAE block descriptors
* hw/dma/xlnx_csu_dma: Set TYPE_XLNX_CSU_DMA class_size
* hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init()
* nsis installer: List emulators in alphabetical order
* nsis installer: Suppress "ANSI targets are deprecated" warning
* nsis installer: Fix mouse-over descriptions for emulators
* hw/arm/virt: Fix gic-version=max when CONFIG_ARM_GICV3_TCG is unset
* Improve M-profile vector table access logging
* Xilinx ZynqMP: model CRF and APU control
* Fix compile issues on modern Solaris

# gpg: Signature made Fri 18 Mar 2022 13:18:20 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20220318' of https://git.linaro.org/people/pmaydell/qemu-arm: (21 commits)
util/osdep: Remove some early cruft
hw/i386/acpi-build: Avoid 'sun' identifier
util/osdep: Avoid madvise proto on modern Solaris
hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control
hw/misc: Add a model of the Xilinx ZynqMP APU Control
hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF
hw/misc: Add a model of the Xilinx ZynqMP CRF
target/arm: Make rvbar settable after realize
hw/arm/xlnx-zynqmp: Add an unimplemented SERDES area
target/arm: Log fault address for M-profile faults
target/arm: Log M-profile vector table accesses
hw/arm/virt: Fix gic-version=max when CONFIG_ARM_GICV3_TCG is unset
hw/intc: Rename CONFIG_ARM_GIC_TCG into CONFIG_ARM_GICV3_TCG
nsis installer: Fix mouse-over descriptions for emulators
nsis installer: Suppress "ANSI targets are deprecated" warning
nsis installer: List emulators in alphabetical order
hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init()
hw/dma/xlnx_csu_dma: Set TYPE_XLNX_CSU_DMA class_size
target/arm: Fix handling of LPAE block descriptors
target/arm: Fix pauth_check_trap vs SEL2
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

hw/intc: Rename CONFIG_ARM_GIC_TCG into CONFIG_ARM_GICV3_TCG

CONFIG_ARM_GIC_TCG actually guards the compilation of TCG GICv3
specific files. So let's rename it into CONFIG_ARM_GICV3_TCG

Signed-off-

hw/intc: Rename CONFIG_ARM_GIC_TCG into CONFIG_ARM_GICV3_TCG

CONFIG_ARM_GIC_TCG actually guards the compilation of TCG GICv3
specific files. So let's rename it into CONFIG_ARM_GICV3_TCG

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id: 20220308182452.223473-2-eric.auger@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20220303' into staging

Fifth RISC-V PR for QEMU 7.0

* Fixup checks for ext_zb[abcs]
* Add AIA support for virt machine
* I

Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20220303' into staging

Fifth RISC-V PR for QEMU 7.0

* Fixup checks for ext_zb[abcs]
* Add AIA support for virt machine
* Increase maximum number of CPUs in virt machine
* Fixup OpenTitan SPI address
* Add support for zfinx, zdinx and zhinx{min} extensions

# gpg: Signature made Thu 03 Mar 2022 05:26:55 GMT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20220303:
target/riscv: expose zfinx, zdinx, zhinx{min} properties
target/riscv: add support for zhinx/zhinxmin
target/riscv: add support for zdinx
target/riscv: add support for zfinx
target/riscv: hardwire mstatus.FS to zero when enable zfinx
target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}
hw: riscv: opentitan: fixup SPI addresses
hw/riscv: virt: Increase maximum number of allowed CPUs
docs/system: riscv: Document AIA options for virt machine
hw/riscv: virt: Add optional AIA IMSIC support to virt machine
hw/intc: Add RISC-V AIA IMSIC device emulation
hw/riscv: virt: Add optional AIA APLIC support to virt machine
target/riscv: fix inverted checks for ext_zb[abcs]

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...