Revision tags: v9.2.0, v9.1.2, v9.1.1 |
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#
b5ab62b3 |
| 04-Oct-2024 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* pc: Add a description for the i8042 property * kvm: support for nested FRED * tests/unit: fix warning when compiling test-n
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* pc: Add a description for the i8042 property * kvm: support for nested FRED * tests/unit: fix warning when compiling test-nested-aio-poll with LTO * kvm: refactoring of VM creation * target/i386: expose IBPB-BRTYPE and SBPB CPUID bits to the guest * hw/char: clean up serial * remove virtfs-proxy-helper * target/i386/kvm: Report which action failed in kvm_arch_put/get_registers * qom: improvements to object_resolve_path*()
# -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmb++MsUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroPVnwf/cdvfxvDm22tEdlh8vHlV17HtVdcC # Hw334M/3PDvbTmGzPBg26lzo4nFS6SLrZ8ETCeqvuJrtKzqVk9bI8ssZW5KA4ijM # nkxguRPHO8E6U33ZSucc+Hn56+bAx4I2X80dLKXJ87OsbMffIeJ6aHGSEI1+fKVh # pK7q53+Y3lQWuRBGhDIyKNuzqU4g+irpQwXOhux63bV3ADadmsqzExP6Gmtl8OKM # DylPu1oK7EPZumlSiJa7Gy1xBqL4Rc4wGPNYx2RVRjp+i7W2/Y1uehm3wSBw+SXC # a6b7SvLoYfWYS14/qCF4cBL3sJH/0f/4g8ZAhDDxi2i5kBr0/5oioDyE/A== # =/zo4 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 03 Oct 2024 21:04:27 BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (23 commits) qom: update object_resolve_path*() documentation qom: set *ambiguous on all paths qom: rename object_resolve_path_type() "ambiguousp" target/i386/kvm: Report which action failed in kvm_arch_put/get_registers kvm: Allow kvm_arch_get/put_registers to accept Error** accel/kvm: refactor dirty ring setup minikconf: print error entirely on stderr 9p: remove 'proxy' filesystem backend driver hw/char: Extract serial-mm hw/char/serial.h: Extract serial-isa.h hw: Remove unused inclusion of hw/char/serial.h target/i386: Expose IBPB-BRTYPE and SBPB CPUID bits to the guest kvm: refactor core virtual machine creation into its own function kvm/i386: replace identity_base variable with a constant kvm/i386: refactor kvm_arch_init and split it into smaller functions kvm: replace fprintf with error_report()/printf() in kvm_init() kvm/i386: fix return values of is_host_cpu_intel() kvm/i386: make kvm_filter_msr() and related definitions private to kvm module hw/i386/pc: Add a description for the i8042 property tests/unit: remove block layer code from test-nested-aio-poll ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
# Conflicts: # hw/arm/Kconfig # hw/arm/pxa2xx.c
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#
7e6b5497 |
| 05-Sep-2024 |
Bernhard Beschow <shentey@gmail.com> |
hw/char: Extract serial-mm
hw/char/serial currently contains the implementation of both TYPE_SERIAL and TYPE_SERIAL_MM. According to serial_class_init(), TYPE_SERIAL is an internal class while TYPE_
hw/char: Extract serial-mm
hw/char/serial currently contains the implementation of both TYPE_SERIAL and TYPE_SERIAL_MM. According to serial_class_init(), TYPE_SERIAL is an internal class while TYPE_SERIAL_MM is used by numerous machine types directly. Let's move the latter into its own module which makes the dependencies more obvious and the code more tidy.
The includes and the dependencies have been converted mechanically except in the hw/char directories which were updated manually. The result was compile-tested. Now, only hw/char makes direct use of TYPE_SERIAL:
# grep -r -e "select SERIAL" | grep -v SERIAL_ hw/char/Kconfig: select SERIAL hw/char/Kconfig: select SERIAL hw/char/Kconfig: select SERIAL hw/char/Kconfig: select SERIAL hw/char/Kconfig: select SERIAL
# grep -r -e "/serial\\.h" include/hw/char/serial-mm.h:#include "hw/char/serial.h" hw/char/serial-pci-multi.c:#include "hw/char/serial.h" hw/char/serial.c:#include "hw/char/serial.h" hw/char/serial-isa.c:#include "hw/char/serial.h" hw/char/serial-pci.c:#include "hw/char/serial.h"
Tested-by: Andrew Jeffery <andrew@codeconstruct.com.au> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Link: https://lore.kernel.org/r/20240905073832.16222-4-shentey@gmail.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Revision tags: v9.1.0 |
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#
83baec64 |
| 25-Apr-2024 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'pull-target-arm-20240425' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * Implement FEAT_NMI and NMI support in the GICv3 * hw/dma: avoid apparent ov
Merge tag 'pull-target-arm-20240425' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * Implement FEAT_NMI and NMI support in the GICv3 * hw/dma: avoid apparent overflow in soc_dma_set_request * linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code * Add ResetType argument to Resettable hold and exit phase methods * Add RESET_TYPE_SNAPSHOT_LOAD ResetType * Implement STM32L4x5 USART
# -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmYqMhMZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3uVlD/47U3zYP33y4+wJcRScC0QI # jYd82jS7GhD5YP5QPrIEMaSbDwtYGi4Rez1taaHvZ2fWLg2gE973iixmTaM2mXCd # xPEqMsRXkFrQnC89K5/v9uR04AvHxoM8J2mD2OKnUT0RVBs38WxCUMLETBsD18/q # obs1RzDRhEs5BnwwPMm5HI1iQeVvDRe/39O3w3rZfA8DuqerrNOQWuJd43asHYjO # Gc1QzCGhALlXDoqk11IzjhJ7es8WbJ5XGvrSNe9QLGNJwNsu9oi1Ez+5WK2Eht9r # eRvGNFjH4kQY1YCShZjhWpdzU9KT0+80KLirMJFcI3vUztrYZ027/rMyKLHVOybw # YAqgEUELwoGVzacpaJg73f77uknKoXrfTH25DfoLX0yFCB35JHOPcjU4Uq1z1pfV # I80ZcJBDJ95mXPfyKLrO+0IyVBztLybufedK2aiH16waEGDpgsJv66FB2QRuQBYW # O0i6/4DEUZmfSpOmr8ct+julz7wCWSjbvo6JFWxzzxvD0M5T3AFKXZI244g1SMdh # LS8V7WVCVzVJ5mK8Ujp2fVaIIxiBzlXVZrQftWv5rhyDOiIIeP8pdekmPlI6p5HK # 3/2efzSYNL2UCDZToIq24El/3md/7vHR6DBfBT1/pagxWUstqqLgkJO42jQtTG0E # JY1cZ/EQY7cqXGrww8lhWA== # =WEsU # -----END PGP SIGNATURE----- # gpg: Signature made Thu 25 Apr 2024 03:36:03 AM PDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
* tag 'pull-target-arm-20240425' of https://git.linaro.org/people/pmaydell/qemu-arm: (37 commits) tests/qtest: Add tests for the STM32L4x5 USART hw/arm: Add the USART to the stm32l4x5 SoC hw/char/stm32l4x5_usart: Add options for serial parameters setting hw/char/stm32l4x5_usart: Enable serial read and write hw/char: Implement STM32L4x5 USART skeleton reset: Add RESET_TYPE_SNAPSHOT_LOAD docs/devel/reset: Update to new API for hold and exit phase methods hw, target: Add ResetType argument to hold and exit phase methods scripts/coccinelle: New script to add ResetType to hold and exit phases allwinner-i2c, adm1272: Use device_cold_reset() for software-triggered reset hw/misc: Don't special case RESET_TYPE_COLD in npcm7xx_clk, gcr linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code hw/dma: avoid apparent overflow in soc_dma_set_request hw/arm/virt: Enable NMI support in the GIC if the CPU has FEAT_NMI target/arm: Add FEAT_NMI to max hw/intc/arm_gicv3: Report the VINMI interrupt hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update() hw/intc/arm_gicv3: Implement NMI interrupt priority hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read() hw/intc/arm_gicv3: Add NMI handling CPU interface registers ...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
4fb37aea |
| 29-Mar-2024 |
Arnaud Minier <arnaud.minier@telecom-paris.fr> |
hw/char: Implement STM32L4x5 USART skeleton
Add the basic infrastructure (register read/write, type...) to implement the STM32L4x5 USART.
Also create different types for the USART, UART and LPUART
hw/char: Implement STM32L4x5 USART skeleton
Add the basic infrastructure (register read/write, type...) to implement the STM32L4x5 USART.
Also create different types for the USART, UART and LPUART of the STM32L4x5 to deduplicate code and enable the implementation of different behaviors depending on the type.
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240329174402.60382-2-arnaud.minier@telecom-paris.fr [PMM: update to new reset hold method signature; fixed a few checkpatch nits] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v8.0.0, v7.2.0, v7.0.0, v6.2.0 |
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ec397e90 |
| 01-Sep-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210901-2' into staging
First RISC-V PR for QEMU 6.2
- Add a config for Shakti UART - Fixup virt flash node - Don't overr
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210901-2' into staging
First RISC-V PR for QEMU 6.2
- Add a config for Shakti UART - Fixup virt flash node - Don't override users supplied ISA version - Fixup some CSR accesses - Use g_strjoinv() for virt machine PLIC string config - Fix an overflow in the SiFive CLINT - Add 64-bit register access helpers - Replace tcg_const_* with direct constant usage
# gpg: Signature made Wed 01 Sep 2021 03:08:48 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-20210901-2: (33 commits) target/riscv: Use {get,dest}_gpr for RVV target/riscv: Tidy trans_rvh.c.inc target/riscv: Use {get,dest}_gpr for RVD target/riscv: Use {get,dest}_gpr for RVF target/riscv: Use gen_shift_imm_fn for slli_uw target/riscv: Use {get,dest}_gpr for RVA target/riscv: Reorg csr instructions target/riscv: Fix hgeie, hgeip target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation target/riscv: Use {get, dest}_gpr for integer load/store target/riscv: Use get_gpr in branches target/riscv: Use extracts for sraiw and srliw target/riscv: Use DisasExtend in shift operations target/riscv: Add DisasExtend to gen_unary target/riscv: Move gen_* helpers for RVB target/riscv: Move gen_* helpers for RVM target/riscv: Use gen_arith for mulh and mulhu target/riscv: Remove gen_arith_div* target/riscv: Add DisasExtend to gen_arith* target/riscv: Introduce DisasExtend and new helpers ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v6.1.0 |
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46b3e254 |
| 31-Jul-2021 |
Vijai Kumar K <vijai@behindbytes.com> |
hw/char: Add config for shakti uart
Use a dedicated UART config(CONFIG_SHAKTI_UART) to select shakti uart.
Signed-off-by: Vijai Kumar K <vijai@behindbytes.com> Reviewed-by: Alistair Francis <alista
hw/char: Add config for shakti uart
Use a dedicated UART config(CONFIG_SHAKTI_UART) to select shakti uart.
Signed-off-by: Vijai Kumar K <vijai@behindbytes.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210731190229.137483-1-vijai@behindbytes.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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#
801f3db7 |
| 20-Jul-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/philmd/tags/kconfig-20210720' into staging
Kconfig patches queue
Various Kconfig patches collected during v6.1 development cycle.
# gpg: Signature made Tue 20
Merge remote-tracking branch 'remotes/philmd/tags/kconfig-20210720' into staging
Kconfig patches queue
Various Kconfig patches collected during v6.1 development cycle.
# gpg: Signature made Tue 20 Jul 2021 19:11:32 BST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd/tags/kconfig-20210720: hw/tricore: fix inclusion of tricore_testboard hw/ppc/Kconfig: Add dependency PEGASOS2 -> ATI_VGA hw/isa/vt82c686: Add missing Kconfig dependency (runtime error) hw/isa/vt82c686: Add missing Kconfig dependencies (build error) hw/pci-host/Kconfig: Add missing dependency MV64361 -> I8259 hw/ppc/Kconfig: Add missing dependency E500 -> DS1338 RTC hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines hw/riscv/Kconfig: Add missing dependency MICROCHIP_PFSOC -> SERIAL hw/arm/Kconfig: Add missing SDHCI symbol to FSL_IMX25 hw/arm/Kconfig: Remove unused DS1338 symbol from i.MX25 PDK Board hw/arm/Kconfig: Add missing dependency NPCM7XX -> SMBUS hw/ide/Kconfig: Add missing dependency PCI -> IDE_QDEV hw/i386/Kconfig: Add missing Kconfig dependency (runtime error) hw/acpi/Kconfig: Add missing Kconfig dependencies (build error) hw/acpi: Do not restrict ACPI core routines to x86 architecture hw/mips: Express dependencies of the Boston machine with Kconfig hw/mips: Add dependency MIPS_CPS -> MIPS_ITU
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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8cbb537e |
| 13-May-2021 |
Philippe Mathieu-Daudé <philmd@redhat.com> |
hw/riscv/Kconfig: Add missing dependency MICROCHIP_PFSOC -> SERIAL
Commit a8fb0a500a6 ("hw/char: Add Microchip PolarFire SoC MMUART emulation") added a dependency on the SERIAL model, but forgot to
hw/riscv/Kconfig: Add missing dependency MICROCHIP_PFSOC -> SERIAL
Commit a8fb0a500a6 ("hw/char: Add Microchip PolarFire SoC MMUART emulation") added a dependency on the SERIAL model, but forgot to add the Kconfig selector. Add the dependency to the MCHP_PFSOC_MMUART symbol to fix when building the MICROCHIP_PFSOC machine stand-alone:
/usr/bin/ld: libcommon.fa.p/hw_char_mchp_pfsoc_mmuart.c.o: in function `mchp_pfsoc_mmuart_create': hw/char/mchp_pfsoc_mmuart.c:79: undefined reference to `serial_mm_init'
Fixes: a8fb0a500a6 ("hw/char: Add Microchip PolarFire SoC MMUART emulation") Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210515173716.358295-7-philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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ff81439a |
| 17-Mar-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-6.0-pull-request' into staging
m68k pull request 20210315
Add m68k virt machine
# gpg: Signature made Mon 15 Mar 2021 20:41:51 GMT # gpg:
Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-6.0-pull-request' into staging
m68k pull request 20210315
Add m68k virt machine
# gpg: Signature made Mon 15 Mar 2021 20:41:51 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C
* remotes/vivier/tags/m68k-for-6.0-pull-request: m68k: add Virtual M68k Machine m68k: add a system controller m68k: add an interrupt controller hw/intc: add goldfish-pic hw/char: add goldfish-tty
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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8c6df16f |
| 12-Mar-2021 |
Laurent Vivier <laurent@vivier.eu> |
hw/char: add goldfish-tty
Implement the goldfish tty device as defined in
https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT
and based on the kerne
hw/char: add goldfish-tty
Implement the goldfish tty device as defined in
https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT
and based on the kernel driver code:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/tty/goldfish.c
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210312214145.2936082-2-laurent@vivier.eu>
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#
229a8345 |
| 08-Mar-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/renesas-20210306' into staging
Renesas patches queue
- MMU prototype cleanups - Clarify licenses - Fine-grained Kconfig entries for SH-4 dev
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/renesas-20210306' into staging
Renesas patches queue
- MMU prototype cleanups - Clarify licenses - Fine-grained Kconfig entries for SH-4 devices
# gpg: Signature made Sat 06 Mar 2021 15:30:46 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd-gitlab/tags/renesas-20210306: hw/sh4/sh7750_regs: Replace link to license by its full content hw/sh4: Remove now unused CONFIG_SH4 from Kconfig hw/pci-host: Introduce SH_PCI Kconfig entry hw/block: Introduce TC58128 eeprom Kconfig entry hw/timer: Introduce SH_TIMER Kconfig entry hw/char: Introduce SH_SCI Kconfig entry hw/intc: Introduce SH_INTC Kconfig entry hw/sh4: Add missing Kconfig dependency on SH7750 for the R2D board hw/sh4: Add missing license target/sh4: Remove unused definitions target/sh4: Let get_physical_address() use MMUAccessType access_type target/sh4: Remove unused 'int access_type' argument target/sh4: Replace magic value by MMUAccessType definitions target/sh4: Fix code style for checkpatch.pl
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
7ae5c8bb |
| 21-Feb-2021 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
hw/char: Introduce SH_SCI Kconfig entry
We want to be able to use the 'SH4' config for architecture specific features. Add more fine-grained selection by adding a CONFIG_SH_SCI selector for the SH4
hw/char: Introduce SH_SCI Kconfig entry
We want to be able to use the 'SH4' config for architecture specific features. Add more fine-grained selection by adding a CONFIG_SH_SCI selector for the SH4 serial controller.
Add the missing MAINTAINERS entries.
Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210222141514.2646278-5-f4bug@amsat.org>
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Revision tags: v5.2.0 |
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f00f57f3 |
| 13-Sep-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200910' into staging
This PR includes multiple fixes and features for RISC-V: - Fixes a bug in printing trap causes - Allo
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200910' into staging
This PR includes multiple fixes and features for RISC-V: - Fixes a bug in printing trap causes - Allows 16-bit writes to the SiFive test device. This fixes the failure to reboot the RISC-V virt machine - Support for the Microchip PolarFire SoC and Icicle Kit - A reafactor of RISC-V code out of hw/riscv
# gpg: Signature made Thu 10 Sep 2020 19:08:06 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-20200910: (30 commits) hw/riscv: Sort the Kconfig options in alphabetical order hw/riscv: Drop CONFIG_SIFIVE hw/riscv: Always build riscv_hart.c hw/riscv: Move sifive_test model to hw/misc hw/riscv: Move sifive_uart model to hw/char hw/riscv: Move riscv_htif model to hw/char hw/riscv: Move sifive_plic model to hw/intc hw/riscv: Move sifive_clint model to hw/intc hw/riscv: Move sifive_gpio model to hw/gpio hw/riscv: Move sifive_u_otp model to hw/misc hw/riscv: Move sifive_u_prci model to hw/misc hw/riscv: Move sifive_e_prci model to hw/misc hw/riscv: sifive_u: Connect a DMA controller hw/riscv: clint: Avoid using hard-coded timebase frequency hw/riscv: microchip_pfsoc: Hook GPIO controllers hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 hw/net: cadence_gem: Add a new 'phy-addr' property hw/riscv: microchip_pfsoc: Connect a DMA controller hw/dma: Add SiFive platform DMA controller emulation ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
# Conflicts: # hw/riscv/trace-events
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#
b609b7e3 |
| 03-Sep-2020 |
Bin Meng <bin.meng@windriver.com> |
hw/riscv: Move sifive_uart model to hw/char
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_
hw/riscv: Move sifive_uart model to hw/char
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_uart model to hw/char directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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#
70eb9f9c |
| 03-Sep-2020 |
Bin Meng <bin.meng@windriver.com> |
hw/riscv: Move riscv_htif model to hw/char
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move riscv_ht
hw/riscv: Move riscv_htif model to hw/char
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move riscv_htif model to hw/char directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-8-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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#
a8fb0a50 |
| 31-Aug-2020 |
Bin Meng <bin.meng@windriver.com> |
hw/char: Add Microchip PolarFire SoC MMUART emulation
Microchip PolarFire SoC MMUART is ns16550 compatible, with some additional registers. Create a simple MMUART model built on top of the existing
hw/char: Add Microchip PolarFire SoC MMUART emulation
Microchip PolarFire SoC MMUART is ns16550 compatible, with some additional registers. Create a simple MMUART model built on top of the existing ns16550 model.
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-6-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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#
d3449830 |
| 11-Jul-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/avr-port-20200711' into staging
8bit AVR port from Michael Rolnik.
Michael started to work on the AVR port few years ago [*] and kept improv
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/avr-port-20200711' into staging
8bit AVR port from Michael Rolnik.
Michael started to work on the AVR port few years ago [*] and kept improving the code over various series.
List of people who help him (in chronological order): - Richard Henderson - Sarah Harris and Edward Robbins - Philippe Mathieu-Daudé and Aleksandar Markovic - Pavel Dovgalyuk - Thomas Huth
[*] The oldest contribution I could find on the list is from 2016: https://lists.nongnu.org/archive/html/qemu-devel/2016-06/msg02985.html
Tests included:
$ avocado --show=app run -t arch:avr tests/acceptance/ Fetching asset from tests/acceptance/machine_avr6.py:AVR6Machine.test_freertos (1/1) tests/acceptance/machine_avr6.py:AVR6Machine.test_freertos: PASS (2.13 s) RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0 JOB TIME : 2.35 s
$ make check-qtest-avr TEST check-qtest-avr: tests/qtest/boot-serial-test TEST check-qtest-avr: tests/qtest/cdrom-test TEST check-qtest-avr: tests/qtest/device-introspect-test TEST check-qtest-avr: tests/qtest/machine-none-test TEST check-qtest-avr: tests/qtest/qmp-test TEST check-qtest-avr: tests/qtest/qmp-cmd-test TEST check-qtest-avr: tests/qtest/qom-test TEST check-qtest-avr: tests/qtest/test-hmp TEST check-qtest-avr: tests/qtest/qos-test
CI results: . https://cirrus-ci.com/build/5697049146425344 . https://gitlab.com/philmd/qemu/-/pipelines/165328058 . https://travis-ci.org/github/philmd/qemu/builds/705817933 . https://app.shippable.com/github/philmd/qemu/runs/822/summary/console
# gpg: Signature made Sat 11 Jul 2020 10:03:11 BST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd-gitlab/tags/avr-port-20200711: (32 commits) target/avr/disas: Fix store instructions display order target/avr/cpu: Fix $PC displayed address target/avr/cpu: Drop tlb_flush() in avr_cpu_reset() target/avr: Add section into QEMU documentation tests/acceptance: Test the Arduino MEGA2560 board tests/boot-serial: Test some Arduino boards (AVR based) hw/avr: Add limited support for some Arduino boards hw/avr: Add some ATmega microcontrollers hw/avr: Add support for loading ELF/raw binaries hw/misc: avr: Add limited support for power reduction device hw/timer: avr: Add limited support for 16-bit timer peripheral hw/char: avr: Add limited support for USART peripheral tests/machine-none: Add AVR support target/avr: Register AVR support with the rest of QEMU target/avr: Add support for disassembling via option '-d in_asm' target/avr: Initialize TCG register variables target/avr: Add instruction translation - CPU main translation function target/avr: Add instruction translation - MCU Control Instructions target/avr: Add instruction translation - Bit and Bit-test Instructions target/avr: Add instruction translation - Data Transfer Instructions ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v5.0.0 |
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#
429ca9d6 |
| 23-Jan-2020 |
Michael Rolnik <mrolnik@gmail.com> |
hw/char: avr: Add limited support for USART peripheral
These were designed to facilitate testing but should provide enough function to be useful in other contexts. Only a subset of the functions of
hw/char: avr: Add limited support for USART peripheral
These were designed to facilitate testing but should provide enough function to be useful in other contexts. Only a subset of the functions of each peripheral is implemented, mainly due to the lack of a standard way to handle electrical connections (like GPIO pins).
[AM: Remove word 'Atmel' from filenames and all elements of code] Suggested-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com> Signed-off-by: Michael Rolnik <mrolnik@gmail.com> Signed-off-by: Sarah Harris <S.E.Harris@kent.ac.uk> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [rth: Squash I/O size fix and file rename from f4bug] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com> Reviewed-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com> Signed-off-by: Thomas Huth <huth@tuxfamily.org> Message-Id: <20200705140315.260514-20-huth@tuxfamily.org>
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#
d88d5a38 |
| 23-Jun-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/renesas-hw-20200622' into staging
Renesas hardware patches
- Add a common entry for Renesas hardware in MAINTAINERS - Trivial SH4 cleanups -
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/renesas-hw-20200622' into staging
Renesas hardware patches
- Add a common entry for Renesas hardware in MAINTAINERS - Trivial SH4 cleanups - Add RX GDB simulator from Yoshinori Sato
The Renesas RX target emulation was added in commit c8c35e5f51, these patches complete the target by adding the hardware emulation.
Tests included:
$ avocado --show=app,console run -t arch:rx tests/acceptance/ Fetching asset from tests/acceptance/machine_rx_gdbsim.py:RxGdbSimMachine.test_uboot Fetching asset from tests/acceptance/machine_rx_gdbsim.py:RxGdbSimMachine.test_linux_sash (1/2) tests/acceptance/machine_rx_gdbsim.py:RxGdbSimMachine.test_uboot: console: U-Boot 2016.05-rc3-23705-ga1ef3c71cb-dirty (Feb 05 2019 - 21:56:06 +0900) PASS (0.26 s) (2/2) tests/acceptance/machine_rx_gdbsim.py:RxGdbSimMachine.test_linux_sash: console: Linux version 4.19.0+ (yo-satoh@yo-satoh-debian) (gcc version 9.0.0 20181105 (experimental) (GCC)) #137 Wed Feb 20 23:20:02 JST 2019 console: Built 1 zonelists, mobility grouping on. Total pages: 8128 console: Kernel command line: console: Dentry cache hash table entries: 4096 (order: 2, 16384 bytes) console: Inode-cache hash table entries: 2048 (order: 1, 8192 bytes) console: Memory: 14648K/32768K available (871K kernel code, 95K rwdata, 140K rodata, 96K init, 175K bss, 18120K reserved, 0K cma-reserved) console: NR_IRQS: 256 console: rx-cmt: used for periodic clock events console: clocksource: rx-tpu: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1274173631191 ns console: 96.00 BogoMIPS (lpj=480000) console: pid_max: default: 4096 minimum: 301 console: Mount-cache hash table entries: 1024 (order: 0, 4096 bytes) console: Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes) console: clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns console: clocksource: Switched to clocksource rx-tpu console: workingset: timestamp_bits=30 max_order=12 bucket_order=0 console: SuperH (H)SCI(F) driver initialized console: 88240.serial: ttySC0 at MMIO 0x88240 (irq = 215, base_baud = 0) is a sci console: console [ttySC0] enabled console: 88248.serial: ttySC1 at MMIO 0x88248 (irq = 219, base_baud = 0) is a sci console: random: get_random_bytes called from 0x01002e48 with crng_init=0 console: Freeing unused kernel memory: 96K console: This architecture does not have kernel memory protection. console: Run /sbin/init as init process console: Run /etc/init as init process console: Run /bin/init as init process console: Run /bin/sh as init process console: Sash command shell (version 1.1.1) console: /> printenv console: HOME=/ console: TERM=linux PASS (0.73 s) RESULTS : PASS 2 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0 JOB TIME : 1.47 s
CI results: . https://cirrus-ci.com/build/6140199509950464 . https://travis-ci.org/github/philmd/qemu/builds/700954881 . https://app.shippable.com/github/philmd/qemu/runs/812/summary/console
# gpg: Signature made Mon 22 Jun 2020 19:52:09 BST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd-gitlab/tags/renesas-hw-20200622: docs: Document the RX target BootLinuxConsoleTest: Test the RX GDB simulator hw/rx: Add RX GDB simulator hw/rx: Register R5F562N7 and R5F562N8 MCUs hw/rx: Honor -accel qtest hw/rx: RX62N microcontroller (MCU) hw/char: RX62N serial communication interface (SCI) hw/timer: RX62N compare match timer (CMT) hw/timer: RX62N 8-Bit timer (TMR) hw/intc: RX62N interrupt controller (ICUa) hw/timer/sh_timer: Remove unused 'qemu/timer.h' include hw/sh4: Extract timer definitions to 'hw/timer/tmu012.h' hw/sh4: Use MemoryRegion typedef MAINTAINERS: Add an entry for common Renesas peripherals MAINTAINERS: Cover sh_intc files in the R2D/Shix machine sections
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v4.2.0, v4.0.0, v4.0.0-rc1, v4.0.0-rc0 |
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#
645194c7 |
| 21-Jan-2019 |
Yoshinori Sato <ysato@users.sourceforge.jp> |
hw/char: RX62N serial communication interface (SCI)
This module supported only non FIFO type. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.p
hw/char: RX62N serial communication interface (SCI)
This module supported only non FIFO type. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200224141923.82118-17-ysato@users.sourceforge.jp> [PMD: Filled VMStateField for migration] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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#
27cb89d1 |
| 17-May-2019 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
Mostly bugfixes and cleanups, the most important being "megasas: fix mapped frame size" from Peter Lieven. In addition,
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
Mostly bugfixes and cleanups, the most important being "megasas: fix mapped frame size" from Peter Lieven. In addition, -realtime is marked as deprecated.
# gpg: Signature made Fri 17 May 2019 14:25:11 BST # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* remotes/bonzini/tags/for-upstream: (21 commits) hw/net/ne2000: Extract the PCI device from the chipset common code hw/char: Move multi-serial devices into separate file ioapic: allow buggy guests mishandling level-triggered interrupts to make progress build: don't build hardware objects with linux-user build: chardev is only needed for softmmu targets configure: qemu-ga is only needed with softmmu targets build: replace GENERATED_FILES by generated-files-y trace: only include trace-event-subdirs when they are needed sun4m: obey -vga none mips-fulong2e: obey -vga none hw/i386/acpi: Assert a pointer is not null BEFORE using it hw/i386/acpi: Add object_resolve_type_unambiguous to improve modularity hw/acpi/piix4: Move TYPE_PIIX4_PM to a public header memory: correct the comment to DIRTY_MEMORY_MIGRATION vl: fix -sandbox parsing crash when seccomp support is disabled hvf: Add missing break statement megasas: fix mapped frame size vl: Add missing descriptions to the VGA adapters list Declare -realtime as deprecated roms: assert if max rom size is less than the used size ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
d09ecd8c |
| 31-Mar-2019 |
Thomas Huth <thuth@redhat.com> |
hw/char: Move multi-serial devices into separate file
In our downstream distribution of QEMU, we'd like to ship the binary without the multi-serial PCI devices. To make this disablement easier, let'
hw/char: Move multi-serial devices into separate file
In our downstream distribution of QEMU, we'd like to ship the binary without the multi-serial PCI devices. To make this disablement easier, let's move the devices into a separate file and add a proper Kconfig- switch for these devices.
Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1554036028-31410-1-git-send-email-thuth@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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#
e56d931a |
| 08-Mar-2019 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream-kconfig' into staging
Initial Kconfig work, excluding ARM and MIPS
# gpg: Signature made Thu 07 Mar 2019 20:54:27 GMT # gpg:
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream-kconfig' into staging
Initial Kconfig work, excluding ARM and MIPS
# gpg: Signature made Thu 07 Mar 2019 20:54:27 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* remotes/bonzini/tags/for-upstream-kconfig: (54 commits) kconfig: add documentation .travis.yml: test that no-default-device builds do not regress xtensa-softmmu.mak: express dependencies with Kconfig unicore32-softmmu.mak: express dependencies with Kconfig sparc64-softmmu.mak: express dependencies with Kconfig sparc-softmmu.mak: express dependencies with Kconfig sh4-softmmu.mak: express dependencies with Kconfig s390x: express dependencies with Kconfig riscv-softmmu.mak: replace CONFIG_* with Kconfig "select" directives or1k-softmmu.mak: express dependencies with Kconfig nios2-softmmu.mak: express dependencies with Kconfig moxie-softmmu.mak: express dependencies with Kconfig microblaze-softmmu.mak: express dependencies with Kconfig m68k-softmmu.mak: express dependencies with Kconfig lm32-softmmu.mak: express dependencies with Kconfig hppa-softmmu.mak: express dependencies with Kconfig cris-softmmu.mak: express dependencies with Kconfig alpha-softmmu.mak: express dependencies with Kconfig ppc: Express dependencies of the embedded machines with kconfig ppc: Express dependencies of the Sam460EX machines with kconfig ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
b42075bb |
| 23-Jan-2019 |
Yang Zhong <yang.zhong@intel.com> |
virtio: express virtio dependencies with Kconfig
Signed-off-by: Yang Zhong <yang.zhong@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20190123065618.3520-42-yang.zhong@intel.com
virtio: express virtio dependencies with Kconfig
Signed-off-by: Yang Zhong <yang.zhong@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20190123065618.3520-42-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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#
a7e23159 |
| 23-Jan-2019 |
Paolo Bonzini <pbonzini@redhat.com> |
isa: express dependencies with kconfig
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Yang Zhong <yang.zhong@intel.com> Message-Id: <20190123065618.3520-36-yang.zhong@intel.com> R
isa: express dependencies with kconfig
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Yang Zhong <yang.zhong@intel.com> Message-Id: <20190123065618.3520-36-yang.zhong@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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