Revision tags: v5.2.0 |
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#
98e5d7a2 |
| 18-Nov-2020 |
Vikram Garhwal <fnu.vikram@xilinx.com> |
hw/net/can: Introduce Xilinx ZynqMP CAN controller
The Xilinx ZynqMP CAN controller is developed based on SocketCAN, QEMU CAN bus implementation. Bus connection and socketCAN connection for each CAN
hw/net/can: Introduce Xilinx ZynqMP CAN controller
The Xilinx ZynqMP CAN controller is developed based on SocketCAN, QEMU CAN bus implementation. Bus connection and socketCAN connection for each CAN module can be set through command lines.
Example for using single CAN: -object can-bus,id=canbus0 \ -machine xlnx-zcu102.canbus0=canbus0 \ -object can-host-socketcan,id=socketcan0,if=vcan0,canbus=canbus0
Example for connecting both CAN to same virtual CAN on host machine: -object can-bus,id=canbus0 -object can-bus,id=canbus1 \ -machine xlnx-zcu102.canbus0=canbus0 \ -machine xlnx-zcu102.canbus1=canbus1 \ -object can-host-socketcan,id=socketcan0,if=vcan0,canbus=canbus0 \ -object can-host-socketcan,id=socketcan1,if=vcan0,canbus=canbus1
To create virtual CAN on the host machine, please check the QEMU CAN docs: https://github.com/qemu/qemu/blob/master/docs/can.txt
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com> Message-id: 1605728926-352690-2-git-send-email-fnu.vikram@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
d3449830 |
| 11-Jul-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/avr-port-20200711' into staging
8bit AVR port from Michael Rolnik.
Michael started to work on the AVR port few years ago [*] and kept improv
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/avr-port-20200711' into staging
8bit AVR port from Michael Rolnik.
Michael started to work on the AVR port few years ago [*] and kept improving the code over various series.
List of people who help him (in chronological order): - Richard Henderson - Sarah Harris and Edward Robbins - Philippe Mathieu-Daudé and Aleksandar Markovic - Pavel Dovgalyuk - Thomas Huth
[*] The oldest contribution I could find on the list is from 2016: https://lists.nongnu.org/archive/html/qemu-devel/2016-06/msg02985.html
Tests included:
$ avocado --show=app run -t arch:avr tests/acceptance/ Fetching asset from tests/acceptance/machine_avr6.py:AVR6Machine.test_freertos (1/1) tests/acceptance/machine_avr6.py:AVR6Machine.test_freertos: PASS (2.13 s) RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0 JOB TIME : 2.35 s
$ make check-qtest-avr TEST check-qtest-avr: tests/qtest/boot-serial-test TEST check-qtest-avr: tests/qtest/cdrom-test TEST check-qtest-avr: tests/qtest/device-introspect-test TEST check-qtest-avr: tests/qtest/machine-none-test TEST check-qtest-avr: tests/qtest/qmp-test TEST check-qtest-avr: tests/qtest/qmp-cmd-test TEST check-qtest-avr: tests/qtest/qom-test TEST check-qtest-avr: tests/qtest/test-hmp TEST check-qtest-avr: tests/qtest/qos-test
CI results: . https://cirrus-ci.com/build/5697049146425344 . https://gitlab.com/philmd/qemu/-/pipelines/165328058 . https://travis-ci.org/github/philmd/qemu/builds/705817933 . https://app.shippable.com/github/philmd/qemu/runs/822/summary/console
# gpg: Signature made Sat 11 Jul 2020 10:03:11 BST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd-gitlab/tags/avr-port-20200711: (32 commits) target/avr/disas: Fix store instructions display order target/avr/cpu: Fix $PC displayed address target/avr/cpu: Drop tlb_flush() in avr_cpu_reset() target/avr: Add section into QEMU documentation tests/acceptance: Test the Arduino MEGA2560 board tests/boot-serial: Test some Arduino boards (AVR based) hw/avr: Add limited support for some Arduino boards hw/avr: Add some ATmega microcontrollers hw/avr: Add support for loading ELF/raw binaries hw/misc: avr: Add limited support for power reduction device hw/timer: avr: Add limited support for 16-bit timer peripheral hw/char: avr: Add limited support for USART peripheral tests/machine-none: Add AVR support target/avr: Register AVR support with the rest of QEMU target/avr: Add support for disassembling via option '-d in_asm' target/avr: Initialize TCG register variables target/avr: Add instruction translation - CPU main translation function target/avr: Add instruction translation - MCU Control Instructions target/avr: Add instruction translation - Bit and Bit-test Instructions target/avr: Add instruction translation - Data Transfer Instructions ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v5.0.0 |
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#
50486d63 |
| 23-Jan-2020 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
hw/avr: Add limited support for some Arduino boards
Arduino boards are build with AVR chipsets. Add some of these boards:
- Arduino Duemilanove - Arduino Uno - Arduino Mega
For more informat
hw/avr: Add limited support for some Arduino boards
Arduino boards are build with AVR chipsets. Add some of these boards:
- Arduino Duemilanove - Arduino Uno - Arduino Mega
For more information: https://www.arduino.cc/en/Main/Products https://store.arduino.cc/arduino-genuino/most-popular
[AM: Remove word 'Atmel' from filenames and all elements of code] Suggested-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Joaquin de Andres <me@xcancerberox.com.ar> [thuth: sysbus_init_child_obj() ==> object_initialize_child()] Signed-off-by: Thomas Huth <huth@tuxfamily.org> Message-Id: <20200705140315.260514-26-huth@tuxfamily.org>
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#
d88d5a38 |
| 23-Jun-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/renesas-hw-20200622' into staging
Renesas hardware patches
- Add a common entry for Renesas hardware in MAINTAINERS - Trivial SH4 cleanups -
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/renesas-hw-20200622' into staging
Renesas hardware patches
- Add a common entry for Renesas hardware in MAINTAINERS - Trivial SH4 cleanups - Add RX GDB simulator from Yoshinori Sato
The Renesas RX target emulation was added in commit c8c35e5f51, these patches complete the target by adding the hardware emulation.
Tests included:
$ avocado --show=app,console run -t arch:rx tests/acceptance/ Fetching asset from tests/acceptance/machine_rx_gdbsim.py:RxGdbSimMachine.test_uboot Fetching asset from tests/acceptance/machine_rx_gdbsim.py:RxGdbSimMachine.test_linux_sash (1/2) tests/acceptance/machine_rx_gdbsim.py:RxGdbSimMachine.test_uboot: console: U-Boot 2016.05-rc3-23705-ga1ef3c71cb-dirty (Feb 05 2019 - 21:56:06 +0900) PASS (0.26 s) (2/2) tests/acceptance/machine_rx_gdbsim.py:RxGdbSimMachine.test_linux_sash: console: Linux version 4.19.0+ (yo-satoh@yo-satoh-debian) (gcc version 9.0.0 20181105 (experimental) (GCC)) #137 Wed Feb 20 23:20:02 JST 2019 console: Built 1 zonelists, mobility grouping on. Total pages: 8128 console: Kernel command line: console: Dentry cache hash table entries: 4096 (order: 2, 16384 bytes) console: Inode-cache hash table entries: 2048 (order: 1, 8192 bytes) console: Memory: 14648K/32768K available (871K kernel code, 95K rwdata, 140K rodata, 96K init, 175K bss, 18120K reserved, 0K cma-reserved) console: NR_IRQS: 256 console: rx-cmt: used for periodic clock events console: clocksource: rx-tpu: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1274173631191 ns console: 96.00 BogoMIPS (lpj=480000) console: pid_max: default: 4096 minimum: 301 console: Mount-cache hash table entries: 1024 (order: 0, 4096 bytes) console: Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes) console: clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns console: clocksource: Switched to clocksource rx-tpu console: workingset: timestamp_bits=30 max_order=12 bucket_order=0 console: SuperH (H)SCI(F) driver initialized console: 88240.serial: ttySC0 at MMIO 0x88240 (irq = 215, base_baud = 0) is a sci console: console [ttySC0] enabled console: 88248.serial: ttySC1 at MMIO 0x88248 (irq = 219, base_baud = 0) is a sci console: random: get_random_bytes called from 0x01002e48 with crng_init=0 console: Freeing unused kernel memory: 96K console: This architecture does not have kernel memory protection. console: Run /sbin/init as init process console: Run /etc/init as init process console: Run /bin/init as init process console: Run /bin/sh as init process console: Sash command shell (version 1.1.1) console: /> printenv console: HOME=/ console: TERM=linux PASS (0.73 s) RESULTS : PASS 2 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0 JOB TIME : 1.47 s
CI results: . https://cirrus-ci.com/build/6140199509950464 . https://travis-ci.org/github/philmd/qemu/builds/700954881 . https://app.shippable.com/github/philmd/qemu/runs/812/summary/console
# gpg: Signature made Mon 22 Jun 2020 19:52:09 BST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd-gitlab/tags/renesas-hw-20200622: docs: Document the RX target BootLinuxConsoleTest: Test the RX GDB simulator hw/rx: Add RX GDB simulator hw/rx: Register R5F562N7 and R5F562N8 MCUs hw/rx: Honor -accel qtest hw/rx: RX62N microcontroller (MCU) hw/char: RX62N serial communication interface (SCI) hw/timer: RX62N compare match timer (CMT) hw/timer: RX62N 8-Bit timer (TMR) hw/intc: RX62N interrupt controller (ICUa) hw/timer/sh_timer: Remove unused 'qemu/timer.h' include hw/sh4: Extract timer definitions to 'hw/timer/tmu012.h' hw/sh4: Use MemoryRegion typedef MAINTAINERS: Add an entry for common Renesas peripherals MAINTAINERS: Cover sh_intc files in the R2D/Shix machine sections
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v4.2.0, v4.0.0, v4.0.0-rc1, v4.0.0-rc0 |
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#
0c80f50f |
| 21-Jan-2019 |
Yoshinori Sato <ysato@users.sourceforge.jp> |
hw/rx: RX62N microcontroller (MCU)
rx62n - RX62N cpu.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Philippe Mathieu-
hw/rx: RX62N microcontroller (MCU)
rx62n - RX62N cpu.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> [PMD: Use TYPE_RX62N_CPU, use #define for RX62N_NR_TMR/CMT/SCI, renamed CPU -> MCU, device -> microcontroller] Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200224141923.82118-18-ysato@users.sourceforge.jp> [PMD: Rebased on b77b5b3dc7, split of machine, use &error_abort] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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#
b80bfaad |
| 13-Dec-2019 |
Andrew Jeffery <andrew@aj.id.au> |
hw: Introduce models for IBM's Flexible Service Interface
Firstly, I'll split this patch up in the future, but wanted to get the integrated setup sent out for any initial thoughts. Anyway:
Time for
hw: Introduce models for IBM's Flexible Service Interface
Firstly, I'll split this patch up in the future, but wanted to get the integrated setup sent out for any initial thoughts. Anyway:
Time for some fun with inter-processor buses. FSI allows a service processor access to the internal busses of a host POWER processor to perform configuration or debugging.
FSI has long existed in POWER processes and so comes with some baggage, including how it has been integrated into the ASPEED SoC.
Working backwards from the POWER processor, the fundamental pieces of interest for the implementation are:
1. The Common FRU Access Macro (CFAM), an address space containing various "engines" that drive accesses on busses internal and external to the POWER chip. Examples include the SBEFIFO and I2C masters. The engines hang off of an internal Local Bus (LBUS) which is described by the CFAM configuration block.
2. The FSI slave: The slave is the terminal point of the FSI bus for FSI symbols addressed to it. Slaves can be cascaded off of one another. The slave's configuration registers appear in address space of the CFAM to which it is attached.
3. The FSI master: A controller in the platform service processor (e.g. BMC) driving CFAM engine accesses into the POWER chip. At the hardware level FSI is a bit-based protocol supporting synchronous and DMA-driven accesses of engines in a CFAM.
4. The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in POWER processors. This now makes an appearance in the ASPEED SoC due to tight integration of the FSI master IP with the OPB, mainly the existence of an MMIO-mapping of the CFAM address straight onto a sub-region of the OPB address space.
5. An APB-to-OPB bridge enabling access to the OPB from the ARM core in the AST2600. Hardware limitations prevent the OPB from being directly mapped into APB, so all accesses are indirect through the bridge.
The implementation appears as following in the qemu device tree:
(qemu) info qtree bus: main-system-bus type System ... dev: aspeed.apb2opb, id "" gpio-out "sysbus-irq" 1 mmio 000000001e79b000/0000000000001000 bus: opb.1 type opb dev: fsi.master, id "" bus: fsi.bus.1 type fsi.bus dev: cfam.config, id "" dev: cfam, id "" bus: lbus.1 type lbus dev: scratchpad, id "" address = 0 (0x0) bus: opb.0 type opb dev: fsi.master, id "" bus: fsi.bus.0 type fsi.bus dev: cfam.config, id "" dev: cfam, id "" bus: lbus.0 type lbus dev: scratchpad, id "" address = 0 (0x0)
The LBUS is modelled to maintain the qdev bus hierarchy and to take advantage of the object model to automatically generate the CFAM configuration block. The configuration block presents engines in the order they are attached to the CFAM's LBUS. Engine implementations should subclass the LBusDevice and set the 'config' member of LBusDeviceClass to match the engine's type.
CFAM designs offer a lot of flexibility, for instance it is possible for a CFAM to be simultaneously driven from multiple FSI links. The modeling is not so complete; it's assumed that each CFAM is attached to a single FSI slave (as a consequence the CFAM subclasses the FSI slave).
As for FSI, its symbols and wire-protocol are not modelled at all. This is not necessary to get FSI off the ground thanks to the mapping of the CFAM address space onto the OPB address space - the models follow this directly and map the CFAM memory region into the OPB's memory region. Future work includes supporting more advanced accesses that drive the FSI master directly rather than indirectly via the CFAM mapping, which will require implementing the FSI state machine and methods for each of the FSI symbols on the slave. Further down the track we can also look at supporting the bitbanged SoftFSI drivers in Linux by extending the FSI slave model to resolve sequences of GPIO IRQs into FSI symbols, and calling the associated symbol method on the slave to map the access onto the CFAM.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
aceeaa69 |
| 17-Dec-2019 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2019-12-17' into staging
* Removal of the deprecated bluetooth code * Some qtest and misc patches
# gpg: Signature made Tue 17 De
Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2019-12-17' into staging
* Removal of the deprecated bluetooth code * Some qtest and misc patches
# gpg: Signature made Tue 17 Dec 2019 08:09:08 GMT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* remotes/huth-gitlab/tags/pull-request-2019-12-17: tests: use g_test_rand_int tests/Makefile: Fix check-report.* targets shown in check-help glib: use portable g_setenv() hw/misc/ivshmem: Bury dead legacy INTx code pseries: disable migration-test if /dev/kvm cannot be used tests: fix modules-test 'duplicate test case' error Remove libbluetooth / bluez from the CI tests Remove the core bluetooth code hw/usb: Remove the USB bluetooth dongle device hw/arm/nseries: Replace the bluetooth chardev with a "null" chardev
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
1d4ffe8d |
| 20-Nov-2019 |
Thomas Huth <thuth@redhat.com> |
Remove the core bluetooth code
It's been deprecated since QEMU v3.1. We've explicitly asked in the deprecation message that people should speak up on qemu-devel in case they are still actively using
Remove the core bluetooth code
It's been deprecated since QEMU v3.1. We've explicitly asked in the deprecation message that people should speak up on qemu-devel in case they are still actively using the bluetooth part of QEMU, but nobody ever replied that they are really still using it.
I've tried it on my own to use this bluetooth subsystem for one of my guests, but I was also not able to get it running anymore: When I was trying to pass-through a real bluetooth device, either the guest did not see the device at all, or the guest crashed.
Even worse for the emulated device: When running
qemu-system-x86_64 -bt device:keyboard
QEMU crashes once you hit a key.
So it seems like the bluetooth stack is not only neglected, it is completely bitrotten, as far as I can tell. The only attention that this code got during the past years were some CVEs that have been spotted there. So this code is a burden for the developers, without any real benefit anymore. Time to remove it.
Note: hw/bt/Kconfig only gets cleared but not removed here yet. Otherwise there is a problem with the *-softmmu/config-devices.mak.d dependency files - they still contain a reference to this file which gets evaluated first on some build hosts, before the file gets properly recreated. To avoid breaking these builders, we still need the file around for some time. It will get removed in a couple of weeks instead.
Message-Id: <20191120091014.16883-4-thuth@redhat.com> Reviewed-by: Ján Tomko <jtomko@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
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#
f724de8d |
| 29-Oct-2019 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/vivier/tags/q800-branch-pull-request' into staging
Add Macintosh Quadra 800 machine in hw/m68k
# gpg: Signature made Mon 28 Oct 2019 18:14:25 GMT # gpg:
Merge remote-tracking branch 'remotes/vivier/tags/q800-branch-pull-request' into staging
Add Macintosh Quadra 800 machine in hw/m68k
# gpg: Signature made Mon 28 Oct 2019 18:14:25 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C
* remotes/vivier/tags/q800-branch-pull-request: BootLinuxConsoleTest: Test the Quadra 800 hw/m68k: define Macintosh Quadra 800 hw/m68k: add a dummy SWIM floppy controller hw/m68k: add Nubus macfb video card hw/m68k: add Nubus support hw/m68k: implement ADB bus support for via hw/m68k: add VIA support dp8393x: manage big endian bus esp: add pseudo-DMA as used by Macintosh esp: move get_cmd() post-DMA code to get_cmd_cb() esp: move handle_ti_cmd() cleanup code to esp_do_dma().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
fa2ba3b8 |
| 26-Oct-2019 |
Laurent Vivier <laurent@vivier.eu> |
hw/m68k: add Nubus support
This patch adds basic support for the NuBus bus. This is used by 680x0 Macintosh.
Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Ca
hw/m68k: add Nubus support
This patch adds basic support for the NuBus bus. This is used by 680x0 Macintosh.
Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <huth@tuxfamily.org> Message-Id: <20191026164546.30020-8-laurent@vivier.eu>
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#
bad76ac3 |
| 25-Oct-2019 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-pull-request' into staging
Fix typos and docs, trivial changes and RTC devices split
# gpg: Signature made Fri 25 Oct 2019 09:35:02
Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-pull-request' into staging
Fix typos and docs, trivial changes and RTC devices split
# gpg: Signature made Fri 25 Oct 2019 09:35:02 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C
* remotes/vivier2/tags/trivial-branch-pull-request: hw/rtc/aspeed_rtc: Remove unused includes hw/rtc/xlnx-zynqmp-rtc: Remove unused "ptimer.h" include hw/rtc/mc146818: Include mc146818rtc_regs.h a bit less hw: Move Aspeed RTC from hw/timer/ to hw/rtc/ subdirectory hw: Move Exynos4210 RTC from hw/timer/ to hw/rtc/ subdirectory hw: Move Xilinx ZynqMP RTC from hw/timer/ to hw/rtc/ subdirectory hw: Move DS1338 device from hw/timer/ to hw/rtc/ subdirectory hw: Move TWL92230 device from hw/timer/ to hw/rtc/ subdirectory hw: Move sun4v hypervisor RTC from hw/timer/ to hw/rtc/ subdirectory hw: Move M41T80 device from hw/timer/ to hw/rtc/ subdirectory hw: Move M48T59 device from hw/timer/ to hw/rtc/ subdirectory hw: Move MC146818 device from hw/timer/ to hw/rtc/ subdirectory hw: Move PL031 device from hw/timer/ to hw/rtc/ subdirectory hw/timer: Compile devices not target-dependent as common object qemu-timer: reuse MIN macro in qemu_timeout_ns_to_ms event_notifier: avoid dandling file descriptor in event_notifier_cleanup util/async: avoid useless cast pci_bridge: fix a typo in comment qemu-options.hx: Update for reboot-timeout parameter
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
# Conflicts: # hw/timer/trace-events
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#
877c181c |
| 03-Oct-2019 |
Philippe Mathieu-Daudé <philmd@redhat.com> |
hw: Move PL031 device from hw/timer/ to hw/rtc/ subdirectory
The PL031 is a Real Time Clock, not a timer. Move it under the hw/rtc/ subdirectory.
Reviewed-by: Alistair Francis <alistair.francis@wdc
hw: Move PL031 device from hw/timer/ to hw/rtc/ subdirectory
The PL031 is a Real Time Clock, not a timer. Move it under the hw/rtc/ subdirectory.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20191003230404.19384-3-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
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#
6ce8733e |
| 10-Sep-2019 |
Andrew Jeffery <andrew@aj.id.au> |
hw: Introduce models for IBM's Flexible Service Interface
Firstly, I'll split this patch up in the future, but wanted to get the integrated setup sent out for any initial thoughts. Anyway:
Time for
hw: Introduce models for IBM's Flexible Service Interface
Firstly, I'll split this patch up in the future, but wanted to get the integrated setup sent out for any initial thoughts. Anyway:
Time for some fun with inter-processor buses. FSI allows a service processor access to the internal busses of a host POWER processor to perform configuration or debugging.
FSI has long existed in POWER processes and so comes with some baggage, including how it has been integrated into the ASPEED SoC.
Working backwards from the POWER processor, the fundamental pieces of interest for the implementation are:
1. The Common FRU Access Macro (CFAM), an address space containing various "engines" that drive accesses on busses internal and external to the POWER chip. Examples include the SBEFIFO and I2C masters. The engines hang off of an internal Local Bus (LBUS) which is described by the CFAM configuration block.
2. The FSI slave: The slave is the terminal point of the FSI bus for FSI symbols addressed to it. Slaves can be cascaded off of one another. The slave's configuration registers appear in address space of the CFAM to which it is attached.
3. The FSI master: A controller in the platform service processor (e.g. BMC) driving CFAM engine accesses into the POWER chip. At the hardware level FSI is a bit-based protocol supporting synchronous and DMA-driven accesses of engines in a CFAM.
4. The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in POWER processors. This now makes an appearance in the ASPEED SoC due to tight integration of the FSI master IP with the OPB, mainly the existence of an MMIO-mapping of the CFAM address straight onto a sub-region of the OPB address space.
5. An APB-to-OPB bridge enabling access to the OPB from the ARM core in the AST2600. Hardware limitations prevent the OPB from being directly mapped into APB, so all accesses are indirect through the bridge.
The implementation appears as following in the qemu device tree:
(qemu) info qtree bus: main-system-bus type System ... dev: aspeed.apb2opb, id "" gpio-out "sysbus-irq" 1 mmio 000000001e79b000/0000000000001000 bus: opb.1 type opb dev: fsi.master, id "" bus: fsi.bus.1 type fsi.bus dev: cfam.config, id "" dev: cfam, id "" bus: lbus.1 type lbus dev: scratchpad, id "" address = 0 (0x0) bus: opb.0 type opb dev: fsi.master, id "" bus: fsi.bus.0 type fsi.bus dev: cfam.config, id "" dev: cfam, id "" bus: lbus.0 type lbus dev: scratchpad, id "" address = 0 (0x0)
The LBUS is modelled to maintain the qdev bus hierarchy and to take advantage of the object model to automatically generate the CFAM configuration block. The configuration block presents engines in the order they are attached to the CFAM's LBUS. Engine implementations should subclass the LBusDevice and set the 'config' member of LBusDeviceClass to match the engine's type.
CFAM designs offer a lot of flexibility, for instance it is possible for a CFAM to be simultaneously driven from multiple FSI links. The modeling is not so complete; it's assumed that each CFAM is attached to a single FSI slave (as a consequence the CFAM subclasses the FSI slave).
As for FSI, its symbols and wire-protocol are not modelled at all. This is not necessary to get FSI off the ground thanks to the mapping of the CFAM address space onto the OPB address space - the models follow this directly and map the CFAM memory region into the OPB's memory region. Future work includes supporting more advanced accesses that drive the FSI master directly rather than indirectly via the CFAM mapping, which will require implementing the FSI state machine and methods for each of the FSI symbols on the slave. Further down the track we can also look at supporting the bitbanged SoftFSI drivers in Linux by extending the FSI slave model to resolve sequences of GPIO IRQs into FSI symbols, and calling the associated symbol method on the slave to map the access onto the CFAM.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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17dc5799 |
| 20-Aug-2019 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2019-08-20' into staging
- Improvements for the Kconfig switches and Makefiles
# gpg: Signature made Tue 20 Aug 2019 08:26:41 BST
Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2019-08-20' into staging
- Improvements for the Kconfig switches and Makefiles
# gpg: Signature made Tue 20 Aug 2019 08:26:41 BST # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* remotes/huth-gitlab/tags/pull-request-2019-08-20: hw/core: Add a config switch for the generic loader device hw/misc: Add a config switch for the "unimplemented" device hw/core: Add a config switch for the "split-irq" device hw/core: Add a config switch for the "or-irq" device hw/core: Add a config switch for the "register" device hw/dma: Do not build the xlnx_dpdma device for the MicroBlaze machines hw/intc: Only build the xlnx-iomod-intc device for the MicroBlaze PMU hw/Kconfig: Move the generic XLNX_ZYNQMP to the root hw/Kconfig
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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883e150f |
| 14-May-2019 |
Thomas Huth <thuth@redhat.com> |
hw/core: Add a config switch for the "register" device
The "register" device is only used by certain machines. Let's add a proper config switch for it so that it only gets compiled when we really ne
hw/core: Add a config switch for the "register" device
The "register" device is only used by certain machines. Let's add a proper config switch for it so that it only gets compiled when we really need it.
Message-Id: <20190817101931.28386-5-thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
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193d78a1 |
| 27-Apr-2019 |
Philippe Mathieu-Daudé <philmd@redhat.com> |
hw/Kconfig: Move the generic XLNX_ZYNQMP to the root hw/Kconfig
The XLNX_ZYNQMP config is used in multiple subdirectories (timer, intc). Move it to the root hw/Kconfig.
Signed-off-by: Philippe Math
hw/Kconfig: Move the generic XLNX_ZYNQMP to the root hw/Kconfig
The XLNX_ZYNQMP config is used in multiple subdirectories (timer, intc). Move it to the root hw/Kconfig.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190427141459.19728-2-philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
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8c1ecb59 |
| 28-May-2019 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-next-280519-2' into staging
Various testing updates
- semihosting re-factor (used in system tests) - aarch64 and alpha system tes
Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-next-280519-2' into staging
Various testing updates
- semihosting re-factor (used in system tests) - aarch64 and alpha system tests - editorconfig tweak for .S - some docker image updates - iotests clean-up (without make check inclusion)
# gpg: Signature made Tue 28 May 2019 17:26:34 BST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44
* remotes/stsquad/tags/pull-testing-next-280519-2: (27 commits) tests/qemu-iotests: re-format output to for make check-block tests/qemu-iotests/group: Re-use the "auto" group for tests that can always run Makefile.target: support per-target coverage reports Makefile: include per-target build directories in coverage report Makefile: fix coverage-report reference to BUILD_DIR .travis.yml: enable aarch64-softmmu and alpha-softmmu tcg tests tests/tcg/alpha: add system boot.S tests/tcg/multiarch: expand system memory test to cover more tests/tcg/minilib: support %c format char tests/tcg/multiarch: move the system memory test tests/tcg/aarch64: add system boot.S editorconfig: add settings for .s/.S files tests/tcg/multiarch: add hello world system test tests/tcg/multiarch: add support for multiarch system tests tests/docker: Test more components on the Fedora default image tests/docker: add ubuntu 18.04 MAINTAINERS: update for semihostings new home target/mips: convert UHI_plog to use common semihosting code target/mips: only build mips-semi for softmmu target/arm: correct return values for WRITE/READ in arm-semi ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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16932bb7 |
| 13-May-2019 |
Alex Bennée <alex.bennee@linaro.org> |
semihosting: introduce CONFIG_SEMIHOSTING
There isn't much point building semihosting for platforms that don't support it. Introduce a new symbol and enable it only for the softmmu targets that need
semihosting: introduce CONFIG_SEMIHOSTING
There isn't much point building semihosting for platforms that don't support it. Introduce a new symbol and enable it only for the softmmu targets that need it.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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84bdc58c |
| 28-Mar-2019 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
* Kconfig improvements (msi_nonbroken, imply for default PCI devices) * intel-iommu: sharing passthrough FlatViews (Pete
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
* Kconfig improvements (msi_nonbroken, imply for default PCI devices) * intel-iommu: sharing passthrough FlatViews (Peter) * Fix for SEV with VFIO (Brijesh) * Allow compilation without CONFIG_PARALLEL (Thomas)
# gpg: Signature made Thu 21 Mar 2019 16:42:24 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* remotes/bonzini/tags/for-upstream: (23 commits) virtio-vga: only enable for specific boards config-all-devices.mak: rebuild on reconfigure minikconf: fix parser typo intel-iommu: optimize nodmar memory regions test-announce-self: convert to qgraph hw/alpha/Kconfig: DP264 hardware requires e1000 network card hw/hppa/Kconfig: Dino board requires e1000 network card hw/sh4/Kconfig: r2d machine requires the rtl8139 network card hw/ppc/Kconfig: e500 based machines require virtio-net-pci device hw/ppc/Kconfig: Bamboo machine requires e1000 network card hw/mips/Kconfig: Fulong 2e board requires ati-vga/rtl8139 PCI devices hw/mips/Kconfig: Malta machine requires the pcnet network card hw/i386/Kconfig: enable devices that can be created by default hw/isa/Kconfig: PIIX4 southbridge requires USB UHCI hw/isa/Kconfig: i82378 SuperIO requires PC speaker device prep: do not select I82374 hw/i386/Kconfig: PC uses I8257, not I82374 hw/char/parallel: Make it possible to compile also without CONFIG_PARALLEL target/i386: sev: Do not pin the ram device memory region memory: Fix the memory region type assignment order ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
# Conflicts: # hw/rdma/Makefile.objs # hw/riscv/sifive_plic.c
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d6c1bd4a |
| 14-Mar-2019 |
Paolo Bonzini <pbonzini@redhat.com> |
kconfig: add dependencies on CONFIG_MSI_NONBROKEN
For devices that require msi_init/msix_init to succeed, add a dependency on CONFIG_MSI_NONBROKEN. This will prevent those devices from appearing in
kconfig: add dependencies on CONFIG_MSI_NONBROKEN
For devices that require msi_init/msix_init to succeed, add a dependency on CONFIG_MSI_NONBROKEN. This will prevent those devices from appearing in a binary that cannot instantiate them.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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e56d931a |
| 08-Mar-2019 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream-kconfig' into staging
Initial Kconfig work, excluding ARM and MIPS
# gpg: Signature made Thu 07 Mar 2019 20:54:27 GMT # gpg:
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream-kconfig' into staging
Initial Kconfig work, excluding ARM and MIPS
# gpg: Signature made Thu 07 Mar 2019 20:54:27 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* remotes/bonzini/tags/for-upstream-kconfig: (54 commits) kconfig: add documentation .travis.yml: test that no-default-device builds do not regress xtensa-softmmu.mak: express dependencies with Kconfig unicore32-softmmu.mak: express dependencies with Kconfig sparc64-softmmu.mak: express dependencies with Kconfig sparc-softmmu.mak: express dependencies with Kconfig sh4-softmmu.mak: express dependencies with Kconfig s390x: express dependencies with Kconfig riscv-softmmu.mak: replace CONFIG_* with Kconfig "select" directives or1k-softmmu.mak: express dependencies with Kconfig nios2-softmmu.mak: express dependencies with Kconfig moxie-softmmu.mak: express dependencies with Kconfig microblaze-softmmu.mak: express dependencies with Kconfig m68k-softmmu.mak: express dependencies with Kconfig lm32-softmmu.mak: express dependencies with Kconfig hppa-softmmu.mak: express dependencies with Kconfig cris-softmmu.mak: express dependencies with Kconfig alpha-softmmu.mak: express dependencies with Kconfig ppc: Express dependencies of the embedded machines with kconfig ppc: Express dependencies of the Sam460EX machines with kconfig ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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9533dcdd |
| 23-Jan-2019 |
Paolo Bonzini <pbonzini@redhat.com> |
ptimer: express dependencies with Kconfig
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Yang Zhong <yang.zhong@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id:
ptimer: express dependencies with Kconfig
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Yang Zhong <yang.zhong@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20190123065618.3520-39-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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c3a98aa5 |
| 24-Jan-2019 |
Paolo Bonzini <pbonzini@redhat.com> |
kconfig: introduce CONFIG_TEST_DEVICES
Devices that are mostly used for testing purposes (for example in endianness-test) will be moved under a new symbol CONFIG_TEST_DEVICES that can be disabled in
kconfig: introduce CONFIG_TEST_DEVICES
Devices that are mostly used for testing purposes (for example in endianness-test) will be moved under a new symbol CONFIG_TEST_DEVICES that can be disabled in the default-configs file. This makes it easier to drop this code from QEMU if desirable.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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82f51817 |
| 23-Jan-2019 |
Paolo Bonzini <pbonzini@redhat.com> |
kconfig: introduce kconfig files
The Kconfig files were generated mostly with this script:
for i in `grep -ho CONFIG_[A-Z0-9_]* default-configs/* | sort -u`; do set fnord `git grep -lw $i --
kconfig: introduce kconfig files
The Kconfig files were generated mostly with this script:
for i in `grep -ho CONFIG_[A-Z0-9_]* default-configs/* | sort -u`; do set fnord `git grep -lw $i -- 'hw/*/Makefile.objs' ` shift if test $# = 1; then cat >> $(dirname $1)/Kconfig << EOF config ${i#CONFIG_} bool
EOF git add $(dirname $1)/Kconfig else echo $i $* fi done sed -i '$d' hw/*/Kconfig for i in hw/*; do if test -d $i && ! test -f $i/Kconfig; then touch $i/Kconfig git add $i/Kconfig fi done
Whenever a symbol is referenced from multiple subdirectories, the script prints the list of directories that reference the symbol. These symbols have to be added manually to the Kconfig files.
Kconfig.host and hw/Kconfig were created manually.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Yang Zhong <yang.zhong@intel.com> Message-Id: <20190123065618.3520-27-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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