| e0dd7af4 | 13-Sep-2023 |
Jayanth Othayoth <ojayanth@in.ibm.com> |
switch fmt::format to use std::format
fmt::format is supported in the c++ std. This will
help to remove fmt package dependency.
Change-Id: Ia3f5c607a348f062a0f112d5eae8b51ecc23fd37
Signed-off-by: J
switch fmt::format to use std::format
fmt::format is supported in the c++ std. This will
help to remove fmt package dependency.
Change-Id: Ia3f5c607a348f062a0f112d5eae8b51ecc23fd37
Signed-off-by: Jayanth Othayoth <ojayanth@in.ibm.com>
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| ee10eada | 05-Dec-2021 |
Jayanth Othayoth <ojayanth@in.ibm.com> |
P9: threadStopall procedure support
This procedure is used to stop all instruction in the threads
for the p9 feature enabled systems. Here following best case
approach. Like issue processor level st
P9: threadStopall procedure support
This procedure is used to stop all instruction in the threads
for the p9 feature enabled systems. Here following best case
approach. Like issue processor level stop all chip-op with
ignore hardware error mode. Since this function is used in
power-off/error path.
Tested: verified procedure on p9 based systems
Signed-off-by: Jayanth Othayoth <ojayanth@in.ibm.com>
Change-Id: I14af85340143d2383683d9fb823394b9ce7b56ca
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| db8d46c0 | 09-Oct-2021 |
Jayanth Othayoth <ojayanth@in.ibm.com> |
PHAL: enterMPIPL chip-op failure handling support
Added new enterMpReboot procedure for PHAL feature enabled
systems to support libphal library API based chip-op
failure handling
Existing enterMpRe
PHAL: enterMPIPL chip-op failure handling support
Added new enterMpReboot procedure for PHAL feature enabled
systems to support libphal library API based chip-op
failure handling
Existing enterMpReboot procedure moved to non PHAL enabled systems.
Tested:
- Poitive Path 3 processor config
Starting Start memory preserving reboot host0...
Starting memory preserving reboot
Enter MPIPL completed on proc(2)
Enter MPIPL completed on proc(3)
Enter MPIPL completed on proc(0)
Finished Start memory preserving reboot host0.
- Error Path:
- Forced proc2 SBE invalid state.
Journal data
SBE (/proc2) is not ready for chip-op: state(0x00000000)
PEL data:
"SBE_ERR_MSG": "SBE chip-op not allowed",
"Message": "chipop request failure reported by SBE",
"SRC6": [
"0x2A901",
"[0:15] chip position, [16:23] command class,
[24:31] command type"
]
},
Signed-off-by: Jayanth Othayoth <ojayanth@in.ibm.com>
Change-Id: Ie0cb5abffd5116d44edfbbeb2fe3d8408bfb73e2
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| 1a9a5a6a | 06-Oct-2021 |
Patrick Williams <patrick@stwcx.xyz> |
catch exceptions as const
Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
Change-Id: Ia8f2ae95679f98f2fc3f32239bbf3b3578c35888 |
| 785cf6a5 | 28-Jun-2021 |
Jayanth Othayoth <ojayanth@in.ibm.com> |
pdbg v3.3 related changes
Separate sbe api into new header libpdbg_sbe.h related
changes.
Signed-off-by: Jayanth Othayoth <ojayanth@in.ibm.com>
Change-Id: I9ec660067ddae0bcc61fde016aa764976263e5a4 |
| 63508a73 | 27-Oct-2020 |
Brad Bishop <bradleyb@fuzziesquirrel.com> |
fix compiler warnings
Fix a couple pedantic, format=, and unused-parameter warnings so we can
turn the warnings all the way up.
Change-Id: I7c6309e30147f54fc64ace99dc784fbd96c77c70
Signed-off-by: B
fix compiler warnings
Fix a couple pedantic, format=, and unused-parameter warnings so we can
turn the warnings all the way up.
Change-Id: I7c6309e30147f54fc64ace99dc784fbd96c77c70
Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
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| 285f73ef | 15-May-2020 |
Dhruvaraj Subhashchandran <dhruvaraj@in.ibm.com> |
Remove multithreading while calling enter_mpipl
libpdbg which implements the enter_mpipl is not thread-safe
so removing multithreading and creating processes.
Signed-off-by: Dhruvaraj Subhashchandr
Remove multithreading while calling enter_mpipl
libpdbg which implements the enter_mpipl is not thread-safe
so removing multithreading and creating processes.
Signed-off-by: Dhruvaraj Subhashchandran <dhruvaraj@in.ibm.com>
Change-Id: I5ca1ff2f203203b387486d9ed410eb4517443474
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| 5cb593ae | 12-Feb-2020 |
Jayanth Othayoth <ojayanth@in.ibm.com> |
Remove VCS workaround
The VCS workaround is only required on P9 DD1.0
Since this chip version is used only for initial
bring-up and not required now.
Signed-off-by: Jayanth Othayoth <ojayanth@in.ib
Remove VCS workaround
The VCS workaround is only required on P9 DD1.0
Since this chip version is used only for initial
bring-up and not required now.
Signed-off-by: Jayanth Othayoth <ojayanth@in.ibm.com>
Change-Id: I73592d5c2ae8c13782e27392d00b55f2a09e477d
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| 08fc264c | 17-Feb-2020 |
Dhruvaraj Subhashchandran <dhruvaraj@in.ibm.com> |
Add support for memory preserving reboot
Memory preserving reboot is executed when an error encountered
in the hypervisor. There are two SBE chip ops to be executed to
initiate and complete this reb
Add support for memory preserving reboot
Memory preserving reboot is executed when an error encountered
in the hypervisor. There are two SBE chip ops to be executed to
initiate and complete this reboot. The sbe_enter_mpipl chip op
initiates the powering off process and sbe_continue_mpipl restarts
the host in the memory preserving way.
Signed-off-by: Dhruvaraj Subhashchandran <dhruvaraj@in.ibm.com>
Change-Id: I5b40398921e3856645bb3f292e49a1de12659f7e
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| ed212d50 | 31-Jan-2020 |
Andrew Geissler <geissonator@yahoo.com> |
warm-reboot: ensure sbe start bit is 0
Cold reboots assume the SBE start bit (P9_CBS_REG, bit 0) will start out
with a value of 0. When the chassis power is cycled, this is a valid
assumption. Howev
warm-reboot: ensure sbe start bit is 0
Cold reboots assume the SBE start bit (P9_CBS_REG, bit 0) will start out
with a value of 0. When the chassis power is cycled, this is a valid
assumption. However, when doing a warm reboot (chassis power remains on)
this is not a valid assumption.
The SBE depends on seeing the 0->1 transition of this bit to know when
to start the host. To support warm reboots, ensure the bit starts at 0.
Signed-off-by: Andrew Geissler <geissonator@yahoo.com>
Change-Id: Iba80ee030ab6f7e7468e4a86cc00668f20f2348e
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| a5311abd | 12-Feb-2020 |
Jayanth Othayoth <ojayanth@in.ibm.com> |
Enable host debug procedure for all power version
Signed-off-by: Jayanth Othayoth <ojayanth@in.ibm.com>
Change-Id: I429ea10623029275f4dde49b49f603adfaa681c5 |
| f7d1c1db | 12-Feb-2020 |
Jayanth Othayoth <ojayanth@in.ibm.com> |
Enable cfam overrides procedure for all power versions
Signed-off-by: Jayanth Othayoth <ojayanth@in.ibm.com>
Change-Id: Ibe20d9407f69e31de7ea270f906a621a2bfb9668 |
| aa2030c2 | 26-Mar-2019 |
Anthony Wilson <wilsonan@us.ibm.com> |
cleanupPCIE: Catch file_error::Open exception
The bus that is read may only show up at certain
times, such as during poweron. It is not
a fatal error condition if the bus is not available.
So we wil
cleanupPCIE: Catch file_error::Open exception
The bus that is read may only show up at certain
times, such as during poweron. It is not
a fatal error condition if the bus is not available.
So we will let it get logged to the journal, but not
let it get committed in this case.
Tested: It was an intermittent failure, but ran
poweron/poweroff a few times and didn't see
the error pop up again.
Resolves: openbmc/openbmc#3510
Change-Id: I47629e5f27fb847aa0094f0757b1988f8e645ebc
Signed-off-by: Anthony Wilson <wilsonan@us.ibm.com>
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| a27263d4 | 05-Feb-2019 |
Matt Spinler <spinler@us.ibm.com> |
Don't create errors in cleanupPCIE
This code always just runs in the power off path, and at times it
may be called when power is already off. In that case the FSI
access would fail since the proces
Don't create errors in cleanupPCIE
This code always just runs in the power off path, and at times it
may be called when power is already off. In that case the FSI
access would fail since the processor won't have power, so just
catch the error and continue on.
Change-Id: Ic02b17875763b0540edaaec47ee19846f305db72
Signed-off-by: Matt Spinler <spinler@us.ibm.com>
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| 729521fe | 26-Oct-2018 |
Matt Spinler <spinler@us.ibm.com> |
In startHost, don't set bit 2 in scratch reg 8
This was keeping hostboot from using some default scratch
register settings.
Tested: Tested by HW team
Change-Id: I1290acbabfa785e67a6038a3aadb7ececd
In startHost, don't set bit 2 in scratch reg 8
This was keeping hostboot from using some default scratch
register settings.
Tested: Tested by HW team
Change-Id: I1290acbabfa785e67a6038a3aadb7ececd9e1f7a
Signed-off-by: Matt Spinler <spinler@us.ibm.com>
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| 59704841 | 07-Nov-2018 |
Anthony Wilson <wilsonan@us.ibm.com> |
p9: cleanupPcie: Run procedure on all CPUs
Procedure should be run on all of the master and
slave CPUs.
Change-Id: I323519b059cfbe14ccd6145e22b1bdae4fd3d476
Signed-off-by: Anthony Wilson <wilsonan@
p9: cleanupPcie: Run procedure on all CPUs
Procedure should be run on all of the master and
slave CPUs.
Change-Id: I323519b059cfbe14ccd6145e22b1bdae4fd3d476
Signed-off-by: Anthony Wilson <wilsonan@us.ibm.com>
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| 7052f71e | 07-Nov-2018 |
Anthony Wilson <wilsonan@us.ibm.com> |
p9: cleanupPcie: Correct line endings
Change-Id: Ia8c516ca1a4ceca46a88c9de72cd765e3b2884c2
Signed-off-by: Anthony Wilson <wilsonan@us.ibm.com> |
| f78d9042 | 01-Nov-2018 |
Patrick Venture <venture@google.com> |
add .clang-format
Add .clang-format for automatic style.
Change-Id: I6d240009370179b5b8f1f646b0476a059ec6aa85
Signed-off-by: Patrick Venture <venture@google.com> |
| e84b4ddb | 01-Nov-2018 |
Patrick Venture <venture@google.com> |
s/copyright char/(C)/g to make compiler happy
Compiler complaining about the copyright characters.
Change-Id: I6730a50a668899a33e9dfcc4accb67ee207a3f08
Signed-off-by: Patrick Venture <venture@googl
s/copyright char/(C)/g to make compiler happy
Compiler complaining about the copyright characters.
Change-Id: I6730a50a668899a33e9dfcc4accb67ee207a3f08
Signed-off-by: Patrick Venture <venture@google.com>
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| f0d958df | 24-Oct-2018 |
Anthony Wilson <wilsonan@us.ibm.com> |
Add cleanupPcie to openpower-proc-control
This disables the drivers and receiver in the
PCIE root control 1 register as follows:
BIT NAME VALUE
19 TP_RI_DC_B 0b0
2
Add cleanupPcie to openpower-proc-control
This disables the drivers and receiver in the
PCIE root control 1 register as follows:
BIT NAME VALUE
19 TP_RI_DC_B 0b0
20 TP_DI1_DC_B 0b0
21 TP_DI2_DC_B 0b0
This should be run on a power off.
Change-Id: I6e027260f78a3fc451a45832f6f9bcf9afc8c3b9
Signed-off-by: Anthony Wilson <wilsonan@us.ibm.com>
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| 6ebf5cac | 19-Sep-2017 |
spashabk-in <shakeebbk@in.ibm.com> |
Log istep info on watchdog timeout
1. SBE istep info (cfam 2809)
2. HB istep info (cfam 283C)
Change-Id: I67632c58fe1148b980791dc017e5c099107caae5
Signed-off-by: Shakeeb Pasha <shakeebbk@in.ibm.com> |
| a231ceb4 | 04-Oct-2017 |
Matt Spinler <spinler@us.ibm.com> |
Use all phosphor-dbus-interfaces errors
Remove the local error definitions and use the
ones in phosphor-dbus-interfaces instead as the ones
there suit our purposes and it simplifies this repository
Use all phosphor-dbus-interfaces errors
Remove the local error definitions and use the
ones in phosphor-dbus-interfaces instead as the ones
there suit our purposes and it simplifies this repository
to do so.
Change-Id: I18428c496914153270ecb181e7193acd0e386e97
Signed-off-by: Matt Spinler <spinler@us.ibm.com>
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| d1df1e27 | 17-Aug-2017 |
Andrew Geissler <andrewg@us.ibm.com> |
Boot from sbe side 0 when boot count is greater than 0
Recent code changes now decrement the boot count at
the start of every boot. The sbe side select design
is to boot from side 0 twice, then side
Boot from sbe side 0 when boot count is greater than 0
Recent code changes now decrement the boot count at
the start of every boot. The sbe side select design
is to boot from side 0 twice, then side 1 on the
last attempt. Now that the boot count is decremented
at the start of the boot (and the total boot count is 3),
the software needs to use side 0 when the boot count
is greater than or equal to 1.
Resolves openbmc/openbmc#2169
Change-Id: Ic08bed34d58de3d40b742ce52ca83627976d8fee
Signed-off-by: Andrew Geissler <andrewg@us.ibm.com>
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| 16e099a7 | 08-Jun-2017 |
Andrew Geissler <andrewg@us.ibm.com> |
Don't run vcs workaround on non-dd10 chips
The VCS workaround is only required (and only make sense)
on P9 DD1.0 based systems. This code does a check of the
chip level and does not run the workarou
Don't run vcs workaround on non-dd10 chips
The VCS workaround is only required (and only make sense)
on P9 DD1.0 based systems. This code does a check of the
chip level and does not run the workaround if the chip
is not DD1.0.
The code will continue to run some of the other workarounds
because although not required for non-dd10 chips, they
do no harm.
Resolves openbmc/openbmc#1695
Change-Id: I1409ca359ccff7b78a186211e4cd447cd753eda7
Signed-off-by: Andrew Geissler <andrewg@us.ibm.com>
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| 2548c7a3 | 18-May-2017 |
Andrew Geissler <andrewg@us.ibm.com> |
Set SBE seeprom boot side
The default side for the SBE to boot from is side 0, which
is indicated by a 0 in bit 17 of cfam 0x2808.
When the boot count goes to 1 (the last before giving up), the
sta
Set SBE seeprom boot side
The default side for the SBE to boot from is side 0, which
is indicated by a 0 in bit 17 of cfam 0x2808.
When the boot count goes to 1 (the last before giving up), the
start_host logic will switch over to side 1 for the SBE to
boot from.
Resolves openbmc/openbmc#1467
Change-Id: I61aa22939baa4cde38c8716429b6ca55f7c850bd
Signed-off-by: Andrew Geissler <andrewg@us.ibm.com>
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