| #
f78d9042 |
| 01-Nov-2018 |
Patrick Venture <venture@google.com> |
add .clang-format
Add .clang-format for automatic style.
Change-Id: I6d240009370179b5b8f1f646b0476a059ec6aa85
Signed-off-by: Patrick Venture <venture@google.com>
|
| #
f0d958df |
| 24-Oct-2018 |
Anthony Wilson <wilsonan@us.ibm.com> |
Add cleanupPcie to openpower-proc-control
This disables the drivers and receiver in the
PCIE root control 1 register as follows:
BIT NAME VALUE
19 TP_R
Add cleanupPcie to openpower-proc-control
This disables the drivers and receiver in the
PCIE root control 1 register as follows:
BIT NAME VALUE
19 TP_RI_DC_B 0b0
20 TP_DI1_DC_B 0b0
21 TP_DI2_DC_B 0b0
This should be run on a power off.
Change-Id: I6e027260f78a3fc451a45832f6f9bcf9afc8c3b9
Signed-off-by: Anthony Wilson <wilsonan@us.ibm.com>
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|
| #
6ebf5cac |
| 19-Sep-2017 |
spashabk-in <shakeebbk@in.ibm.com> |
Log istep info on watchdog timeout
1. SBE istep info (cfam 2809)
2. HB istep info (cfam 283C)
Change-Id: I67632c58fe1148b980791dc017e5c099107caae5
Signed-off-by: Shakeeb Pas
Log istep info on watchdog timeout
1. SBE istep info (cfam 2809)
2. HB istep info (cfam 283C)
Change-Id: I67632c58fe1148b980791dc017e5c099107caae5
Signed-off-by: Shakeeb Pasha <shakeebbk@in.ibm.com>
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|
| #
16e099a7 |
| 08-Jun-2017 |
Andrew Geissler <andrewg@us.ibm.com> |
Don't run vcs workaround on non-dd10 chips
The VCS workaround is only required (and only make sense)
on P9 DD1.0 based systems. This code does a check of the
chip level and does not
Don't run vcs workaround on non-dd10 chips
The VCS workaround is only required (and only make sense)
on P9 DD1.0 based systems. This code does a check of the
chip level and does not run the workaround if the chip
is not DD1.0.
The code will continue to run some of the other workarounds
because although not required for non-dd10 chips, they
do no harm.
Resolves openbmc/openbmc#1695
Change-Id: I1409ca359ccff7b78a186211e4cd447cd753eda7
Signed-off-by: Andrew Geissler <andrewg@us.ibm.com>
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|
| #
2548c7a3 |
| 18-May-2017 |
Andrew Geissler <andrewg@us.ibm.com> |
Set SBE seeprom boot side
The default side for the SBE to boot from is side 0, which
is indicated by a 0 in bit 17 of cfam 0x2808.
When the boot count goes to 1 (the last before
Set SBE seeprom boot side
The default side for the SBE to boot from is side 0, which
is indicated by a 0 in bit 17 of cfam 0x2808.
When the boot count goes to 1 (the last before giving up), the
start_host logic will switch over to side 1 for the SBE to
boot from.
Resolves openbmc/openbmc#1467
Change-Id: I61aa22939baa4cde38c8716429b6ca55f7c850bd
Signed-off-by: Andrew Geissler <andrewg@us.ibm.com>
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| #
0c0eeff6 |
| 28-Feb-2017 |
Matt Spinler <spinler@us.ibm.com> |
Add code to access P9 CFAM registers
Change-Id: Idd98d016f0d6a246b516b4850e887991c771ae16
Signed-off-by: Matt Spinler <spinler@us.ibm.com>
|