| #
3b59356a |
| 12-Oct-2023 |
Deepa Karthikeyan <deepakala.karthikeyan@ibm.com> |
PHAL:Fix missing clock diagnostic data during ipl
During the IPL process, the Chassis Power State D-Bus property is
updated once all services and targets within the Chassis Power On target
have been
PHAL:Fix missing clock diagnostic data during ipl
During the IPL process, the Chassis Power State D-Bus property is
updated once all services and targets within the Chassis Power On target
have been completed. During this specific timeframe, when the
"op-clock-data-logger@.service.in" initiates, it may fail to capture
clock data due to a failed check. This situation occurs because, even
though the chassis power is turned on, the D-Bus property does not
provide the precise status, resulting in a missed opportunity to record
informational clock data.
The "op-clock-data-logger@.service.in" service is already configured to
start after the "obmc-host-started@%i.target" and is set to conflict
with the "obmc-host-stop@%i.target." This design ensures that whenever
this method is invoked, the chassis power will always be in the ON
state. Therefore, there is no need to redundantly check the chassis
power state for being ON. Consequently, the redundant conditional
statement has been removed.
Tested and found the clock informational diagnostic data added after
every ipl.
Change-Id: I56e62467be14c6f203d163d86aa6a5fd748d0d85
Signed-off-by: Deepa Karthikeyan <deepakala.karthikeyan@ibm.com>
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| #
be14ec2d |
| 24-Mar-2023 |
Matt Spinler <spinler@us.ibm.com> |
Change daily clock log to informational severity
The event log was using a severity of Error, and because the PEL message
registry had a severity of Informational, phosphor-log-manager would
spit ou
Change daily clock log to informational severity
The event log was using a severity of Error, and because the PEL message
registry had a severity of Informational, phosphor-log-manager would
spit out a trace about how the severities mismatched every time the PEL
was created.
Change-Id: Ia7559a5c3cfdf6ad93277783bfd85cb639af25a0
Signed-off-by: Matt Spinler <spinler@us.ibm.com>
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| #
5ffe7fb7 |
| 09-Sep-2022 |
Jayanth Othayoth <ojayanth@in.ibm.com> |
PHAL: Added clock register data in the clock daily data logger
Informational log includes all the present clock register information
required for clock debug.
Tested:
"Clock0": "Functio
PHAL: Added clock register data in the clock daily data logger
Informational log includes all the present clock register information
required for clock debug.
Tested:
"Clock0": "Functional",
"Clock0 path": "/bmc0/i2c-0/oscrefclk0",
"Clock0_0x00": " 37 d0 40 03 00 bf 00 02",
"Clock0_0x08": " 01 00 00 00 00 00 21 0b",
"Clock0_0x10": " 17 12 01 00 30 24 04 72",
:: ::
"Clock0_0xe0": " 00 00 00 00 00 00 00 00",
"Clock0_0xe8": " 00 00 c1 00 00 00 00 00",
"Clock0_0xf0": " 00 00 00 00 00 00 00 00",
"Clock0_0xf8": " 00 00 00 00 00 00 00 00"
Signed-off-by: Jayanth Othayoth <ojayanth@in.ibm.com>
Change-Id: Ic536337f494febfa92162c0387cf2995e24e9b10
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| #
91bf93e0 |
| 09-Sep-2022 |
Jayanth Othayoth <ojayanth@in.ibm.com> |
PHAL: Added processor CFAM register data in the clock daily data logger
Informational log includes all the present processor CFAM register
information required for clock debug.
Tested:
"Proc0":
PHAL: Added processor CFAM register data in the clock daily data logger
Informational log includes all the present processor CFAM register
information required for clock debug.
Tested:
"Proc0": "Functional",
"Proc0 EC": "0x0000000020",
"Proc0 Location Code": "Ufcs-P0-C61",
"Proc0 REG 0x1007": "0x00200004",
"Proc0 REG 0x2804": "0x3c000020",
"Proc0 REG 0x2810": "0x80ff6007",
"Proc0 REG 0x2813": "0xefeeeeff",
"Proc0 REG 0x2814": "0x000000e4",
"Proc0 REG 0x2815": "0xc0000000",
"Proc0 REG 0x2816": "0xff000000",
"Proc0 REG 0x281d": "0x00000000",
"Proc0 REG 0x281e": "0x00000000",
Signed-off-by: Jayanth Othayoth <ojayanth@in.ibm.com>
Change-Id: I47289a7c95ca9e64598eb26bbb5b49bf4fc2b680
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| #
ed7fb7ae |
| 09-Sep-2022 |
Jayanth Othayoth <ojayanth@in.ibm.com> |
PHAL: clock daily data logger base infrastructure support
To support system clock issues debug added support to log clock
specific register information every 24 hours and report externally.
This co
PHAL: clock daily data logger base infrastructure support
To support system clock issues debug added support to log clock
specific register information every 24 hours and report externally.
This commit provides support to base infrastructure to log informational
logs every 24 hours and at the beginning of application start.
Tested:
"User Header": {
"Section Version": "1",
"Sub-section type": "0",
"Log Committed by": "0x2000",
"Subsystem": "CEC Hardware - Clock",
"Event Scope": "Entire Platform",
"Event Severity": "Informational Event",
"Event Type": "Miscellaneous, Informational Only",
"Action Flags": [
"Service Action Required",
"Report Externally",
"HMC Call Home"
],
"Host Transmission": "Not Sent",
"HMC Transmission": "Not Sent"
},
"Primary SRC": {
"Section Version": "1",
"Sub-section type": "1",
"Created by": "0x3000",
"SRC Version": "0x02",
"SRC Format": "0x55",
"Virtual Progress SRC": "False",
"I5/OS Service Event Bit": "False",
"Hypervisor Dump Initiated":"False",
"Backplane CCIN": "2E33",
"Terminate FW Error": "False",
"Deconfigured": "False",
"Guarded": "False",
"Error Details": {
"Message": "Informational error to house clock debug info"
},
"Valid Word Count": "0x09",
"Reference Code": "BD58300A",
"Hex Word 2": "00080055",
"Hex Word 3": "2E330010",
"Hex Word 4": "00000000",
"Hex Word 5": "00000000",
"Hex Word 6": "00000000",
"Hex Word 7": "00000000",
"Hex Word 8": "00000000",
"Hex Word 9": "00000000"
}
Signed-off-by: Jayanth Othayoth <ojayanth@in.ibm.com>
Change-Id: I91cffe17ffe7d38b1127f89e61484c597b9b378b
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