a0c724d3 | 16-Aug-2024 |
Patrick Williams <patrick@stwcx.xyz> |
clang-format: re-format for clang-18
clang-format-18 isn't compatible with the clang-format-17 output, so we need to reformat the code with the latest version. The way clang-18 handles lambda forma
clang-format: re-format for clang-18
clang-format-18 isn't compatible with the clang-format-17 output, so we need to reformat the code with the latest version. The way clang-18 handles lambda formatting also changed, so we have made changes to the organization default style format to better handle lambda formatting.
See I5e08687e696dd240402a2780158664b7113def0e for updated style. See Iea0776aaa7edd483fa395e23de25ebf5a6288f71 for clang-18 enablement.
Change-Id: I1d204ff0a167c43688f2217e9dee5504c71cd4f0 Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
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c62813d4 | 22-Aug-2023 |
Zane Shelley <zshelle@us.ibm.com> |
Odyssey PLL unlock analysis plugin
Signed-off-by: Zane Shelley <zshelle@us.ibm.com> Change-Id: Ia53910eecdcdeb836bd836039a509f00121a67f7 |
27dd6368 | 10-May-2023 |
Patrick Williams <patrick@stwcx.xyz> |
clang-format: copy latest and re-format
clang-format-16 has some backwards incompatible changes that require additional settings for best compatibility and re-running the formatter. Copy the latest
clang-format: copy latest and re-format
clang-format-16 has some backwards incompatible changes that require additional settings for best compatibility and re-running the formatter. Copy the latest .clang-format from the docs repository and reformat the repository.
Change-Id: I27b0d1357211259edb6ec2776924729052f238d6 Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
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51f8202c | 22-Feb-2023 |
Caleb Palmer <cnpalmer@us.ibm.com> |
Update DSTL_FIR callouts in the event of failure to analyze an OCMB
Change-Id: I40c17703ad032aa98f02b43d9cb321b7fc86fea3 Signed-off-by: Caleb Palmer <cnpalmer@us.ibm.com> |
d5fa9584 | 27-Feb-2023 |
Caleb Palmer <cnpalmer@us.ibm.com> |
Add initial RAS data files for Odyssey
Change-Id: I70a596dd364057a4ce555546c36cc8369764b785 Signed-off-by: Caleb Palmer <cnpalmer@us.ibm.com> |
b82cbf75 | 27-Jun-2022 |
Zane Shelley <zshelle@us.ibm.com> |
Update to clang-format-14
Required because the Jenkins CI tools have moved to v14.
Signed-off-by: Zane Shelley <zshelle@us.ibm.com> Change-Id: I3cf4df1b45325545a423bdcb810040724a598ec5 |
513f64aa | 15-Jun-2022 |
Zane Shelley <zshelle@us.ibm.com> |
Handling for host detected LPC timeout
For reasons not explained yet, hardware will not initiate an LPC timeout attention via NCU timeout FIR bit as we expected. When the host firmware detects an LP
Handling for host detected LPC timeout
For reasons not explained yet, hardware will not initiate an LPC timeout attention via NCU timeout FIR bit as we expected. When the host firmware detects an LPC timeout, it will manually set N1_LOCAL_FIR[61] to force a system checkstop. The service response for this bit will be to call out the hardware as if there was a hardware reported LPC timeout.
Signed-off-by: Zane Shelley <zshelle@us.ibm.com> Change-Id: I863e8aa3ef50a4b18b5106b3a45c4cf81b2c7808
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026e5a3f | 05-May-2022 |
Zane Shelley <zshelle@us.ibm.com> |
Avoid guarding on TOD interfaces errors
The error could be anywhere between the two processors in the interface. Fatally guarding the MDMT will cause system outage until service is done. Instead, do
Avoid guarding on TOD interfaces errors
The error could be anywhere between the two processors in the interface. Fatally guarding the MDMT will cause system outage until service is done. Instead, do not guard on the TOD interface errors to avoid outage.
Signed-off-by: Zane Shelley <zshelle@us.ibm.com> Change-Id: I446917bad985e5143657398b2fbadacf6e8c4a9d
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8f07b2e6 | 21-Apr-2022 |
Zane Shelley <zshelle@us.ibm.com> |
Add chip at fault to TOD secondary error callout list
The error could be anywhere between the chip at fault and the clock source chip. So both chips should be added to the callout list.
Signed-off-
Add chip at fault to TOD secondary error callout list
The error could be anywhere between the chip at fault and the clock source chip. So both chips should be added to the callout list.
Signed-off-by: Zane Shelley <zshelle@us.ibm.com> Change-Id: I2a9e9b7b03ea300fc8ea92fcbd41080737f862d7
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27a17a5b | 21-Feb-2022 |
Zane Shelley <zshelle@us.ibm.com> |
Hardware analysis support of TOD failures
Signed-off-by: Zane Shelley <zshelle@us.ibm.com> Change-Id: I8e2659cc832113e05c99b8dd091757bcab3dcdea |
3f363d4a | 10-Feb-2022 |
Zane Shelley <zshelle@us.ibm.com> |
callout rule for TOD fault analysis
This does not include actual callout support, just the rules when an callout is needed. The actual callouts will come in subsequent commits after adding support t
callout rule for TOD fault analysis
This does not include actual callout support, just the rules when an callout is needed. The actual callouts will come in subsequent commits after adding support to query the TOD configuration registers.
Signed-off-by: Zane Shelley <zshelle@us.ibm.com> Change-Id: I72c702a778e12ee20555f3e6dca77e0b6f023be7
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2fbd267e | 03-Feb-2022 |
Zane Shelley <zshelle@us.ibm.com> |
Better exception handling in the analyzer
Give the ability to continue creating a PEL with FFDC if there is an exception in the analysis portion of the analyzer.
Signed-off-by: Zane Shelley <zshell
Better exception handling in the analyzer
Give the ability to continue creating a PEL with FFDC if there is an exception in the analysis portion of the analyzer.
Signed-off-by: Zane Shelley <zshelle@us.ibm.com> Change-Id: I2de281a7c974cfc80779a861a12cb2b9c99e0491
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d195b716 | 26-Jan-2022 |
Zane Shelley <zshelle@us.ibm.com> |
Add support for TOD clock callouts
Signed-off-by: Zane Shelley <zshelle@us.ibm.com> Change-Id: I42726f6d1b036120fcfe217e6dd47be8dd6d927b |
cbd20fa3 | 21-Jan-2022 |
Zane Shelley <zshelle@us.ibm.com> |
RAS Data File updates for TOD fault errors
Signed-off-by: Zane Shelley <zshelle@us.ibm.com> Change-Id: I1b1e1a7690e294ab2569d0fad60fa215acc37479 |
e90b85dc | 17-Dec-2021 |
Zane Shelley <zshelle@us.ibm.com> |
plugin for LPC timeout callouts
Change-Id: I39fed3c1ba5a16283c33c5072479f24c9c69a208 Signed-off-by: Zane Shelley <zshelle@us.ibm.com> |
2c228cdc | 16-Dec-2021 |
Zane Shelley <zshelle@us.ibm.com> |
Add plugin function for PLL unlock clock callouts
Change-Id: Ic0e9c9d7fee7afb5a6534266ab011d9d41d9ca48 Signed-off-by: Zane Shelley <zshelle@us.ibm.com> |
15527a43 | 16-Dec-2021 |
Zane Shelley <zshelle@us.ibm.com> |
create PluginMap and plugin definition
Signed-off-by: Zane Shelley <zshelle@us.ibm.com> Change-Id: I1d4c9c59657f7c07f0fffdd6dc94d5d21033ff0a |