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Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36
# 5c93c4c7 26-Jun-2023 Andy Chiu <andy.chiu@sifive.com>

selftests: Test RISC-V Vector's first-use handler

This add a test to check if the kernel zero-initializes all V registers
after the first-use trap handler returns.

If V registers are not zero-initi

selftests: Test RISC-V Vector's first-use handler

This add a test to check if the kernel zero-initializes all V registers
after the first-use trap handler returns.

If V registers are not zero-initialized, then the test should fail one
out of several runs:

```
root@sifive-fpga:~# ./v_initval_nolibc
# vl = 256
not ok 1 detect stale values on v-regesters
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 4c 41 4e 47 3d 43 0 50 41 54 48 3d 2f 75 73
72 2f 6c 6f 63 61 6c 2f 73 62 69 6e 3a 2f 75 73
72 2f 6c 6f 63 61 6c 2f 62 69 6e 3a 2f 75 73 72
ff ff 81 0 0 0 0 0 0 0 0 0 0 0 0 0
```

Otherwise, the test passes without errors each run.

Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Björn Töpel <bjorn@rivosinc.com>
Link: https://lore.kernel.org/r/20230627015556.12329-3-andy.chiu@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

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Revision tags: v6.4, v6.1.35, v6.1.34, v6.1.33
# 7cf6198c 05-Jun-2023 Andy Chiu <andy.chiu@sifive.com>

selftests: Test RISC-V Vector prctl interface

This add a test for prctl interface that controls the use of userspace
Vector.

Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Link: https://lore.kerne

selftests: Test RISC-V Vector prctl interface

This add a test for prctl interface that controls the use of userspace
Vector.

Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Link: https://lore.kernel.org/r/20230605110724.21391-27-andy.chiu@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

show more ...