c68b12a9 | 02-Jan-2023 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
riscv: dts: renesas: rzfive-smarc-som: Enable OSTM nodes
Enable OSTM{1,2} nodes on RZ/Five SMARC SoM.
Note, OSTM{1,2} nodes are enabled in the RZ/G2UL SMARC SoM DTSI [0] hence deleting the disabled
riscv: dts: renesas: rzfive-smarc-som: Enable OSTM nodes
Enable OSTM{1,2} nodes on RZ/Five SMARC SoM.
Note, OSTM{1,2} nodes are enabled in the RZ/G2UL SMARC SoM DTSI [0] hence deleting the disabled nodes from RZ/Five SMARC SoM DTSI enables it here too as we include [0] in RZ/Five SMARC SoM DTSI.
[0] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230102222233.274021-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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40005cb6 | 15-Nov-2022 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C
Enable CANFD and I2C on RZ/Five SMARC EVK.
Note, these blocks are enabled in RZ/G2UL SMARC EVK DTSI [0] hence deleting these disabled nodes from
riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C
Enable CANFD and I2C on RZ/Five SMARC EVK.
Note, these blocks are enabled in RZ/G2UL SMARC EVK DTSI [0] hence deleting these disabled nodes from RZ/Five SMARC EVK DTSI enables them here too as we include [0] in RZ/Five SMARC EVK DTSI.
[0] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20221115105135.1180490-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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42d3345e | 15-Nov-2022 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU
Enable support for below blocks found on RZ/Five SMARC EVK SoC/SoM: - ADC - OPP - Thermal Zones - TSU
Note, these
riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU
Enable support for below blocks found on RZ/Five SMARC EVK SoC/SoM: - ADC - OPP - Thermal Zones - TSU
Note, these blocks are enabled in RZ/G2UL SMARC SoM DTSI [0] hence deleting these disabled nodes from RZ/Five SMARC SoM DTSI enables them here too as we include [0] in RZ/Five SMARC SoM DTSI.
[0] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20221115105135.1180490-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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4adb690a | 28-Oct-2022 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
Enable the minimal blocks required for booting the Renesas RZ/Five SMARC EVK with initramfs.
Below are the blocks which are enable
riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
Enable the minimal blocks required for booting the Renesas RZ/Five SMARC EVK with initramfs.
Below are the blocks which are enabled: - CPG - CPU0 - DDR (memory regions) - PINCTRL - PLIC - SCIF0
As we are reusing the RZ/G2UL SoC base DTSI [0], RZ/G2UL SMARC SoM [1] and carrier [2] board DTSIs which enables almost all the blocks supported by the RZ/G2UL SMARC EVK and whereas on RZ/Five SoC we will be gradually enabling the blocks hence the aliases for ETH/I2C are deleted and rest of the IP blocks are marked as disabled/deleted.
[0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi [1] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi [2] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20221028165921.94487-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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