| e77da13b | 07-Mar-2023 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: fix the mpfs' mailbox regs
The mailbox on PolarFire SoC should really have three reg properties,
not two. Without splitting into three sections, the system controller's
QSPI c
riscv: dts: microchip: fix the mpfs' mailbox regs
The mailbox on PolarFire SoC should really have three reg properties,
not two. Without splitting into three sections, the system controller's
QSPI cannot be accessed as it sits inside the current first range. The
driver & binding have been adapted to account for both two & three
ranges, so fix the dts too.
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| d9c36d01 | 25-Jan-2023 |
Conor Dooley <conor.dooley@microchip.com> |
Merge patch series "Add a devicetree for the Aldec PolarFire SoC TySoM"
As it says on the tin, add a DT for this board. It's been sitting on my
desk for a while, so may as well have it upstream...
Merge patch series "Add a devicetree for the Aldec PolarFire SoC TySoM"
As it says on the tin, add a DT for this board. It's been sitting on my
desk for a while, so may as well have it upstream...
The DT is only partially complete, as it needs the fabric content added.
Unfortunately, I don't have a reference design in RTL or SmartDesign
for it and therefore don't know what that fabric content is.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| f4e700fd | 15-Nov-2022 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: remove unused pcie clocks
The PCIe root port in the designs that ship with the PolarBerry and
M100PFSEVP are connected via one, not two Fabric Interface Controllers
(FIC). The
riscv: dts: microchip: remove unused pcie clocks
The PCIe root port in the designs that ship with the PolarBerry and
M100PFSEVP are connected via one, not two Fabric Interface Controllers
(FIC). The one at 0x20_0000_0000 is fic0, so remove the fic1 clocks from
the dt node.
The same clock provides both, so this is harmless but inaccurate.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| bdd28ab3 | 07-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: fix the icicle's #pwm-cells
\#pwm-cells for the Icicle kit's fabric PWM was incorrectly set to 2 &
blindly overridden by the (out of tree) driver anyway. The core can
support
riscv: dts: microchip: fix the icicle's #pwm-cells
\#pwm-cells for the Icicle kit's fabric PWM was incorrectly set to 2 &
blindly overridden by the (out of tree) driver anyway. The core can
support inverted operation, so update the entry to correctly report its
capabilities.
Fixes: 72560c6559b8 ("riscv: dts: microchip: add fpga fabric section to icicle kit")
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| d6105a8b | 25-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: fix memory node unit address for icicle
Evidently I forgot to update the unit address for the 38-bit cached
memory node when I changed the address in the reg property..
Update
riscv: dts: microchip: fix memory node unit address for icicle
Evidently I forgot to update the unit address for the 38-bit cached
memory node when I changed the address in the reg property..
Update it to match.
Fixes: 6c1193301791 ("riscv: dts: microchip: update memory configuration for v2022.10")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 0d814000 | 20-Oct-2022 |
Emil Renner Berthing <emil.renner.berthing@canonical.com> |
riscv: dts: microchip: icicle: Add GPIO controlled LEDs
Add the 4 GPIO controlled LEDs to the Microchip PolarFire-SoC Icicle
Kit device tree. The schematic doesn't specify any special function
for t
riscv: dts: microchip: icicle: Add GPIO controlled LEDs
Add the 4 GPIO controlled LEDs to the Microchip PolarFire-SoC Icicle
Kit device tree. The schematic doesn't specify any special function
for the LEDs, so they're added here without any default triggers and
named led1, led2, led3 and led4 just like in the schematic.
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| c210b918 | 20-Sep-2022 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: fix fabric i2c reg size
The size of the reg should've been changed when the address was changed,
but obviously I forgot to do so.
Fixes: ab291621a8b8 ("riscv: dts: microchip:
riscv: dts: microchip: fix fabric i2c reg size
The size of the reg should've been changed when the address was changed,
but obviously I forgot to do so.
Fixes: ab291621a8b8 ("riscv: dts: microchip: icicle: re-jig fabric peripheral addresses")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 6c119330 | 27-Sep-2022 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: update memory configuration for v2022.10
In the v2022.10 reference design, the seg registers are going to be
changed, resulting in a required change to the memory map in Linux
riscv: dts: microchip: update memory configuration for v2022.10
In the v2022.10 reference design, the seg registers are going to be
changed, resulting in a required change to the memory map in Linux.
A small 4M reservation is made at the end of 32-bit DDR to provide some
memory for the HSS to use, so that it can cache its payload.bin between
reboots of a specific context.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| d4916664 | 27-Sep-2022 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: add a devicetree for aries' m100pfsevp
Add device trees for both configs used by the Aries Embedded
M100PFSEVP. The M100OFSEVP consists of a MPFS250T on a SOM,
featuring:
- 2G
riscv: dts: microchip: add a devicetree for aries' m100pfsevp
Add device trees for both configs used by the Aries Embedded
M100PFSEVP. The M100OFSEVP consists of a MPFS250T on a SOM,
featuring:
- 2GB DDR4 SDRAM dedicated to the HMS
- 512MB DDR4 SDRAM dedicated to the FPGA
- 32 MB SPI NOR Flash
- 4 GByte eMMC
and a carrier board with:
- 2x Gigabit Ethernet
- USB
- 2x UART
- 2x CAN
- TFT connector
- HSMC extension connector
- 3x PMOD extension connectors
- microSD-card slot
Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-som-mpfs025t-pcie-serdes
Link: https://www.aries-embedded.com/evaluation-kit/fpga/polarfire-microchip-soc-fpga-m100pfsevp-riscv-hsmc-pmod
Link: https://downloads.aries-embedded.de/products/M100PFS/Hardware/M100PFSEVP-Schematics.pdf
Co-developed-by: Wolfgang Grandegger <wg@aries-embedded.de>
Signed-off-by: Wolfgang Grandegger <wg@aries-embedded.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 978a17d1 | 27-Sep-2022 |
Vattipalli Praveen <praveen.kumar@microchip.com> |
riscv: dts: microchip: add sevkit device tree
Add a basic dts for the Microchip Smart Embedded Vision dev kit.
The SEV kit is an upcoming first party board, featuring an MPFS250T and:
- Dual Sony Ca
riscv: dts: microchip: add sevkit device tree
Add a basic dts for the Microchip Smart Embedded Vision dev kit.
The SEV kit is an upcoming first party board, featuring an MPFS250T and:
- Dual Sony Camera Sensors (IMX334)
- IEEE 802.11 b/g/n 20MHz (1x1) Wi-Fi
- Bluetooth 5 Low Energy
- 4 GB DDR4 x64
- 2 GB LPDDR4 x32
- 1 GB SPI Flash
- 8 GB eMMC flash & SD card slot (multiplexed)
- HDMI2.0 Video Input/Output
- MIPI DSI Output
- MIPI CSI-2 Input
Link: https://onlinedocs.microchip.com/pr/GUID-404D3738-DC76-46BA-8683-6A77E837C2DD-en-US-1/index.html?GUID-065AEBEE-7B2C-4895-8579-B1D73D797F06
Signed-off-by: Vattipalli Praveen <praveen.kumar@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| fa52935a | 27-Sep-2022 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: reduce the fic3 clock rate
For the v2022.09 release of the reference design, the fic3 clock rate
been reduced from 62.5 MHz to 50 MHz as it allows timing to be closed
signific
riscv: dts: microchip: reduce the fic3 clock rate
For the v2022.09 release of the reference design, the fic3 clock rate
been reduced from 62.5 MHz to 50 MHz as it allows timing to be closed
significantly more quickly by customers who chose to build the
reference design themselves.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| ab291621 | 27-Sep-2022 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: icicle: re-jig fabric peripheral addresses
When users try to add onto the reference design, they find that the
current addresses that peripherals connected to Fabric InterConn
riscv: dts: microchip: icicle: re-jig fabric peripheral addresses
When users try to add onto the reference design, they find that the
current addresses that peripherals connected to Fabric InterConnect
(FIC) 3 use are restrictive. For the v2022.09 reference design, the
peripherals have been shifted down, leaving more contiguous address
space for their custom IP/peripherals.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 6fc655ed | 27-Sep-2022 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: icicle: update pci address properties
For the v2022.09 reference design the PCI root port's data region has
been moved to FIC1 from FIC0. This is a shorter path, allowing for
riscv: dts: microchip: icicle: update pci address properties
For the v2022.09 reference design the PCI root port's data region has
been moved to FIC1 from FIC0. This is a shorter path, allowing for
higher clock rates and improved through-put. As a result, the address at
which the PCIe's data region appears to the core complex has changed.
The config region's address is unchanged.
As FIC0 is no longer used, its clock can be removed too.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 99d451a7 | 27-Sep-2022 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi
In today's edition of moving things around:
The PCIe root port on PolarFire SoC is more part of the FPGA than of
the Core Complex. It
riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi
In today's edition of moving things around:
The PCIe root port on PolarFire SoC is more part of the FPGA than of
the Core Complex. It is located on the other side of the chip and,
apart from its interrupts, most of its configuration is determined
by the FPGA bitstream rather. This includes:
- address translation in both directions
- the addresses at which the config and data regions appear to the
core complex
- the clocks used by the AXI bus
- the plic interrupt used
Moving the PCIe node to the -fabric.dtsi makes it clearer than a
singular configuration for root port is not correct & allows the
base SoC dtsi to be more easily included.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| f890e67f | 27-Sep-2022 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: add pci dma ranges for the icicle kit
The recently removed, accidentally included, "matr0" property was used
in place of a dma-ranges property. The PCI controller is non-funct
riscv: dts: microchip: add pci dma ranges for the icicle kit
The recently removed, accidentally included, "matr0" property was used
in place of a dma-ranges property. The PCI controller is non-functional
with mainline Linux in the v2022.02 or later reference designs and has
not worked without configuration of address-translation since v2021.08.
Add the address translation that will be used by the v2022.09 reference
design & update the compatible used by the dts. Since this change is not
backwards compatible, update the compatible to denote this, jumping over
v2022.09 directly to v2022.10.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| e4009c5f | 19-Aug-2022 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: mpfs: remove pci axi address translation property
An AXI master address translation table property was inadvertently
added to the device tree & this was not caught by dtbs_che
riscv: dts: microchip: mpfs: remove pci axi address translation property
An AXI master address translation table property was inadvertently
added to the device tree & this was not caught by dtbs_check at the
time. Remove the property - it should not be in mpfs.dtsi anyway as
it would be more suitable in -fabric.dtsi nor does it actually apply
to the version of the reference design we are using for upstream.
Link: https://www.microsemi.com/document-portal/doc_download/1245812-polarfire-fpga-and-polarfire-soc-fpga-pci-express-user-guide # Section 1.3.3
Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 2b55915d | 19-Aug-2022 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: mpfs: remove bogus card-detect-delay
Recent versions of dt-schema warn about a previously undetected
undocumented property:
arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb:
riscv: dts: microchip: mpfs: remove bogus card-detect-delay
Recent versions of dt-schema warn about a previously undetected
undocumented property:
arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: mmc@20008000: Unevaluated properties are not allowed ('card-detect-delay' was unexpected)
From schema: Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
There are no GPIOs connected to MSSIO6B4 pin K3 so adding the common
cd-debounce-delay-ms property makes no sense. The Cadence IP has a
register that sets the card detect delay as "DP * tclk". On MPFS, this
clock frequency is not configurable (it must be 200 MHz) & the FPGA
comes out of reset with this register already set.
Fixes: bc47b2217f24 ("riscv: dts: microchip: add the sundance polarberry")
Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 72a05748 | 19-Aug-2022 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: microchip: mpfs: remove ti,fifo-depth property
Recent versions of dt-schema warn about a previously undetected
undocument property on the icicle & polarberry devicetrees:
arch/riscv/boo
riscv: dts: microchip: mpfs: remove ti,fifo-depth property
Recent versions of dt-schema warn about a previously undetected
undocument property on the icicle & polarberry devicetrees:
arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: ethernet@20112000: ethernet-phy@8: Unevaluated properties are not allowed ('ti,fifo-depth' was unexpected)
From schema: Documentation/devicetree/bindings/net/cdns,macb.yaml
I know what you're thinking, the binding doesn't look to be the problem
and I agree. I am not sure why a TI vendor property was ever actually
added since it has no meaning... just get rid of it.
Fixes: bc47b2217f24 ("riscv: dts: microchip: add the sundance polarberry")
Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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