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Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44 |
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f05af44f |
| 07-Aug-2023 |
John Watts <contact@jookia.org> |
riscv: dts: allwinner: d1: Add CAN controller nodes
The Allwinner D1, T113 provide two CAN controllers that are variants
of the R40 controller.
I have tested support for these controllers on two bo
riscv: dts: allwinner: d1: Add CAN controller nodes
The Allwinner D1, T113 provide two CAN controllers that are variants
of the R40 controller.
I have tested support for these controllers on two boards:
- A Lichee Panel RV 86 Panel running a D1 chip
- A Mango Pi MQ Dual running a T113-s3 chip
Both of these fully support both CAN controllers.
Signed-off-by: John Watts <contact@jookia.org>
Link: https://lore.kernel.org/r/20230807191952.2019208-1-contact@jookia.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
show more ...
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84059a0e |
| 07-Aug-2023 |
Marc Kleine-Budde <mkl@pengutronix.de> |
Revert "riscv: dts: allwinner: d1: Add CAN controller nodes"
It turned out the dtsi changes were not quite ready, revert them for
now.
This reverts commit 6ea1ad888f5900953a21853e709fa499fdfcb317.
Revert "riscv: dts: allwinner: d1: Add CAN controller nodes"
It turned out the dtsi changes were not quite ready, revert them for
now.
This reverts commit 6ea1ad888f5900953a21853e709fa499fdfcb317.
Link: https://lore.kernel.org/all/2690764.mvXUDI8C0e@jernej-laptop
Suggested-by: Jernej Škrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/all/20230807-riscv-allwinner-d1-revert-can-controller-nodes-v1-1-eb3f70b435d9@pengutronix.de
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
show more ...
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Revision tags: v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35 |
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d0d73ee5 |
| 19-Jun-2023 |
Maksim Kiselev <bigunclemax@gmail.com> |
riscv: dts: allwinner: d1: Add GPADC node
This patch adds declaration of the general purpose ADC for D1
and T113s SoCs.
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Acked-by: Jernej Skrabe
riscv: dts: allwinner: d1: Add GPADC node
This patch adds declaration of the general purpose ADC for D1
and T113s SoCs.
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20230619154252.3951913-5-bigunclemax@gmail.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
show more ...
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| #
6ea1ad88 |
| 21-Jul-2023 |
John Watts <contact@jookia.org> |
riscv: dts: allwinner: d1: Add CAN controller nodes
The Allwinner D1, T113 provide two CAN controllers that are variants
of the R40 controller.
I have tested support for these controllers on two bo
riscv: dts: allwinner: d1: Add CAN controller nodes
The Allwinner D1, T113 provide two CAN controllers that are variants
of the R40 controller.
I have tested support for these controllers on two boards:
- A Lichee Panel RV 86 Panel running a D1 chip
- A Mango Pi MQ Dual running a T113-s3 chip
Both of these fully support both CAN controllers.
Signed-off-by: John Watts <contact@jookia.org>
Link: https://lore.kernel.org/all/20230721221552.1973203-4-contact@jookia.org
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
show more ...
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Revision tags: v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28 |
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c1b2093d |
| 10-May-2023 |
Maksim Kiselev <bigunclemax@gmail.com> |
riscv: dts: allwinner: d1: Add SPI controllers node
Some boards form the MangoPi family (MQ\MQ-Dual\MQ-R) may have
an optional SPI flash that connects to the SPI0 controller.
This controller is the
riscv: dts: allwinner: d1: Add SPI controllers node
Some boards form the MangoPi family (MQ\MQ-Dual\MQ-R) may have
an optional SPI flash that connects to the SPI0 controller.
This controller is the same for R329/D1/R528/T113s SoCs and
should be supported by the sun50i-r329-spi driver.
So let's add its DT nodes.
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20230510081121.3463710-6-bigunclemax@gmail.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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Revision tags: v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21 |
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a140b18f |
| 21-Mar-2023 |
Cristian Ciocaltea <cristian.ciocaltea@collabora.com> |
riscv: dts: allwinner: d1: Switch dma-names order for snps,dw-apb-uart nodes
Commit 370f696e4474 ("dt-bindings: serial: snps-dw-apb-uart: add dma &
dma-names properties") documented dma-names proper
riscv: dts: allwinner: d1: Switch dma-names order for snps,dw-apb-uart nodes
Commit 370f696e4474 ("dt-bindings: serial: snps-dw-apb-uart: add dma &
dma-names properties") documented dma-names property to handle Allwinner
D1 dtbs_check warnings, but relies on the rx->tx ordering, which is the
reverse of what a bunch of different boards expect.
The initial proposed solution was to allow a flexible dma-names order in
the binding, due to potential ABI breakage concerns after fixing the DTS
files. But luckily the Allwinner boards are not affected, since they are
using a shared DMA channel for rx and tx.
Hence, the first step in fixing the inconsistency was to change
dma-names order in the binding to tx->rx.
Do the same for the snps,dw-apb-uart nodes in the DTS file.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230321215624.78383-7-cristian.ciocaltea@collabora.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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d30a28a7 |
| 21-Mar-2023 |
Cristian Ciocaltea <cristian.ciocaltea@collabora.com> |
riscv: dts: allwinner: d1: Switch dma-names order for snps,dw-apb-uart nodes
Commit 370f696e4474 ("dt-bindings: serial: snps-dw-apb-uart: add dma &
dma-names properties") documented dma-names proper
riscv: dts: allwinner: d1: Switch dma-names order for snps,dw-apb-uart nodes
Commit 370f696e4474 ("dt-bindings: serial: snps-dw-apb-uart: add dma &
dma-names properties") documented dma-names property to handle Allwinner
D1 dtbs_check warnings, but relies on the rx->tx ordering, which is the
reverse of what a bunch of different boards expect.
The initial proposed solution was to allow a flexible dma-names order in
the binding, due to potential ABI breakage concerns after fixing the DTS
files. But luckily the Allwinner boards are not affected, since they are
using a shared DMA channel for rx and tx.
Hence, the first step in fixing the inconsistency was to change
dma-names order in the binding to tx->rx.
Do the same for the snps,dw-apb-uart nodes in the DTS file.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230321215624.78383-7-cristian.ciocaltea@collabora.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
show more ...
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Revision tags: v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17 |
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| #
9ebdff9a |
| 31-Dec-2022 |
Samuel Holland <samuel@sholland.org> |
riscv: dts: allwinner: d1: Add crypto engine node
D1 contains a crypto engine which is supported by the sun8i-ce driver.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Jernej Skrabec
riscv: dts: allwinner: d1: Add crypto engine node
D1 contains a crypto engine which is supported by the sun8i-ce driver.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20221231220146.646-4-samuel@sholland.org
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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dca36f7b |
| 26-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: dts: allwinner: d1: Add power controller node
The Allwinner D1 family of SoCs contain a PPU power domain controller
separate from the PRCM. It can power down the video engine and DSP, and
it
riscv: dts: allwinner: d1: Add power controller node
The Allwinner D1 family of SoCs contain a PPU power domain controller
separate from the PRCM. It can power down the video engine and DSP, and
it contains special logic for hardware-assisted CPU idle.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20230126063419.15971-4-samuel@sholland.org
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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077e5f4f |
| 25-Jan-2023 |
Samuel Holland <samuel@sholland.org> |
riscv: dts: allwinner: Add the D1/D1s SoC devicetree
D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs based
on a single die, or at a pair of dies derived from the same design.
D1
riscv: dts: allwinner: Add the D1/D1s SoC devicetree
D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs based
on a single die, or at a pair of dies derived from the same design.
D1 and D1s contain a single T-HEAD Xuantie C906 CPU, whereas R528 and
T113 contain a pair of Cortex-A7's. D1 and R528 are the full version of
the chip with a BGA package, whereas D1s and T113 are low-pin-count QFP
variants.
Because the original design supported both ARM and RISC-V CPUs, some
peripherals are duplicated. In addition, all variants except D1s contain
a HiFi 4 DSP with its own set of peripherals.
The devicetrees are organized to minimize duplication:
- Common perhiperals are described in sunxi-d1s-t113.dtsi
- DSP-related peripherals are described in sunxi-d1-t113.dtsi
- RISC-V specific hardware is described in sun20i-d1s.dtsi
- Functionality unique to the D1 variant is described in sun20i-d1.dtsi
The SOC_PERIPHERAL_IRQ macro handles the different #interrupt-cells
values between the ARM (GIC) and RISC-V (PLIC) versions of the SoC.
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230126045738.47903-5-samuel@sholland.org
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
show more ...
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