arm64: dts: ti: k3-j721s2: Fix power domain for VTM node

[ Upstream commit 5ef196ed912e80a1e64936119ced8d7eb5635f0f ]

Fix the power domain device ID for wkup_vtm0 node.

Link: https://software-dl.t

arm64: dts: ti: k3-j721s2: Fix power domain for VTM node

[ Upstream commit 5ef196ed912e80a1e64936119ced8d7eb5635f0f ]

Fix the power domain device ID for wkup_vtm0 node.

Link: https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j721s2/devices.html
Fixes: d148e3fe52c8 ("arm64: dts: ti: j721s2: Add VTM node")
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20240201-b4-upstream-j721s2-fix-vtm-devid-v2-1-85fd568b77e3@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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arm64: dts: ti: k3-j721s2: Enable GPIO nodes at the board level

GPIO nodes defined in the top-level J721s2 SoC dtsi files are incomplete
and may not be functional unless they are extended with pinmu

arm64: dts: ti: k3-j721s2: Enable GPIO nodes at the board level

GPIO nodes defined in the top-level J721s2 SoC dtsi files are incomplete
and may not be functional unless they are extended with pinmux and
device information.

Disable the GPIO nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20230810003814.85450-10-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3: Add cfg reg region to ringacc node

Add register range of ringacc cfg node to all k3 SoC dtsi files. This is
normally under Device Management firmware control but some entities li

arm64: dts: ti: k3: Add cfg reg region to ringacc node

Add register range of ringacc cfg node to all k3 SoC dtsi files. This is
normally under Device Management firmware control but some entities like
bootloader have to access directly and thus required to be present in DT.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20230809175932.2553156-3-vigneshr@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: add missing space before {

Add missing whitespace between node name/label and opening {.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: David Lechn

arm64: dts: ti: add missing space before {

Add missing whitespace between node name/label and opening {.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: David Lechner <david@lechnology.com>
Link: https://lore.kernel.org/r/20230705145755.292927-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-j721s2: Fix wkup pinmux range

The WKUP_PADCONFIG register region in J721S2 has multiple non-addressable
regions, accordingly split the existing wkup_pmx region as follows to avoid

arm64: dts: ti: k3-j721s2: Fix wkup pinmux range

The WKUP_PADCONFIG register region in J721S2 has multiple non-addressable
regions, accordingly split the existing wkup_pmx region as follows to avoid
the non-addressable regions and include the rest of valid WKUP_PADCONFIG
registers. Also update references to old nodes with new ones.

wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12)
wkup_pmx1 -> 11 pins (WKUP_PADCONFIG 14 - 24)
wkup_pmx2 -> 72 pins (WKUP_PADCONFIG 26 - 97)
wkup_pmx3 -> 1 pin (WKUP_PADCONFIG 100)

Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC")
Cc: <stable@vger.kernel.org> # 6.3
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
Signed-off-by: Thejasvi Konduru <t-konduru@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230602153554.1571128-2-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-j721s2: Change CPTS clock parent

MAIN_PLL0 has a flag set in DM (Device Manager) that removes it's
capability to re-initialise clock frequencies. CPTS and RGMII has
MAIN_PLL3 as t

arm64: dts: ti: k3-j721s2: Change CPTS clock parent

MAIN_PLL0 has a flag set in DM (Device Manager) that removes it's
capability to re-initialise clock frequencies. CPTS and RGMII has
MAIN_PLL3 as their parent which does not have this flag. While RGMII
needs this reinitialisation to default frequency to be able to get
250MHz with its divider, CPTS can not get its required 200MHz with its
divider. Thus, move CPTS clock parent on J721S2 from MAIN_PLL3_HSDIV1 to
MAIN_PLL0_HSDIV6.

(Note: even GTC will be moved from MAIN_PLL3 to MAIN_PLL0 in U-Boot side
for the same reason)

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Link: https://lore.kernel.org/r/20230605110443.84568-1-n-francis@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-j721s2: Configure pinctrl for timer IO

There are timer IO pads in the MCU domain, and in the MAIN domain. These
pads can be muxed for the related timers.

The details of the multi

arm64: dts: ti: k3-j721s2: Configure pinctrl for timer IO

There are timer IO pads in the MCU domain, and in the MAIN domain. These
pads can be muxed for the related timers.

The details of the multiplexing can be found in the register
documentation and Technical Reference Manual[1].

These are similar to J721e/J7200, but have different mux capabilities.

[1] https://www.ti.com/lit/zip/spruj28

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20230531213215.602395-5-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-j721s2: Add general purpose timers

There are 20 general purpose timers on j721s2 that can be used for
things like PWM using pwm-omap-dmtimer driver. There are also
additional ten

arm64: dts: ti: k3-j721s2: Add general purpose timers

There are 20 general purpose timers on j721s2 that can be used for
things like PWM using pwm-omap-dmtimer driver. There are also
additional ten timers in the MCU domain which are meant for MCU
firmware usage and hence marked reserved by default.

Though the count is similar to J721e/J7200, the device IDs and clocks
used in j721s2 are different with the option of certain clocks having
options of additional clock muxes. Since there is very minimal reuse,
it is cleaner to integrate as part of SoC files itself. The defaults
are configured for clocking the timers from system clock(HFOSC0).

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20230531213215.602395-4-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-j721s2-mcu-wakeup: Add sa3_secproxy and mcu_sec_proxy

Security Management Subsystem(SMS) has it's own unique secure
proxy as part of Security Accelerator (SA3) module. This is use

arm64: dts: ti: k3-j721s2-mcu-wakeup: Add sa3_secproxy and mcu_sec_proxy

Security Management Subsystem(SMS) has it's own unique secure
proxy as part of Security Accelerator (SA3) module. This is used
for communicating with ROM and for special usecases such as HSM
operations. In addition MCU island has it's own secure proxy for
usecases involving the MCU micro controllers. These are in addition
to the one in the main domain DMSS subsystem that is used for general
purpose communication.

Describe the nodes for use with bootloaders and firmware that require
these communication paths which uses interrupts to corresponding micro
controller interrupt controller. Mark the node as disabled since these
instances do not have interrupts routed to the main processor by
default for a complete description of the node.

Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230530165900.47502-7-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: j721s2: Add VTM node

VTM stands for Voltage Thermal Management. Add the thermal zones.
Six sensors mapping to six thermal zones. Main0, Main1, Main2, Main3,
WKUP1 & WKUP2 domains res

arm64: dts: ti: j721s2: Add VTM node

VTM stands for Voltage Thermal Management. Add the thermal zones.
Six sensors mapping to six thermal zones. Main0, Main1, Main2, Main3,
WKUP1 & WKUP2 domains respectively.

Signed-off-by: Keerthy <j-keerthy@ti.com>
[bb@ti.com: rebased on v6.3-rc1]
Signed-off-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20230405215328.3755561-8-bb@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI

Add support for two instance of OSPI in J721S2 SoC.

Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Aswath Govindraju <a-go

arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI

Add support for two instance of OSPI in J721S2 SoC.

Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230331090028.8373-4-r-gunasekaran@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-j721s2: Add MCSPI nodes

J721S2 has 8 MCSPI instances in the main domain and 3 instances
in the MCU domain. Add the DT nodes for all the 11 instances and
keep them disabled. MAIN_M

arm64: dts: ti: k3-j721s2: Add MCSPI nodes

J721S2 has 8 MCSPI instances in the main domain and 3 instances
in the MCU domain. Add the DT nodes for all the 11 instances and
keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2
by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out
externally.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Keerthy <j-keerthy@ti.com>
Link: https://lore.kernel.org/r/20230321082827.14274-4-vaishnav.a@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support for ADC nodes

J721s2 has two instances of 8 channel ADCs in MCU domain. Add support
for both ADC nodes.

Signed-off-by: Bhavya Kapoor <b-kapoor@ti.c

arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support for ADC nodes

J721s2 has two instances of 8 channel ADCs in MCU domain. Add support
for both ADC nodes.

Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20230316095146.498999-2-b-kapoor@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-j721s2: Fix the interrupt ranges property for main & wkup gpio intr

The parent's input irq number is wrongly subtracted with 32 instead of
using the exact numbers in:

https://sof

arm64: dts: ti: k3-j721s2: Fix the interrupt ranges property for main & wkup gpio intr

The parent's input irq number is wrongly subtracted with 32 instead of
using the exact numbers in:

https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j721s2/interrupt_cfg.html

The GPIO interrupts are not working because of that. The toggling works
fine but interrupts are not firing. Fix the parent's input irq that
specifies the base for parent irq.

Tested for MAIN_GPIO0_6 interrupt on the j721s2 EVM.

Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC")
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20220922072950.9157-1-j-keerthy@ti.com

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arm64: dts: ti: k3-j721s2: Enable I2C nodes at the board level

I2C nodes defined in the top-level J721s2 SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux

arm64: dts: ti: k3-j721s2: Enable I2C nodes at the board level

I2C nodes defined in the top-level J721s2 SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
information.

As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.

Disable the I2C nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.

Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20221020160305.18711-13-afd@ti.com

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arm64: dts: ti: k3-j721s2: Enable MCAN nodes at the board level

MCAN nodes defined in the top-level J721s2 SoC dtsi files are incomplete
and may not be functional unless they are extended with pinmu

arm64: dts: ti: k3-j721s2: Enable MCAN nodes at the board level

MCAN nodes defined in the top-level J721s2 SoC dtsi files are incomplete
and may not be functional unless they are extended with pinmux
information.

As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.

Disable the MCAN nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.

Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20221020160305.18711-12-afd@ti.com

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arm64: dts: ti: k3-j721s2: Enable UART nodes at the board level

UART nodes defined in the top-level J721s2 SoC dtsi files are incomplete
and may not be functional unless they are extended with pinmu

arm64: dts: ti: k3-j721s2: Enable UART nodes at the board level

UART nodes defined in the top-level J721s2 SoC dtsi files are incomplete
and may not be functional unless they are extended with pinmux
information.

As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.

Disable the UART nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.

Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20221020160305.18711-8-afd@ti.com

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arm64: dts: ti: Adjust whitespace around '='

Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment. No functional
changes (same DTB

arm64: dts: ti: Adjust whitespace around '='

Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment. No functional
changes (same DTB).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20220526204139.831895-1-krzysztof.kozlowski@linaro.org

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arm64: dts: ti: k3-j721s2-mcu-wakeup: Fix the interrupt-parent for wkup_gpioX instances

The interrupt-parent for wkup_gpioX instances are wrongly assigned as
main_gpio_intr instead of wkup_gpio_intr

arm64: dts: ti: k3-j721s2-mcu-wakeup: Fix the interrupt-parent for wkup_gpioX instances

The interrupt-parent for wkup_gpioX instances are wrongly assigned as
main_gpio_intr instead of wkup_gpio_intr. Fix it.

Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC")
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20220203132647.11314-1-a-govindraju@ti.com

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arm64: dts: ti: Add initial support for J721S2 SoC

The J721S2 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration in automotive ADAS applications and
ind

arm64: dts: ti: Add initial support for J721S2 SoC

The J721S2 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration in automotive ADAS applications and
industrial applications requiring AI at the network edge. This SoC extends
the Jacinto 7 family of SoCs with focus on lowering system costs and power
while providing interfaces, memory architecture and compute performance for
single and multi-sensor applications.

Some highlights of this SoC are:

* Dual Cortex-A72s in a single cluster, three clusters of lockstep capable
dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x
floating point Vector DSP.
* 3D GPU: Automotive grade IMG BXS-4-64
* Vision Processing Accelerator (VPAC) with image signal processor and
Depth and Motion Processing Accelerator (DMPAC)
* Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface.
* Two Ethernet ports with RGMII support.
* Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems,
* Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller,
QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL
management.
* Chips and Media Wave521CL H.264/H.265 encode/decode engine

See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021)
for further details: http://www.ti.com/lit/pdf/spruj28

Introduce basic support for the J721S2 SoC.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20211207080904.14324-4-a-govindraju@ti.com

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