Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45 |
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#
1228242d |
| 09-Aug-2023 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable TSCADC nodes at the board level
TSCADC nodes defined in the top-level AM65 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmu
arm64: dts: ti: k3-am65: Enable TSCADC nodes at the board level
TSCADC nodes defined in the top-level AM65 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and/or device information.
Disable the TSCADC nodes in the top-level dtsi files and only enable the ones that are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230810003814.85450-13-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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#
46d0c519 |
| 09-Aug-2023 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable OSPI nodes at the board level
OSPI nodes defined in the top-level AM65x SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux a
arm64: dts: ti: k3-am65: Enable OSPI nodes at the board level
OSPI nodes defined in the top-level AM65x SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information.
As the attached OSPI device is only known about at the board integration level, these nodes should only be enabled when provided with this information.
Disable the OSPI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230810003814.85450-5-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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Revision tags: v6.1.44, v6.1.43 |
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#
7a649518 |
| 01-Aug-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3: Fixup remaining pin group node names for make dtbs checks
Fix up outstanding pingroup node names to be compliant with the upcoming pinctrl-single schema.
Reviewed-by: Tony Lindg
arm64: dts: ti: k3: Fixup remaining pin group node names for make dtbs checks
Fix up outstanding pingroup node names to be compliant with the upcoming pinctrl-single schema.
Reviewed-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20230802040347.2264339-1-nm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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Revision tags: v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35 |
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#
a4956811 |
| 15-Jun-2023 |
Tony Lindgren <tony@atomide.com> |
arm64: dts: ti: Unify pin group node names for make dtbs checks
Prepare for pinctrl-single yaml binding and unify pin group node names.
Let's standardize on pin group node naming ending in -pins. A
arm64: dts: ti: Unify pin group node names for make dtbs checks
Prepare for pinctrl-single yaml binding and unify pin group node names.
Let's standardize on pin group node naming ending in -pins. As we don't necessarily have a SoC specific compatible property for pinctrl-single. I'd rather not add a pattern match for pins somewhere in the name for all the users.
Trying to add matches for pins-default will be futile as on the earlier SoCs we've already seen names like pins-sleep, pins-idle, pins-off and so on that would need to be matched.
And as the node is a pin group, let's prefer to use naming -pins rather than -pin as more pins may need to be added to the pin group later on.
Signed-off-by: Tony Lindgren <tony@atomide.com> [vigneshr@ti.com: Rebase onto latest ti/next and extend to new nodes] Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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Revision tags: v6.1.34, v6.1.33 |
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#
9da060be |
| 06-Jun-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am654-base-board: Fixup reference to phandles array
When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors wit
arm64: dts: ti: k3-am654-base-board: Fixup reference to phandles array
When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage.
Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230606182220.3661956-14-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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Revision tags: v6.1.32, v6.1.31, v6.1.30, v6.1.29 |
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#
c08cb9ce |
| 13-May-2023 |
Vaishnav Achath <vaishnav.a@ti.com> |
arm64: dts: ti: k3-am654-baseboard: Describe OSPI flash partition info
Describe OSPI flash partition information through device tree, this helps to remove passing partition information through the m
arm64: dts: ti: k3-am654-baseboard: Describe OSPI flash partition info
Describe OSPI flash partition information through device tree, this helps to remove passing partition information through the mtdparts commandline parameter which requires maintaining the partition information in a string format. AM654 baseboard has a MT35XU512ABA 64 MiB OSPI flash with sector size of 128 KiB thus the size of the smallest partition is chosen as 128 KiB, the partition names and offsets are chosen according to the corresponding name and offsets in bootloader.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Link: https://lore.kernel.org/r/20230513141712.27346-5-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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Revision tags: v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25 |
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#
692e8888 |
| 19-Apr-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am654-base-board: Add aliases
Introduce aliases compatible with the base definition, but focussed on the interfaces that have been exposed on the platform.
Signed-off-by: Nishant
arm64: dts: ti: k3-am654-base-board: Add aliases
Introduce aliases compatible with the base definition, but focussed on the interfaces that have been exposed on the platform.
Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20230419225913.663448-7-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
895e2f4f |
| 19-Apr-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am654-base-board: Add board detect eeprom
Enable AT24CM01 on the base board using the corresponding compatible.
Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kamlesh Gur
arm64: dts: ti: k3-am654-base-board: Add board detect eeprom
Enable AT24CM01 on the base board using the corresponding compatible.
Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20230419225913.663448-6-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
282621ed |
| 19-Apr-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am654-base-board: Add missing PMIC
Add the missing vdd_mpu PMIC.
Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.ker
arm64: dts: ti: k3-am654-base-board: Add missing PMIC
Add the missing vdd_mpu PMIC.
Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20230419225913.663448-5-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
5292f504 |
| 19-Apr-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am654-base-board: Add VTT GPIO regulator for DDR
Hold the DDR vtt regulator active for functionality.
Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kamlesh Gurudasani <k
arm64: dts: ti: k3-am654-base-board: Add VTT GPIO regulator for DDR
Hold the DDR vtt regulator active for functionality.
Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20230419225913.663448-4-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
ec1b5482 |
| 19-Apr-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am654-base-board: Rename regulator node name
Rename the regulator node names to the standard regulator-0.. numbers.
Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kamlesh
arm64: dts: ti: k3-am654-base-board: Rename regulator node name
Rename the regulator node names to the standard regulator-0.. numbers.
Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20230419225913.663448-3-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
3ae28642 |
| 19-Apr-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am654-base-board: Add missing pinmux wkup_uart, mcu_uart and mcu_i2c
Many of the definitions depend on pinmux done by the bootloader. Be explicit about the pinmux for functionalit
arm64: dts: ti: k3-am654-base-board: Add missing pinmux wkup_uart, mcu_uart and mcu_i2c
Many of the definitions depend on pinmux done by the bootloader. Be explicit about the pinmux for functionality and completeness.
Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20230419225913.663448-2-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
da4159a7 |
| 19-Apr-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am65*: Drop bootargs
Drop bootargs from the dts. earlycon is a debug property that should be enabled only when debug is desired and not as default - see referenced link on discuss
arm64: dts: ti: k3-am65*: Drop bootargs
Drop bootargs from the dts. earlycon is a debug property that should be enabled only when debug is desired and not as default - see referenced link on discussion on this topic.
Cc: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/ Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/20230419141222.383567-3-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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Revision tags: v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6 |
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#
fdb02688 |
| 28-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable McASP nodes at the board level
McASP nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmu
arm64: dts: ti: k3-am65: Enable McASP nodes at the board level
McASP nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information.
As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information.
Disable the McASP nodes in the dtsi files and only enable the ones that are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221028142417.10642-12-afd@ti.com
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3f9089ea |
| 28-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable Mailbox nodes at the board level
Mailbox nodes defined in the top-level AM65x SoC dtsi files are incomplete and may not be functional unless they are extended with a
arm64: dts: ti: k3-am65: Enable Mailbox nodes at the board level
Mailbox nodes defined in the top-level AM65x SoC dtsi files are incomplete and may not be functional unless they are extended with a chosen interrupt and connection to a remote processor.
As the remote processors depend on memory nodes which are only known at the board integration level, these nodes should only be enabled when provided with the above information.
Disable the Mailbox nodes in the dtsi files and only enable the ones that are actually used on a given board.
Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221028142417.10642-11-afd@ti.com
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7ff8432c |
| 28-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable PCIe nodes at the board level
PCIe nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with a SerDe
arm64: dts: ti: k3-am65: Enable PCIe nodes at the board level
PCIe nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with a SerDes PHY. And usually only one of the two modes can be used at a time as they share a SerDes link.
As the PHY and mode is only known at the board integration level, these nodes should only be enabled when provided with this information.
Disable the PCIe nodes in the dtsi files and only enable the ones that are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221028142417.10642-10-afd@ti.com
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b08bf4a5 |
| 28-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable MCAN nodes at the board level
MCAN nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux
arm64: dts: ti: k3-am65: Enable MCAN nodes at the board level
MCAN nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information.
As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information.
Disable the MCAN nodes in the dtsi files and only enable the ones that are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221028142417.10642-9-afd@ti.com
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c75c5c0b |
| 28-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable MDIO nodes at the board level
MDIO nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with a pinmu
arm64: dts: ti: k3-am65: Enable MDIO nodes at the board level
MDIO nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with a pinmux.
As the attached PHY is only known about at the board integration level, these nodes should only be enabled when provided with this information.
Disable the MDIO nodes in the dtsi files and only enable the ones that are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221028142417.10642-8-afd@ti.com
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0edd6d7e |
| 28-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: MDIO pinmux should belong to the MDIO node
Although usually integrated as a child of an Ethernet controller, MDIO IP has an independent pinout. This pinout should be control
arm64: dts: ti: k3-am65: MDIO pinmux should belong to the MDIO node
Although usually integrated as a child of an Ethernet controller, MDIO IP has an independent pinout. This pinout should be controlled by the MDIO node (so if it was to be disabled for instance, the pinmux state would reflect that).
Move the MDIO pins pinmux to the MIDO nodes.
Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221028142417.10642-7-afd@ti.com
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c1d1189e |
| 28-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable ECAP nodes at the board level
ECAP nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux
arm64: dts: ti: k3-am65: Enable ECAP nodes at the board level
ECAP nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. (These and the EPWM nodes could be used to trigger internal actions but they are not used like that currently)
As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information.
Disable the ECAP nodes in the dtsi files and only enable the ones that are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221028142417.10642-6-afd@ti.com
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#
1c49cbb1 |
| 28-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable SPI nodes at the board level
SPI nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux in
arm64: dts: ti: k3-am65: Enable SPI nodes at the board level
SPI nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information.
As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information.
Disable the SPI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221028142417.10642-4-afd@ti.com
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c0a5ba87 |
| 28-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable I2C nodes at the board level
I2C nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux in
arm64: dts: ti: k3-am65: Enable I2C nodes at the board level
I2C nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information.
As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information.
Disable the I2C nodes in the dtsi files and only enable the ones that are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221028142417.10642-3-afd@ti.com
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#
65e8781a |
| 28-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable UART nodes at the board level
UART nodes defined in the top-level AM65x SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux i
arm64: dts: ti: k3-am65: Enable UART nodes at the board level
UART nodes defined in the top-level AM65x SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux information.
As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information.
Disable the UART nodes in the dtsi files and only enable the ones that are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221028142417.10642-2-afd@ti.com
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Revision tags: v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48 |
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#
85423386 |
| 15-Jun-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: ti: Align gpio-key node names with dtschema
The node names should be generic and DT schema expects certain pattern (e.g. with key/button/switch).
Signed-off-by: Krzysztof Kozlowski <krz
arm64: dts: ti: Align gpio-key node names with dtschema
The node names should be generic and DT schema expects certain pattern (e.g. with key/button/switch).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20220616005333.18491-29-krzysztof.kozlowski@linaro.org
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Revision tags: v5.15.47, v5.15.46, v5.15.45, v5.15.44 |
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5888f1ed |
| 26-May-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: ti: Adjust whitespace around '='
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB
arm64: dts: ti: Adjust whitespace around '='
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20220526204139.831895-1-krzysztof.kozlowski@linaro.org
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