arm64: dts: rockchip: add efuse for RK3368 SoCs

This adds the definition for eFuse that is found on RK3368 SoCs with the
corresponding data cells.

Signed-off-by: Romain Perier <romain.perier@collab

arm64: dts: rockchip: add efuse for RK3368 SoCs

This adds the definition for eFuse that is found on RK3368 SoCs with the
corresponding data cells.

Signed-off-by: Romain Perier <romain.perier@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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arm64: dts: rockchip: fix typo in iommu nodes

The latest dtc warns about an extraneous cell in the interrupt
property of two of the iommu device nodes:

Warning (interrupts_property): interrupts siz

arm64: dts: rockchip: fix typo in iommu nodes

The latest dtc warns about an extraneous cell in the interrupt
property of two of the iommu device nodes:

Warning (interrupts_property): interrupts size is (16), expected multiple of 12 in /iommu@ff373f00
Warning (interrupts_property): interrupts size is (16), expected multiple of 12 in /iommu@ff900800

This removes the typo.

Fixes: cede4c79de28 ("arm64: dts: rockchip: add rk3368 iommu nodes")
Fixes: 49c82f2b7c5d ("arm64: dts: rockchip: add rk3328 iommu nodes")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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Revert "arm64: dts: rockchip: Add basic cpu frequencies for RK3368"

This reverts commit 6f2dea1f5fdb73eb2e050d9ebe990121d557e519.

Without accurate cpu regulators being set for boards this will wrea

Revert "arm64: dts: rockchip: Add basic cpu frequencies for RK3368"

This reverts commit 6f2dea1f5fdb73eb2e050d9ebe990121d557e519.

Without accurate cpu regulators being set for boards this will wreak havoc
when cpufreq-dt begins to set new frequencies without adjusting the core
frequency.

Additionally the rk3368 has an unsolved issue in that it has two separate
cpu clusters with separate clock lines but only one cpu supply regulator
for both clusters, which causes even more problems.

While it seems that originally only one cluster was supposed to be active
at a time (big or little), talking with real users of the hardware
revealed that having all 8 cores accessible at 1.2GHz max is way more
liked than having 4 cores at 1.5GHz max. Such an approach needs changes
to cpufreq and/or opp though to control the two separate clock lines when
setting both clusters to the same frequencies.

In any case, having the OPPs in the dts at this point in time is
undesireable, so remove them again for now.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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arm64: dts: rockchip: add rk3368 iommu nodes

Add IEP/ISP/VOP/HEVC/VPU iommu nodes

Signed-off-by: Simon Xue <xxm@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

arm64: dts: rockchip: Add basic cpu frequencies for RK3368

This adds and enable the operating points that have been tested and are
currently supported by the SoC. This also adds clocks for ARMCLKL a

arm64: dts: rockchip: Add basic cpu frequencies for RK3368

This adds and enable the operating points that have been tested and are
currently supported by the SoC. This also adds clocks for ARMCLKL and
ARMCLKB.

Signed-off-by: Romain Perier <romain.perier@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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arm64: dts: rockchip: add rk3368 spdif node

This patch add the spdif dt node for rk3368 soc.

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

arm64: dts: rockchip: add rk3368 dw-mmc resets

dw-mmc got its reset-properties specified, so add the softresets
for it on the rk3368.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Sh

arm64: dts: rockchip: add rk3368 dw-mmc resets

dw-mmc got its reset-properties specified, so add the softresets
for it on the rk3368.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>

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arm64: dts: rockchip: disable mailbox of RK3368 SoCs per default

Default to disable mailbox in rk3368 core dts file.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Heiko Stuebner

arm64: dts: rockchip: disable mailbox of RK3368 SoCs per default

Default to disable mailbox in rk3368 core dts file.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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arm64: dts: rockchip: add i2s nodes support for RK3368 SoCs

I2S of RK3368 SoCs keep same as RK3066 SoCs found on Rockchip,
add nodes to support them.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.co

arm64: dts: rockchip: add i2s nodes support for RK3368 SoCs

I2S of RK3368 SoCs keep same as RK3066 SoCs found on Rockchip,
add nodes to support them.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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arm64: dts: rockchip: add dmac nodes for rk3368 SoCs

Add dmac bus and dmac peri dts nodes for peripherals,
such as I2S, SPI, UART and so on.

Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

arm64: dts: rockchip: add dmac nodes for rk3368 SoCs

Add dmac bus and dmac peri dts nodes for peripherals,
such as I2S, SPI, UART and so on.

Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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arm64: dts: rockchip: remove wrongly added idle states on rk3368

As reported by Lorenzo, the residency/latency values defined in the
idle-state for rk3368 "make no sense". When introducing them I
si

arm64: dts: rockchip: remove wrongly added idle states on rk3368

As reported by Lorenzo, the residency/latency values defined in the
idle-state for rk3368 "make no sense". When introducing them I
simply took the idle-state node from the vendor kernel in error
as I didn't look up if these values were sane in the first place.

Talking to people and determining why they were used in this way
showed that it was meant to make sure the cpu_suspend callback
got initialized which at the 3.10 time was somehow required even
for wfi-based idle handling.

Of course the generic arch_cpu_idle() now does wfi-based idle-handling
already and the rk3368 does not implement any other idle states than
the default WFI, so these wrong idle-states should go away.

Reported-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

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usb: dwc2: Deprecate g-use-dma binding

This is not needed as the gadget now fully supports DMA and it can
autodetect it. This was initially added because gadget DMA mode was only
partially implement

usb: dwc2: Deprecate g-use-dma binding

This is not needed as the gadget now fully supports DMA and it can
autodetect it. This was initially added because gadget DMA mode was only
partially implemented so could not be automatically enabled.

Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>

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arm64: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max"

In drivers/mmc/core/host.c, there is "max-freqeuncy" property.
It should be same behavior, So Use the "max-frequency"

arm64: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max"

In drivers/mmc/core/host.c, there is "max-freqeuncy" property.
It should be same behavior, So Use the "max-frequency" instead of
"clock-freq-min-max".

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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arm64: dts: rockchip: fix i2c resource error of rk3368

According to the TRM and downstream code from rockchip, the register
address of i2c1 on rk3368 is 0xff660000 and i2c2 is 0xff140000.

This patc

arm64: dts: rockchip: fix i2c resource error of rk3368

According to the TRM and downstream code from rockchip, the register
address of i2c1 on rk3368 is 0xff660000 and i2c2 is 0xff140000.

This patch fix the i2c1 & i2c2 register address definition error, also
fix the clk and pinctrl reference error.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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arm64: dts: rockchip: add reset saradc node for rk3368 SoCs

SARADC controller needs to be reset before programming it, otherwise
it will not function properly.

Signed-off-by: Caesar Wang <wxt@rock-

arm64: dts: rockchip: add reset saradc node for rk3368 SoCs

SARADC controller needs to be reset before programming it, otherwise
it will not function properly.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>

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arm64: dts: rockchip: add syscon-reboot-mode DT node

Add syscon-reboot-mode driver DT node for rk3368 platform

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Tested-by: Caesar Wang <caesar.upstr

arm64: dts: rockchip: add syscon-reboot-mode DT node

Add syscon-reboot-mode driver DT node for rk3368 platform

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Tested-by: Caesar Wang <caesar.upstream@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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arm64: dts: rockchip: fixes the gic400 2nd region size for rk3368

The 2nd additional region is the GIC virtual cpu interface register
base and size.

As the gic400 of rk3368 says, the cpu interface

arm64: dts: rockchip: fixes the gic400 2nd region size for rk3368

The 2nd additional region is the GIC virtual cpu interface register
base and size.

As the gic400 of rk3368 says, the cpu interface register map as below

:

-0x0000 GICC_CTRL
.
.
.
-0x00fc GICC_IIDR
-0x1000 GICC_IDR

Obviously, the region size should be greater than 0x1000.
So we should make sure to include the GICC_IDR since the kernel will access
it in some cases.

Fixes: b790c2cab5ca ("arm64: dts: add Rockchip rk3368 core dtsi and board dts for the r88 board")
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Cc: stable@vger.kernel.org

[added Fixes and stable-cc]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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arm64: dts: rockchip: add rk3368 io-domain core nodes

Add the core io-domain nodes to grf and pmugrf which individual
boards than just have to enable and add the necessary supplies to.

Signed-off-b

arm64: dts: rockchip: add rk3368 io-domain core nodes

Add the core io-domain nodes to grf and pmugrf which individual
boards than just have to enable and add the necessary supplies to.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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arm64: dts: rockchip: make rk3368 grf syscons simple-mfds

The general register files do contain a lot of separate functions and
while some really are only registers with a lot of different 1-bit
set

arm64: dts: rockchip: make rk3368 grf syscons simple-mfds

The general register files do contain a lot of separate functions and
while some really are only registers with a lot of different 1-bit
settings, there are also a lot of them containing some bigger function
blocks. To be able to define these as sub-devices, make them simple-mfds.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: David Wu <david.wu@rock-chips.com>

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arm64: dts: rockchip: move the rk3368 thermal data into rk3368.dtsi

In order to be standard to manage for rockchip SoCs, move the thermal
data into rk3368 dtsi, we needn't to add a new file for the

arm64: dts: rockchip: move the rk3368 thermal data into rk3368.dtsi

In order to be standard to manage for rockchip SoCs, move the thermal
data into rk3368 dtsi, we needn't to add a new file for thermal.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: Eduardo Valentin <edubezval@gmail.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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arm64: dts: rockchip: Add rk3368 mailbox device nodes

This adds mailbox device nodes in dts.

Mailbox is used by the Rockchip CPU cores to communicate
requests to MCU processor.

Signed-off-by: Caes

arm64: dts: rockchip: Add rk3368 mailbox device nodes

This adds mailbox device nodes in dts.

Mailbox is used by the Rockchip CPU cores to communicate
requests to MCU processor.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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arm64: dts: rockchip: fix the incorrect otp-out pin on rk3368

This patch fixes the incorrect Over-temperature protection pin.
since the rk3368 io list said the otp pin is gpio0a3.

Anyway, that shou

arm64: dts: rockchip: fix the incorrect otp-out pin on rk3368

This patch fixes the incorrect Over-temperature protection pin.
since the rk3368 io list said the otp pin is gpio0a3.

Anyway, that should be fixed in here.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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arm64: dts: rockchip: add rk3368 tuning clk for emmc and sdmmc

Add tuning clk for emmc and sdmmc, otherwise I get
the following failure while enabling mmc-hs200-1_8v.

dwmmc_rockchip ff0f0000.dwmmc:

arm64: dts: rockchip: add rk3368 tuning clk for emmc and sdmmc

Add tuning clk for emmc and sdmmc, otherwise I get
the following failure while enabling mmc-hs200-1_8v.

dwmmc_rockchip ff0f0000.dwmmc: Tuning clock (sample_clk) not defined.
mmc0: tuning execution failed
mmc0: error -5 whilst initialising MMC card

With it
dwmmc_rockchip ff0f0000.dwmmc: Successfully tuned phase to 170
mmc0: new HS200 MMC card at address 0001
mmcblk0: mmc0:0001 M8G1GC 7.28 GiB

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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arm64: dts: rockchip: Add the broadcast-timer for RK3368 SoC

There is a need of a broadcast timer in this case to ensure proper
wakeup when the cpus are in sleep mode and a timer expires.

Signed-of

arm64: dts: rockchip: Add the broadcast-timer for RK3368 SoC

There is a need of a broadcast timer in this case to ensure proper
wakeup when the cpus are in sleep mode and a timer expires.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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arm64: dts: rockchip: Fix typo in rk3368 sdmmc card detect pin name

The card detect pin is currently called sdmcc-cd.
This patch fixes the typo and renames the pin to sdmmc-cd.

Signed-off-by: Matth

arm64: dts: rockchip: Fix typo in rk3368 sdmmc card detect pin name

The card detect pin is currently called sdmcc-cd.
This patch fixes the typo and renames the pin to sdmmc-cd.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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