1/* 2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include <dt-bindings/clock/rk3368-cru.h> 44#include <dt-bindings/gpio/gpio.h> 45#include <dt-bindings/interrupt-controller/irq.h> 46#include <dt-bindings/interrupt-controller/arm-gic.h> 47#include <dt-bindings/pinctrl/rockchip.h> 48#include <dt-bindings/thermal/thermal.h> 49 50/ { 51 compatible = "rockchip,rk3368"; 52 interrupt-parent = <&gic>; 53 #address-cells = <2>; 54 #size-cells = <2>; 55 56 aliases { 57 ethernet0 = &gmac; 58 i2c0 = &i2c0; 59 i2c1 = &i2c1; 60 i2c2 = &i2c2; 61 i2c3 = &i2c3; 62 i2c4 = &i2c4; 63 i2c5 = &i2c5; 64 serial0 = &uart0; 65 serial1 = &uart1; 66 serial2 = &uart2; 67 serial3 = &uart3; 68 serial4 = &uart4; 69 spi0 = &spi0; 70 spi1 = &spi1; 71 spi2 = &spi2; 72 }; 73 74 cpus { 75 #address-cells = <0x2>; 76 #size-cells = <0x0>; 77 78 cpu-map { 79 cluster0 { 80 core0 { 81 cpu = <&cpu_b0>; 82 }; 83 core1 { 84 cpu = <&cpu_b1>; 85 }; 86 core2 { 87 cpu = <&cpu_b2>; 88 }; 89 core3 { 90 cpu = <&cpu_b3>; 91 }; 92 }; 93 94 cluster1 { 95 core0 { 96 cpu = <&cpu_l0>; 97 }; 98 core1 { 99 cpu = <&cpu_l1>; 100 }; 101 core2 { 102 cpu = <&cpu_l2>; 103 }; 104 core3 { 105 cpu = <&cpu_l3>; 106 }; 107 }; 108 }; 109 110 idle-states { 111 entry-method = "psci"; 112 113 cpu_sleep: cpu-sleep-0 { 114 compatible = "arm,idle-state"; 115 arm,psci-suspend-param = <0x1010000>; 116 entry-latency-us = <0x3fffffff>; 117 exit-latency-us = <0x40000000>; 118 min-residency-us = <0xffffffff>; 119 }; 120 }; 121 122 cpu_l0: cpu@0 { 123 device_type = "cpu"; 124 compatible = "arm,cortex-a53", "arm,armv8"; 125 reg = <0x0 0x0>; 126 cpu-idle-states = <&cpu_sleep>; 127 enable-method = "psci"; 128 129 #cooling-cells = <2>; /* min followed by max */ 130 }; 131 132 cpu_l1: cpu@1 { 133 device_type = "cpu"; 134 compatible = "arm,cortex-a53", "arm,armv8"; 135 reg = <0x0 0x1>; 136 cpu-idle-states = <&cpu_sleep>; 137 enable-method = "psci"; 138 }; 139 140 cpu_l2: cpu@2 { 141 device_type = "cpu"; 142 compatible = "arm,cortex-a53", "arm,armv8"; 143 reg = <0x0 0x2>; 144 cpu-idle-states = <&cpu_sleep>; 145 enable-method = "psci"; 146 }; 147 148 cpu_l3: cpu@3 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a53", "arm,armv8"; 151 reg = <0x0 0x3>; 152 cpu-idle-states = <&cpu_sleep>; 153 enable-method = "psci"; 154 }; 155 156 cpu_b0: cpu@100 { 157 device_type = "cpu"; 158 compatible = "arm,cortex-a53", "arm,armv8"; 159 reg = <0x0 0x100>; 160 cpu-idle-states = <&cpu_sleep>; 161 enable-method = "psci"; 162 163 #cooling-cells = <2>; /* min followed by max */ 164 }; 165 166 cpu_b1: cpu@101 { 167 device_type = "cpu"; 168 compatible = "arm,cortex-a53", "arm,armv8"; 169 reg = <0x0 0x101>; 170 cpu-idle-states = <&cpu_sleep>; 171 enable-method = "psci"; 172 }; 173 174 cpu_b2: cpu@102 { 175 device_type = "cpu"; 176 compatible = "arm,cortex-a53", "arm,armv8"; 177 reg = <0x0 0x102>; 178 cpu-idle-states = <&cpu_sleep>; 179 enable-method = "psci"; 180 }; 181 182 cpu_b3: cpu@103 { 183 device_type = "cpu"; 184 compatible = "arm,cortex-a53", "arm,armv8"; 185 reg = <0x0 0x103>; 186 cpu-idle-states = <&cpu_sleep>; 187 enable-method = "psci"; 188 }; 189 }; 190 191 arm-pmu { 192 compatible = "arm,armv8-pmuv3"; 193 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 201 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, 202 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>, 203 <&cpu_b2>, <&cpu_b3>; 204 }; 205 206 psci { 207 compatible = "arm,psci-0.2"; 208 method = "smc"; 209 }; 210 211 timer { 212 compatible = "arm,armv8-timer"; 213 interrupts = <GIC_PPI 13 214 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 215 <GIC_PPI 14 216 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 217 <GIC_PPI 11 218 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 219 <GIC_PPI 10 220 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 221 }; 222 223 xin24m: oscillator { 224 compatible = "fixed-clock"; 225 clock-frequency = <24000000>; 226 clock-output-names = "xin24m"; 227 #clock-cells = <0>; 228 }; 229 230 sdmmc: dwmmc@ff0c0000 { 231 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 232 reg = <0x0 0xff0c0000 0x0 0x4000>; 233 clock-freq-min-max = <400000 150000000>; 234 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 235 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 236 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 237 fifo-depth = <0x100>; 238 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 239 status = "disabled"; 240 }; 241 242 sdio0: dwmmc@ff0d0000 { 243 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 244 reg = <0x0 0xff0d0000 0x0 0x4000>; 245 clock-freq-min-max = <400000 150000000>; 246 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 247 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 248 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 249 fifo-depth = <0x100>; 250 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 251 status = "disabled"; 252 }; 253 254 emmc: dwmmc@ff0f0000 { 255 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 256 reg = <0x0 0xff0f0000 0x0 0x4000>; 257 clock-freq-min-max = <400000 150000000>; 258 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 259 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 260 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 261 fifo-depth = <0x100>; 262 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 263 status = "disabled"; 264 }; 265 266 saradc: saradc@ff100000 { 267 compatible = "rockchip,saradc"; 268 reg = <0x0 0xff100000 0x0 0x100>; 269 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 270 #io-channel-cells = <1>; 271 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 272 clock-names = "saradc", "apb_pclk"; 273 status = "disabled"; 274 }; 275 276 spi0: spi@ff110000 { 277 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 278 reg = <0x0 0xff110000 0x0 0x1000>; 279 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 280 clock-names = "spiclk", "apb_pclk"; 281 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 282 pinctrl-names = "default"; 283 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 status = "disabled"; 287 }; 288 289 spi1: spi@ff120000 { 290 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 291 reg = <0x0 0xff120000 0x0 0x1000>; 292 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 293 clock-names = "spiclk", "apb_pclk"; 294 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 status = "disabled"; 300 }; 301 302 spi2: spi@ff130000 { 303 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 304 reg = <0x0 0xff130000 0x0 0x1000>; 305 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 306 clock-names = "spiclk", "apb_pclk"; 307 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 308 pinctrl-names = "default"; 309 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 310 #address-cells = <1>; 311 #size-cells = <0>; 312 status = "disabled"; 313 }; 314 315 i2c1: i2c@ff140000 { 316 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 317 reg = <0x0 0xff140000 0x0 0x1000>; 318 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 clock-names = "i2c"; 322 clocks = <&cru PCLK_I2C1>; 323 pinctrl-names = "default"; 324 pinctrl-0 = <&i2c1_xfer>; 325 status = "disabled"; 326 }; 327 328 i2c3: i2c@ff150000 { 329 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 330 reg = <0x0 0xff150000 0x0 0x1000>; 331 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 332 #address-cells = <1>; 333 #size-cells = <0>; 334 clock-names = "i2c"; 335 clocks = <&cru PCLK_I2C3>; 336 pinctrl-names = "default"; 337 pinctrl-0 = <&i2c3_xfer>; 338 status = "disabled"; 339 }; 340 341 i2c4: i2c@ff160000 { 342 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 343 reg = <0x0 0xff160000 0x0 0x1000>; 344 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 clock-names = "i2c"; 348 clocks = <&cru PCLK_I2C4>; 349 pinctrl-names = "default"; 350 pinctrl-0 = <&i2c4_xfer>; 351 status = "disabled"; 352 }; 353 354 i2c5: i2c@ff170000 { 355 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 356 reg = <0x0 0xff170000 0x0 0x1000>; 357 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 358 #address-cells = <1>; 359 #size-cells = <0>; 360 clock-names = "i2c"; 361 clocks = <&cru PCLK_I2C5>; 362 pinctrl-names = "default"; 363 pinctrl-0 = <&i2c5_xfer>; 364 status = "disabled"; 365 }; 366 367 uart0: serial@ff180000 { 368 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 369 reg = <0x0 0xff180000 0x0 0x100>; 370 clock-frequency = <24000000>; 371 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 372 clock-names = "baudclk", "apb_pclk"; 373 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 374 reg-shift = <2>; 375 reg-io-width = <4>; 376 status = "disabled"; 377 }; 378 379 uart1: serial@ff190000 { 380 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 381 reg = <0x0 0xff190000 0x0 0x100>; 382 clock-frequency = <24000000>; 383 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 384 clock-names = "baudclk", "apb_pclk"; 385 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 386 reg-shift = <2>; 387 reg-io-width = <4>; 388 status = "disabled"; 389 }; 390 391 uart3: serial@ff1b0000 { 392 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 393 reg = <0x0 0xff1b0000 0x0 0x100>; 394 clock-frequency = <24000000>; 395 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 396 clock-names = "baudclk", "apb_pclk"; 397 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 398 reg-shift = <2>; 399 reg-io-width = <4>; 400 status = "disabled"; 401 }; 402 403 uart4: serial@ff1c0000 { 404 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 405 reg = <0x0 0xff1c0000 0x0 0x100>; 406 clock-frequency = <24000000>; 407 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 408 clock-names = "baudclk", "apb_pclk"; 409 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 410 reg-shift = <2>; 411 reg-io-width = <4>; 412 status = "disabled"; 413 }; 414 415 thermal-zones { 416 #include "rk3368-thermal.dtsi" 417 }; 418 419 tsadc: tsadc@ff280000 { 420 compatible = "rockchip,rk3368-tsadc"; 421 reg = <0x0 0xff280000 0x0 0x100>; 422 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 423 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 424 clock-names = "tsadc", "apb_pclk"; 425 resets = <&cru SRST_TSADC>; 426 reset-names = "tsadc-apb"; 427 pinctrl-names = "init", "default", "sleep"; 428 pinctrl-0 = <&otp_gpio>; 429 pinctrl-1 = <&otp_out>; 430 pinctrl-2 = <&otp_gpio>; 431 #thermal-sensor-cells = <1>; 432 rockchip,hw-tshut-temp = <95000>; 433 status = "disabled"; 434 }; 435 436 gmac: ethernet@ff290000 { 437 compatible = "rockchip,rk3368-gmac"; 438 reg = <0x0 0xff290000 0x0 0x10000>; 439 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 440 interrupt-names = "macirq"; 441 rockchip,grf = <&grf>; 442 clocks = <&cru SCLK_MAC>, 443 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 444 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 445 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 446 clock-names = "stmmaceth", 447 "mac_clk_rx", "mac_clk_tx", 448 "clk_mac_ref", "clk_mac_refout", 449 "aclk_mac", "pclk_mac"; 450 status = "disabled"; 451 }; 452 453 usb_host0_ehci: usb@ff500000 { 454 compatible = "generic-ehci"; 455 reg = <0x0 0xff500000 0x0 0x100>; 456 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 457 clocks = <&cru HCLK_HOST0>; 458 clock-names = "usbhost"; 459 status = "disabled"; 460 }; 461 462 usb_otg: usb@ff580000 { 463 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb", 464 "snps,dwc2"; 465 reg = <0x0 0xff580000 0x0 0x40000>; 466 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&cru HCLK_OTG0>; 468 clock-names = "otg"; 469 dr_mode = "otg"; 470 g-np-tx-fifo-size = <16>; 471 g-rx-fifo-size = <275>; 472 g-tx-fifo-size = <256 128 128 64 64 32>; 473 g-use-dma; 474 status = "disabled"; 475 }; 476 477 i2c0: i2c@ff650000 { 478 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 479 reg = <0x0 0xff650000 0x0 0x1000>; 480 clocks = <&cru PCLK_I2C0>; 481 clock-names = "i2c"; 482 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 483 pinctrl-names = "default"; 484 pinctrl-0 = <&i2c0_xfer>; 485 #address-cells = <1>; 486 #size-cells = <0>; 487 status = "disabled"; 488 }; 489 490 i2c2: i2c@ff660000 { 491 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 492 reg = <0x0 0xff660000 0x0 0x1000>; 493 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 494 #address-cells = <1>; 495 #size-cells = <0>; 496 clock-names = "i2c"; 497 clocks = <&cru PCLK_I2C2>; 498 pinctrl-names = "default"; 499 pinctrl-0 = <&i2c2_xfer>; 500 status = "disabled"; 501 }; 502 503 pwm0: pwm@ff680000 { 504 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 505 reg = <0x0 0xff680000 0x0 0x10>; 506 #pwm-cells = <3>; 507 pinctrl-names = "default"; 508 pinctrl-0 = <&pwm0_pin>; 509 clocks = <&cru PCLK_PWM1>; 510 clock-names = "pwm"; 511 status = "disabled"; 512 }; 513 514 pwm1: pwm@ff680010 { 515 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 516 reg = <0x0 0xff680010 0x0 0x10>; 517 #pwm-cells = <3>; 518 pinctrl-names = "default"; 519 pinctrl-0 = <&pwm1_pin>; 520 clocks = <&cru PCLK_PWM1>; 521 clock-names = "pwm"; 522 status = "disabled"; 523 }; 524 525 pwm2: pwm@ff680020 { 526 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 527 reg = <0x0 0xff680020 0x0 0x10>; 528 #pwm-cells = <3>; 529 clocks = <&cru PCLK_PWM1>; 530 clock-names = "pwm"; 531 status = "disabled"; 532 }; 533 534 pwm3: pwm@ff680030 { 535 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 536 reg = <0x0 0xff680030 0x0 0x10>; 537 #pwm-cells = <3>; 538 pinctrl-names = "default"; 539 pinctrl-0 = <&pwm3_pin>; 540 clocks = <&cru PCLK_PWM1>; 541 clock-names = "pwm"; 542 status = "disabled"; 543 }; 544 545 uart2: serial@ff690000 { 546 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 547 reg = <0x0 0xff690000 0x0 0x100>; 548 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 549 clock-names = "baudclk", "apb_pclk"; 550 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 551 pinctrl-names = "default"; 552 pinctrl-0 = <&uart2_xfer>; 553 reg-shift = <2>; 554 reg-io-width = <4>; 555 status = "disabled"; 556 }; 557 558 pmugrf: syscon@ff738000 { 559 compatible = "rockchip,rk3368-pmugrf", "syscon"; 560 reg = <0x0 0xff738000 0x0 0x1000>; 561 }; 562 563 cru: clock-controller@ff760000 { 564 compatible = "rockchip,rk3368-cru"; 565 reg = <0x0 0xff760000 0x0 0x1000>; 566 rockchip,grf = <&grf>; 567 #clock-cells = <1>; 568 #reset-cells = <1>; 569 }; 570 571 grf: syscon@ff770000 { 572 compatible = "rockchip,rk3368-grf", "syscon"; 573 reg = <0x0 0xff770000 0x0 0x1000>; 574 }; 575 576 wdt: watchdog@ff800000 { 577 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt"; 578 reg = <0x0 0xff800000 0x0 0x100>; 579 clocks = <&cru PCLK_WDT>; 580 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 581 status = "disabled"; 582 }; 583 584 timer@ff810000 { 585 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; 586 reg = <0x0 0xff810000 0x0 0x20>; 587 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 588 }; 589 590 gic: interrupt-controller@ffb71000 { 591 compatible = "arm,gic-400"; 592 interrupt-controller; 593 #interrupt-cells = <3>; 594 #address-cells = <0>; 595 596 reg = <0x0 0xffb71000 0x0 0x1000>, 597 <0x0 0xffb72000 0x0 0x1000>, 598 <0x0 0xffb74000 0x0 0x2000>, 599 <0x0 0xffb76000 0x0 0x2000>; 600 interrupts = <GIC_PPI 9 601 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 602 }; 603 604 pinctrl: pinctrl { 605 compatible = "rockchip,rk3368-pinctrl"; 606 rockchip,grf = <&grf>; 607 rockchip,pmu = <&pmugrf>; 608 #address-cells = <0x2>; 609 #size-cells = <0x2>; 610 ranges; 611 612 gpio0: gpio0@ff750000 { 613 compatible = "rockchip,gpio-bank"; 614 reg = <0x0 0xff750000 0x0 0x100>; 615 clocks = <&cru PCLK_GPIO0>; 616 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>; 617 618 gpio-controller; 619 #gpio-cells = <0x2>; 620 621 interrupt-controller; 622 #interrupt-cells = <0x2>; 623 }; 624 625 gpio1: gpio1@ff780000 { 626 compatible = "rockchip,gpio-bank"; 627 reg = <0x0 0xff780000 0x0 0x100>; 628 clocks = <&cru PCLK_GPIO1>; 629 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>; 630 631 gpio-controller; 632 #gpio-cells = <0x2>; 633 634 interrupt-controller; 635 #interrupt-cells = <0x2>; 636 }; 637 638 gpio2: gpio2@ff790000 { 639 compatible = "rockchip,gpio-bank"; 640 reg = <0x0 0xff790000 0x0 0x100>; 641 clocks = <&cru PCLK_GPIO2>; 642 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>; 643 644 gpio-controller; 645 #gpio-cells = <0x2>; 646 647 interrupt-controller; 648 #interrupt-cells = <0x2>; 649 }; 650 651 gpio3: gpio3@ff7a0000 { 652 compatible = "rockchip,gpio-bank"; 653 reg = <0x0 0xff7a0000 0x0 0x100>; 654 clocks = <&cru PCLK_GPIO3>; 655 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>; 656 657 gpio-controller; 658 #gpio-cells = <0x2>; 659 660 interrupt-controller; 661 #interrupt-cells = <0x2>; 662 }; 663 664 pcfg_pull_up: pcfg-pull-up { 665 bias-pull-up; 666 }; 667 668 pcfg_pull_down: pcfg-pull-down { 669 bias-pull-down; 670 }; 671 672 pcfg_pull_none: pcfg-pull-none { 673 bias-disable; 674 }; 675 676 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 677 bias-disable; 678 drive-strength = <12>; 679 }; 680 681 emmc { 682 emmc_clk: emmc-clk { 683 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 684 }; 685 686 emmc_cmd: emmc-cmd { 687 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>; 688 }; 689 690 emmc_pwr: emmc-pwr { 691 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>; 692 }; 693 694 emmc_bus1: emmc-bus1 { 695 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>; 696 }; 697 698 emmc_bus4: emmc-bus4 { 699 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, 700 <1 19 RK_FUNC_2 &pcfg_pull_up>, 701 <1 20 RK_FUNC_2 &pcfg_pull_up>, 702 <1 21 RK_FUNC_2 &pcfg_pull_up>; 703 }; 704 705 emmc_bus8: emmc-bus8 { 706 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, 707 <1 19 RK_FUNC_2 &pcfg_pull_up>, 708 <1 20 RK_FUNC_2 &pcfg_pull_up>, 709 <1 21 RK_FUNC_2 &pcfg_pull_up>, 710 <1 22 RK_FUNC_2 &pcfg_pull_up>, 711 <1 23 RK_FUNC_2 &pcfg_pull_up>, 712 <1 24 RK_FUNC_2 &pcfg_pull_up>, 713 <1 25 RK_FUNC_2 &pcfg_pull_up>; 714 }; 715 }; 716 717 gmac { 718 rgmii_pins: rgmii-pins { 719 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>, 720 <3 24 RK_FUNC_1 &pcfg_pull_none>, 721 <3 19 RK_FUNC_1 &pcfg_pull_none>, 722 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 723 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>, 724 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>, 725 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>, 726 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>, 727 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>, 728 <3 15 RK_FUNC_1 &pcfg_pull_none>, 729 <3 16 RK_FUNC_1 &pcfg_pull_none>, 730 <3 17 RK_FUNC_1 &pcfg_pull_none>, 731 <3 18 RK_FUNC_1 &pcfg_pull_none>, 732 <3 25 RK_FUNC_1 &pcfg_pull_none>, 733 <3 20 RK_FUNC_1 &pcfg_pull_none>; 734 }; 735 736 rmii_pins: rmii-pins { 737 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>, 738 <3 24 RK_FUNC_1 &pcfg_pull_none>, 739 <3 19 RK_FUNC_1 &pcfg_pull_none>, 740 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 741 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>, 742 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>, 743 <3 15 RK_FUNC_1 &pcfg_pull_none>, 744 <3 16 RK_FUNC_1 &pcfg_pull_none>, 745 <3 20 RK_FUNC_1 &pcfg_pull_none>, 746 <3 21 RK_FUNC_1 &pcfg_pull_none>; 747 }; 748 }; 749 750 i2c0 { 751 i2c0_xfer: i2c0-xfer { 752 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, 753 <0 7 RK_FUNC_1 &pcfg_pull_none>; 754 }; 755 }; 756 757 i2c1 { 758 i2c1_xfer: i2c1-xfer { 759 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>, 760 <2 22 RK_FUNC_1 &pcfg_pull_none>; 761 }; 762 }; 763 764 i2c2 { 765 i2c2_xfer: i2c2-xfer { 766 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>, 767 <3 31 RK_FUNC_2 &pcfg_pull_none>; 768 }; 769 }; 770 771 i2c3 { 772 i2c3_xfer: i2c3-xfer { 773 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>, 774 <1 17 RK_FUNC_1 &pcfg_pull_none>; 775 }; 776 }; 777 778 i2c4 { 779 i2c4_xfer: i2c4-xfer { 780 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>, 781 <3 25 RK_FUNC_2 &pcfg_pull_none>; 782 }; 783 }; 784 785 i2c5 { 786 i2c5_xfer: i2c5-xfer { 787 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>, 788 <3 27 RK_FUNC_2 &pcfg_pull_none>; 789 }; 790 }; 791 792 pwm0 { 793 pwm0_pin: pwm0-pin { 794 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>; 795 }; 796 }; 797 798 pwm1 { 799 pwm1_pin: pwm1-pin { 800 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>; 801 }; 802 }; 803 804 pwm3 { 805 pwm3_pin: pwm3-pin { 806 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>; 807 }; 808 }; 809 810 sdio0 { 811 sdio0_bus1: sdio0-bus1 { 812 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>; 813 }; 814 815 sdio0_bus4: sdio0-bus4 { 816 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>, 817 <2 29 RK_FUNC_1 &pcfg_pull_up>, 818 <2 30 RK_FUNC_1 &pcfg_pull_up>, 819 <2 31 RK_FUNC_1 &pcfg_pull_up>; 820 }; 821 822 sdio0_cmd: sdio0-cmd { 823 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>; 824 }; 825 826 sdio0_clk: sdio0-clk { 827 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>; 828 }; 829 830 sdio0_cd: sdio0-cd { 831 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>; 832 }; 833 834 sdio0_wp: sdio0-wp { 835 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>; 836 }; 837 838 sdio0_pwr: sdio0-pwr { 839 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>; 840 }; 841 842 sdio0_bkpwr: sdio0-bkpwr { 843 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>; 844 }; 845 846 sdio0_int: sdio0-int { 847 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>; 848 }; 849 }; 850 851 sdmmc { 852 sdmmc_clk: sdmmc-clk { 853 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>; 854 }; 855 856 sdmmc_cmd: sdmmc-cmd { 857 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>; 858 }; 859 860 sdmmc_cd: sdmmc-cd { 861 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>; 862 }; 863 864 sdmmc_bus1: sdmmc-bus1 { 865 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>; 866 }; 867 868 sdmmc_bus4: sdmmc-bus4 { 869 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>, 870 <2 6 RK_FUNC_1 &pcfg_pull_up>, 871 <2 7 RK_FUNC_1 &pcfg_pull_up>, 872 <2 8 RK_FUNC_1 &pcfg_pull_up>; 873 }; 874 }; 875 876 spi0 { 877 spi0_clk: spi0-clk { 878 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>; 879 }; 880 spi0_cs0: spi0-cs0 { 881 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>; 882 }; 883 spi0_cs1: spi0-cs1 { 884 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>; 885 }; 886 spi0_tx: spi0-tx { 887 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>; 888 }; 889 spi0_rx: spi0-rx { 890 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>; 891 }; 892 }; 893 894 spi1 { 895 spi1_clk: spi1-clk { 896 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>; 897 }; 898 spi1_cs0: spi1-cs0 { 899 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>; 900 }; 901 spi1_cs1: spi1-cs1 { 902 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>; 903 }; 904 spi1_rx: spi1-rx { 905 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>; 906 }; 907 spi1_tx: spi1-tx { 908 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>; 909 }; 910 }; 911 912 spi2 { 913 spi2_clk: spi2-clk { 914 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>; 915 }; 916 spi2_cs0: spi2-cs0 { 917 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>; 918 }; 919 spi2_rx: spi2-rx { 920 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>; 921 }; 922 spi2_tx: spi2-tx { 923 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>; 924 }; 925 }; 926 927 tsadc { 928 otp_gpio: otp-gpio { 929 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>; 930 }; 931 932 otp_out: otp-out { 933 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>; 934 }; 935 }; 936 937 uart0 { 938 uart0_xfer: uart0-xfer { 939 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>, 940 <2 25 RK_FUNC_1 &pcfg_pull_none>; 941 }; 942 943 uart0_cts: uart0-cts { 944 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>; 945 }; 946 947 uart0_rts: uart0-rts { 948 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>; 949 }; 950 }; 951 952 uart1 { 953 uart1_xfer: uart1-xfer { 954 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>, 955 <0 21 RK_FUNC_3 &pcfg_pull_none>; 956 }; 957 958 uart1_cts: uart1-cts { 959 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>; 960 }; 961 962 uart1_rts: uart1-rts { 963 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>; 964 }; 965 }; 966 967 uart2 { 968 uart2_xfer: uart2-xfer { 969 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>, 970 <2 5 RK_FUNC_2 &pcfg_pull_none>; 971 }; 972 /* no rts / cts for uart2 */ 973 }; 974 975 uart3 { 976 uart3_xfer: uart3-xfer { 977 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>, 978 <3 30 RK_FUNC_3 &pcfg_pull_none>; 979 }; 980 981 uart3_cts: uart3-cts { 982 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>; 983 }; 984 985 uart3_rts: uart3-rts { 986 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>; 987 }; 988 }; 989 990 uart4 { 991 uart4_xfer: uart4-xfer { 992 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>, 993 <0 26 RK_FUNC_3 &pcfg_pull_none>; 994 }; 995 996 uart4_cts: uart4-cts { 997 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>; 998 }; 999 1000 uart4_rts: uart4-rts { 1001 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>; 1002 }; 1003 }; 1004 }; 1005}; 1006