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Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39 |
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| #
10ca61c6 |
| 06-Jul-2023 |
Biju Das <biju.das.jz@bp.renesas.com> |
arm64: dts: renesas: rzg2l-smarc: Add support for enabling MTU3
Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/{G2,V2}L SMARC
EVK.
The MTU3a PWM pins are muxed with spi1 pins and counter
arm64: dts: renesas: rzg2l-smarc: Add support for enabling MTU3
Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/{G2,V2}L SMARC
EVK.
The MTU3a PWM pins are muxed with spi1 pins and counter external input
phase clock pins are muxed with scif2 pins. Disable these IPs when
PMOD_MTU3 macro is enabled.
Apart from this, the counter Z phase clock signal is muxed with the
SDHI1 cd signal. So disable SDHI1 IP, when the counter Z phase signal
is enabled.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230706153047.368993-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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Revision tags: v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50 |
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| #
d1273f54 |
| 23-Jun-2022 |
Chris Paterson <chris.paterson2@renesas.com> |
arm64: dts: renesas: r9a07g054l2-smarc: Correct SoC name in comment
This dts is for the RZ/V2L SMARC EVK, not RZ/G2L.
Fixes: f91c4c74796a ("arm64: dts: renesas: Add initial device tree for RZ/V2L S
arm64: dts: renesas: r9a07g054l2-smarc: Correct SoC name in comment
This dts is for the RZ/V2L SMARC EVK, not RZ/G2L.
Fixes: f91c4c74796a ("arm64: dts: renesas: Add initial device tree for RZ/V2L SMARC EVK")
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Link: https://lore.kernel.org/r/20220623103024.24222-1-chris.paterson2@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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Revision tags: v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26 |
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| #
e3ab4573 |
| 27-Feb-2022 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
arm64: dts: renesas: r9a07g054l2-smarc: Drop deleting can{0,1}-stb-hog nodes
Drop deleting can{0,1}-stb-hog nodes so that CAN becomes operational on
Renesas RZ/V2L SMARC EVK.
Signed-off-by: Lad Pra
arm64: dts: renesas: r9a07g054l2-smarc: Drop deleting can{0,1}-stb-hog nodes
Drop deleting can{0,1}-stb-hog nodes so that CAN becomes operational on
Renesas RZ/V2L SMARC EVK.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220227203744.18355-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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| #
b0bb96e5 |
| 27-Feb-2022 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
arm64: dts: renesas: r9a07g054l2-smarc: Drop deleting gpio-hog pins related to SDHI
Drop deleting gpio-hog pins related to SDHI0/1 so that SDHI functionality
gets enabled on Renesas RZ/V2L SMARC EVK
arm64: dts: renesas: r9a07g054l2-smarc: Drop deleting gpio-hog pins related to SDHI
Drop deleting gpio-hog pins related to SDHI0/1 so that SDHI functionality
gets enabled on Renesas RZ/V2L SMARC EVK.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220227203744.18355-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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| #
48d8ee5b |
| 24-Feb-2022 |
Geert Uytterhoeven <geert+renesas@glider.be> |
arm64: dts: renesas: Align GPIO hog names with dtschema
Dtschema expects GPIO hogs to end with a "hog" suffix.
Also, the convention for node names is to use hyphens, not underscores.
Signed-off-by:
arm64: dts: renesas: Align GPIO hog names with dtschema
Dtschema expects GPIO hogs to end with a "hog" suffix.
Also, the convention for node names is to use hyphens, not underscores.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/baee4b9980576ffbab24122fce7147c9cbc2ea59.1645705998.git.geert+renesas@glider.be
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Revision tags: v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20 |
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| #
726fd781 |
| 03-Feb-2022 |
Biju Das <biju.das.jz@bp.renesas.com> |
arm64: dts: renesas: rzg2l-smarc: Add common dtsi file
RZ/{G2L,V2L} and G2LC SoC use the same carrier board, but the SoM is
different.
Different pin mapping is possible on SoM. For eg:- RZ/G2L SMAR
arm64: dts: renesas: rzg2l-smarc: Add common dtsi file
RZ/{G2L,V2L} and G2LC SoC use the same carrier board, but the SoM is
different.
Different pin mapping is possible on SoM. For eg:- RZ/G2L SMARC EVK
uses SCIF2, whereas RZ/G2LC uses SCIF1 for the serial interface available
on PMOD1.
This patch adds support for handling the pin mapping differences by moving
definitions common to RZ/G2L and RZ/G2LC to a common dtsi file.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220203170636.7747-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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Revision tags: v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15 |
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| #
f91c4c74 |
| 10-Jan-2022 |
Biju Das <biju.das.jz@bp.renesas.com> |
arm64: dts: renesas: Add initial device tree for RZ/V2L SMARC EVK
Add basic support for the RZ/V2L SMARC EVK (based on R9A07G054L2):
- memory
- External input clock
- CPG
- Pin controller
- SCIF
- G
arm64: dts: renesas: Add initial device tree for RZ/V2L SMARC EVK
Add basic support for the RZ/V2L SMARC EVK (based on R9A07G054L2):
- memory
- External input clock
- CPG
- Pin controller
- SCIF
- GbEthernet
- Audio Clock
It shares the same carrier board with RZ/G2L with the same pin mapping.
Delete the gpio-hog nodes from pinctrl as they will be added later when
the functionality has been tested.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220110134659.30424-12-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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