arm64: tegra: Rename power-monitor input nodes

Child nodes of the TI INA3221 power monitor device tree node should be
called input@* according to the DT schema.

Signed-off-by: Thierry Reding <tredi

arm64: tegra: Rename power-monitor input nodes

Child nodes of the TI INA3221 power monitor device tree node should be
called input@* according to the DT schema.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Rename thermal zones nodes

The DT schema requires that nodes representing thermal zones include a
"-thermal" suffix in their name.

Signed-off-by: Thierry Reding <treding@nvidia.com>

arm64: tegra: Sort Tegra132 XUSB clocks correctly

Make the order of the clocks and clock-names properties match the order
in the device tree bindings. This isn't strictly necessary from a point
of v

arm64: tegra: Sort Tegra132 XUSB clocks correctly

Make the order of the clocks and clock-names properties match the order
in the device tree bindings. This isn't strictly necessary from a point
of view of the operating system because matching will be done based on
the clock-names, but it makes it easier to validate the device trees
against the DT schema.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Drop unused AHCI clocks on Tegra132

The CML1 and PLL_E clocks are never explicitly used by the AHCI
controller found on Tegra132, so drop them from the corresponding device
tree node.

arm64: tegra: Drop unused AHCI clocks on Tegra132

The CML1 and PLL_E clocks are never explicitly used by the AHCI
controller found on Tegra132, so drop them from the corresponding device
tree node.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fix Tegra132 I2C compatible string list

The I2C controller found on Tegra124 is not fully compatible with the
Tegra114 version, so drop the fallback compatible string from the list.

S

arm64: tegra: Fix Tegra132 I2C compatible string list

The I2C controller found on Tegra124 is not fully compatible with the
Tegra114 version, so drop the fallback compatible string from the list.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add OPP tables on Tegra132

Add peripheral OPP tables on Tegra132 and wire them up to ACTMON and the
EMC. While at it, add the missing "#interconnect-cells" properties to
the memory con

arm64: tegra: Add OPP tables on Tegra132

Add peripheral OPP tables on Tegra132 and wire them up to ACTMON and the
EMC. While at it, add the missing "#interconnect-cells" properties to
the memory controller and external memory controller nodes. Also set the
"#reset-cells" property for the memory controller because it exports the
hotflush reset controls.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fix compatible string for Tegra132 timer

The TKE (time-keeping engine) found on Tegra132 is not backwards
compatible with the version found on Tegra20, so update the compatible
string

arm64: tegra: Fix compatible string for Tegra132 timer

The TKE (time-keeping engine) found on Tegra132 is not backwards
compatible with the version found on Tegra20, so update the compatible
string list accordingly.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Remove unsupported properties on Norrin

The Tegra PMC device tree bindings don't support the "#wake-cells" and
"nvidia,reset-gpio" properties, so remove them.

Signed-off-by: Thierry R

arm64: tegra: Remove unsupported properties on Norrin

The Tegra PMC device tree bindings don't support the "#wake-cells" and
"nvidia,reset-gpio" properties, so remove them.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fix unit-addresses on Norrin

The AS3722 pinmux device tree node doesn't have a "reg" property and
therefore must not have a unit-address, so drop it.

While at it, add missing unit-add

arm64: tegra: Fix unit-addresses on Norrin

The AS3722 pinmux device tree node doesn't have a "reg" property and
therefore must not have a unit-address, so drop it.

While at it, add missing unit-addresses for the charger and smart
battery IC's on the ChromeOS embedded controller's I2C tunnel bus.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add native timer support on Tegra186

The native timers IP block found on NVIDIA Tegra SoCs implements a
watchdog timer that can be used to recover from system hangs. Add the
device tre

arm64: tegra: Add native timer support on Tegra186

The native timers IP block found on NVIDIA Tegra SoCs implements a
watchdog timer that can be used to recover from system hangs. Add the
device tree node on Tegra186.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Rename top-level regulators

Regulators defined at the top level in device tree are no longer part of
a simple bus and therefore don't have a reg property. Nodes without a
reg property

arm64: tegra: Rename top-level regulators

Regulators defined at the top level in device tree are no longer part of
a simple bus and therefore don't have a reg property. Nodes without a
reg property shouldn't have a unit-address either, so drop the unit
address from the node names. To ensure nodes aren't duplicated (in which
case they would end up merged in the final DTB), append the name of the
regulator to the node name.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Rename top-level clocks

Clocks defined at the top level in device tree are no longer part of a
simple bus and therefore don't have a reg property. Nodes without a reg
property shouldn'

arm64: tegra: Rename top-level clocks

Clocks defined at the top level in device tree are no longer part of a
simple bus and therefore don't have a reg property. Nodes without a reg
property shouldn't have a unit-address either, so drop the unit address
from the node names. To ensure nodes aren't duplicated (in which case
they would end up merged in the final DTB), append the name of the clock
to the node name.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add ISO SMMU controller for Tegra194

The display controllers are attached to a separate ARM SMMU instance
that is dedicated to servicing isochronous memory clients. Add this ISO
instan

arm64: tegra: Add ISO SMMU controller for Tegra194

The display controllers are attached to a separate ARM SMMU instance
that is dedicated to servicing isochronous memory clients. Add this ISO
instance of the ARM SMMU to device tree.

Please note that the display controllers are not hooked up to this SMMU
yet, because we are still missing a means to transition framebuffers
used by the bootloader to the kernel.

This based upon an initial patch by Thierry Reding <treding@nvidia.com>.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add NVENC and NVJPG nodes for Tegra186 and Tegra194

Populate the device-tree nodes for NVENC and NVJPG Host1x engines on
Tegra186 and Tegra194.

Signed-off-by: Jon Hunter <jonathanh@nv

arm64: tegra: Add NVENC and NVJPG nodes for Tegra186 and Tegra194

Populate the device-tree nodes for NVENC and NVJPG Host1x engines on
Tegra186 and Tegra194.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add support to enumerate SD in UHS mode

Add support to enumerate SD in UHS mode on Tegra194. Add required
device-tree properties in SDMMC1 and SDMMC3 instances to enable dynamic
pad vo

arm64: tegra: Add support to enumerate SD in UHS mode

Add support to enumerate SD in UHS mode on Tegra194. Add required
device-tree properties in SDMMC1 and SDMMC3 instances to enable dynamic
pad voltage switching and enumerate SD card in UHS-I modes.

Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add NVIDIA Jetson AGX Orin Developer Kit support

The Jetson AGX Orin Developer Kit is a continuation of the Jetson
Developer Kit line using the new NVIDIA Tegra234 (Orin) SoC.

Signed-

arm64: tegra: Add NVIDIA Jetson AGX Orin Developer Kit support

The Jetson AGX Orin Developer Kit is a continuation of the Jetson
Developer Kit line using the new NVIDIA Tegra234 (Orin) SoC.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Describe Tegra234 CPU hierarchy

The NVIDIA Tegra234 SoC has 3 clusters of 4 Cortex-A78AE CPU cores each,
for a total of 12 CPUs. Each CPU has 64 KiB instruction and data caches
with ea

arm64: tegra: Describe Tegra234 CPU hierarchy

The NVIDIA Tegra234 SoC has 3 clusters of 4 Cortex-A78AE CPU cores each,
for a total of 12 CPUs. Each CPU has 64 KiB instruction and data caches
with each cluster having an additional 256 KiB unified L2 cache and a 2
MiB L3 cache.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add main and AON GPIO controllers on Tegra234

These two controllers expose general purpose I/O pins that can be used
to control or monitor a variety of signals.

Signed-off-by: Thierry

arm64: tegra: Add main and AON GPIO controllers on Tegra234

These two controllers expose general purpose I/O pins that can be used
to control or monitor a variety of signals.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add Tegra234 TCU device

Add a device for TCU (Tegra Combined UART) used for serial console.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <tredi

arm64: tegra: Add Tegra234 TCU device

Add a device for TCU (Tegra Combined UART) used for serial console.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fill in properties for Tegra234 eMMC

Add missing properties to the eMMC controller, as required to use it on
actual hardware.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Si

arm64: tegra: Fill in properties for Tegra234 eMMC

Add missing properties to the eMMC controller, as required to use it on
actual hardware.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Update Tegra234 BPMP channel addresses

On final Tegra234 systems, shared memory for communication with BPMP is
located at offset 0x70000 in SYSRAM.

Signed-off-by: Mikko Perttunen <mpe

arm64: tegra: Update Tegra234 BPMP channel addresses

On final Tegra234 systems, shared memory for communication with BPMP is
located at offset 0x70000 in SYSRAM.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add clock for Tegra234 RTC

The RTC device requires a clock. Add it.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

arm64: tegra: Fixup SYSRAM references

The json-schema bindings for SRAM expect the nodes to be called "sram"
rather than "sysram" or "shmem". Furthermore, place the brackets around
the SYSRAM refere

arm64: tegra: Fixup SYSRAM references

The json-schema bindings for SRAM expect the nodes to be called "sram"
rather than "sysram" or "shmem". Furthermore, place the brackets around
the SYSRAM references such that a two-element array is created rather
than a two-element array nested in a single-element array. This is not
relevant for device tree itself, but allows the nodes to be properly
validated against json-schema bindings.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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