arm64: tegra: Add dma-coherent for Tegra194 VIC

DMA operations for the Tegra194 Video Image Compositor (VIC) are
coherent and so populate the 'dma-coherent' property.

Signed-off-by: Jon Hunter <jon

arm64: tegra: Add dma-coherent for Tegra194 VIC

DMA operations for the Tegra194 Video Image Compositor (VIC) are
coherent and so populate the 'dma-coherent' property.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Rename Ethernet PHY nodes

Name the Ethernet PHY device tree nodes as expected by the DT schema.

Signed-off-by: Thierry Reding <treding@nvidia.com>

arm64: tegra: Remove unused only-1-8-v properties

The only-1-8-v property is not support by an DT schema, so drop it.

Signed-off-by: Thierry Reding <treding@nvidia.com>

arm64: tegra: Sort Tegra210 XUSB clocks correctly

Make the order of the clocks and clock-names properties match the order
in the device tree bindings. This isn't strictly necessary from a point
of v

arm64: tegra: Sort Tegra210 XUSB clocks correctly

Make the order of the clocks and clock-names properties match the order
in the device tree bindings. This isn't strictly necessary from a point
of view of the operating system because matching will be done based on
the clock-names, but it makes it easier to validate the device trees
against the DT schema.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add missing TSEC properties on Tegra210

Add missing interrupts, clocks, clock-names, reset and reset-names
properties for the TSEC blocks found on Tegra210.

Signed-off-by: Thierry Red

arm64: tegra: Add missing TSEC properties on Tegra210

Add missing interrupts, clocks, clock-names, reset and reset-names
properties for the TSEC blocks found on Tegra210.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: jetson-nano: Remove extra PLL power supplies for PCIe and XUSB

The XUSB pad controller handles the various PLL power supplies, so
remove any references to them from the PCIe and XUSB c

arm64: tegra: jetson-nano: Remove extra PLL power supplies for PCIe and XUSB

The XUSB pad controller handles the various PLL power supplies, so
remove any references to them from the PCIe and XUSB controller device
tree nodes.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: smaug: Remove extra PLL power supplies for XUSB

The XUSB pad controller handles the various PLL power supplies, so
remove any references to them from the XUSB controller device tree
no

arm64: tegra: smaug: Remove extra PLL power supplies for XUSB

The XUSB pad controller handles the various PLL power supplies, so
remove any references to them from the XUSB controller device tree
node.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: jetson-tx1: Remove extra PLL power supplies for PCIe and XUSB

The XUSB pad controller handles the various PLL power supplies, so
remove any references to them from the PCIe and XUSB co

arm64: tegra: jetson-tx1: Remove extra PLL power supplies for PCIe and XUSB

The XUSB pad controller handles the various PLL power supplies, so
remove any references to them from the PCIe and XUSB controller device
tree nodes.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Rename GPIO hog nodes to match schema

GPIO hog nodes must have a "hog-" prefix or "-hog" suffix according to
the DT schema. Rename all such nodes to allow validation to pass.

Signed-o

arm64: tegra: Rename GPIO hog nodes to match schema

GPIO hog nodes must have a "hog-" prefix or "-hog" suffix according to
the DT schema. Rename all such nodes to allow validation to pass.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Remove unsupported regulator properties

Remove the unsupported "regulator-disable-ramp-delay" properties which
ended up in various DTS files for some reason.

Signed-off-by: Thierry Re

arm64: tegra: Remove unsupported regulator properties

Remove the unsupported "regulator-disable-ramp-delay" properties which
ended up in various DTS files for some reason.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Rename TCU node to "serial"

The TCU is basically a serial port (albeit a fancy one), so it should be
named "serial".

Signed-off-by: Thierry Reding <treding@nvidia.com>

arm64: tegra: Remove undocumented Tegra194 PCIe "core_m" clock

The "core_m" clock is not documented in the Tegra194 PCIe device tree
bindings, so remove it.

Signed-off-by: Thierry Reding <treding@n

arm64: tegra: Remove undocumented Tegra194 PCIe "core_m" clock

The "core_m" clock is not documented in the Tegra194 PCIe device tree
bindings, so remove it.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Drop unused properties for Tegra194 PCIe

The num-viewport property is never used and can be dropped, whereas the
"iommus" property is not needed since we use "iommu-map-mask" and
"iomm

arm64: tegra: Drop unused properties for Tegra194 PCIe

The num-viewport property is never used and can be dropped, whereas the
"iommus" property is not needed since we use "iommu-map-mask" and
"iommu-map" already.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fix Tegra194 HSP compatible string

The HSP instances on Tegra194 are not fully compatible with the version
found on Tegra186, so drop the fallback compatible string from the list.

Sig

arm64: tegra: Fix Tegra194 HSP compatible string

The HSP instances on Tegra194 are not fully compatible with the version
found on Tegra186, so drop the fallback compatible string from the list.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Drop unsupported nvidia,lpdr property

The Tegra194 pinmux DT bindings do not define the nvidia,lpdr property,
so drop them from the device trees that have listed them.

Signed-off-by:

arm64: tegra: Drop unsupported nvidia,lpdr property

The Tegra194 pinmux DT bindings do not define the nvidia,lpdr property,
so drop them from the device trees that have listed them.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Use JEDEC vendor prefix for SPI NOR flash chips

The standard "jedec," vendor prefix should be used for SPI NOR flash
chips. This allows the right DT schema to be picked for validation.

arm64: tegra: Use JEDEC vendor prefix for SPI NOR flash chips

The standard "jedec," vendor prefix should be used for SPI NOR flash
chips. This allows the right DT schema to be picked for validation.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Drop unit-address for audio card graph endpoints

Audio graph endpoints don't have a "reg" property, so they shouldn't
have a unit-address either.

Signed-off-by: Thierry Reding <tredin

arm64: tegra: Drop unit-address for audio card graph endpoints

Audio graph endpoints don't have a "reg" property, so they shouldn't
have a unit-address either.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Adjust length of CCPLEX cluster MMIO region

The Tegra186 CCPLEX cluster register region is 4 MiB is length, not 4
MiB - 1. This was likely presumed to be the "limit" rather than length

arm64: tegra: Adjust length of CCPLEX cluster MMIO region

The Tegra186 CCPLEX cluster register region is 4 MiB is length, not 4
MiB - 1. This was likely presumed to be the "limit" rather than length.
Fix it up.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fix Tegra186 compatible string list

The I2C controller found on Tegra186 is not fully compatible with the
Tegra210 version, so drop the fallback compatible string from the list.

Signe

arm64: tegra: Fix Tegra186 compatible string list

The I2C controller found on Tegra186 is not fully compatible with the
Tegra210 version, so drop the fallback compatible string from the list.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Rename power-monitor input nodes

Child nodes of the TI INA3221 power monitor device tree node should be
called input@* according to the DT schema.

Signed-off-by: Thierry Reding <tredi

arm64: tegra: Rename power-monitor input nodes

Child nodes of the TI INA3221 power monitor device tree node should be
called input@* according to the DT schema.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Rename thermal zones nodes

The DT schema requires that nodes representing thermal zones include a
"-thermal" suffix in their name.

Signed-off-by: Thierry Reding <treding@nvidia.com>

arm64: tegra: Sort Tegra132 XUSB clocks correctly

Make the order of the clocks and clock-names properties match the order
in the device tree bindings. This isn't strictly necessary from a point
of v

arm64: tegra: Sort Tegra132 XUSB clocks correctly

Make the order of the clocks and clock-names properties match the order
in the device tree bindings. This isn't strictly necessary from a point
of view of the operating system because matching will be done based on
the clock-names, but it makes it easier to validate the device trees
against the DT schema.

Signed-off-by: Thierry Reding <treding@nvidia.com>

show more ...

arm64: tegra: Drop unused AHCI clocks on Tegra132

The CML1 and PLL_E clocks are never explicitly used by the AHCI
controller found on Tegra132, so drop them from the corresponding device
tree node.

arm64: tegra: Drop unused AHCI clocks on Tegra132

The CML1 and PLL_E clocks are never explicitly used by the AHCI
controller found on Tegra132, so drop them from the corresponding device
tree node.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fix Tegra132 I2C compatible string list

The I2C controller found on Tegra124 is not fully compatible with the
Tegra114 version, so drop the fallback compatible string from the list.

S

arm64: tegra: Fix Tegra132 I2C compatible string list

The I2C controller found on Tegra124 is not fully compatible with the
Tegra114 version, so drop the fallback compatible string from the list.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add OPP tables on Tegra132

Add peripheral OPP tables on Tegra132 and wire them up to ACTMON and the
EMC. While at it, add the missing "#interconnect-cells" properties to
the memory con

arm64: tegra: Add OPP tables on Tegra132

Add peripheral OPP tables on Tegra132 and wire them up to ACTMON and the
EMC. While at it, add the missing "#interconnect-cells" properties to
the memory controller and external memory controller nodes. Also set the
"#reset-cells" property for the memory controller because it exports the
hotflush reset controls.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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