#
09a0774a |
| 05-Sep-2019 |
Vidya Sagar <vidyas@nvidia.com> |
arm64: tegra: Add PCIe slot supply information in p2972-0000 platform
Add 3.3V and 12V supplies regulators information of x16 PCIe slot in p2972-0000 platform which is owned by C5 controller and als
arm64: tegra: Add PCIe slot supply information in p2972-0000 platform
Add 3.3V and 12V supplies regulators information of x16 PCIe slot in p2972-0000 platform which is owned by C5 controller and also enable C5 controller.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
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Revision tags: v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11, v5.1.10 |
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a586c88e |
| 12-Jun-2019 |
Vidya Sagar <vidyas@nvidia.com> |
arm64: tegra: Enable PCIe slots in P2972-0000 board
Enable PCIe controller nodes to enable respective PCIe slots on P2972-0000 board. Following is the ownership of slots by different PCIe controller
arm64: tegra: Enable PCIe slots in P2972-0000 board
Enable PCIe controller nodes to enable respective PCIe slots on P2972-0000 board. Following is the ownership of slots by different PCIe controllers. Controller-0 : M.2 Key-M slot Controller-1 : On-board Marvell eSATA controller Controller-3 : M.2 Key-E slot
Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.1.9, v5.1.8, v5.1.7, v5.1.6, v5.1.5 |
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f85d82e5 |
| 22-May-2019 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Clarify that P2888 is the Jetson AGX Xavier
P2888 is the internal part number for the Jetson AGX Xavier module. Clarify that using the DT model property.
Acked-by: Jon Hunter <jonatha
arm64: tegra: Clarify that P2888 is the Jetson AGX Xavier
P2888 is the internal part number for the Jetson AGX Xavier module. Clarify that using the DT model property.
Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.1.4, v5.1.3, v5.1.2, v5.1.1, v5.0.14, v5.1, v5.0.13, v5.0.12, v5.0.11, v5.0.10, v5.0.9, v5.0.8, v5.0.7, v5.0.6, v5.0.5, v5.0.4, v5.0.3, v4.19.29, v5.0.2, v4.19.28, v5.0.1, v4.19.27, v5.0, v4.19.26 |
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#
73207330 |
| 26-Feb-2019 |
Jon Hunter <jonathanh@nvidia.com> |
arm64: tegra: Add supply for temperature sensor on P2888
The VCC supply property is not populated for the temperature sensor on the P2888 board and so the following warning is observed on boot ...
arm64: tegra: Add supply for temperature sensor on P2888
The VCC supply property is not populated for the temperature sensor on the P2888 board and so the following warning is observed on boot ...
lm90 0-004c: 0-004c supply vcc not found, using dummy regulator
On the P2888 board, the VCC supply for the temperature sensor is connected to the 'vdd_1v8ls' rail. Add the 'vcc-supply' property for the temperature sensor to prevent this warning message from occurring.
Fixes: 8b457812f54b ('arm64: tegra: Add temperature sensor on P2888') Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v4.19.25, v4.19.24, v4.19.23, v4.19.22, v4.19.21, v4.19.20, v4.19.19, v4.19.18, v4.19.17, v4.19.16, v4.19.15, v4.19.14, v4.19.13, v4.19.12, v4.19.11, v4.19.10, v4.19.9, v4.19.8, v4.19.7, v4.19.6 |
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#
6ab6a4d2 |
| 28-Nov-2018 |
Mikko Perttunen <mperttunen@nvidia.com> |
arm64: tegra: Mark TCU as primary serial port on Tegra194 P2888
The Tegra Combined UART is the proper primary serial port on P2888, so use it.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
arm64: tegra: Mark TCU as primary serial port on Tegra194 P2888
The Tegra Combined UART is the proper primary serial port on P2888, so use it.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
8b457812 |
| 28-Nov-2018 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Add temperature sensor on P2888
The P2888 processor module contains a TI TMP451 temperature sensor with two channels. These are used to measure the temperatures at different locations
arm64: tegra: Add temperature sensor on P2888
The P2888 processor module contains a TI TMP451 temperature sensor with two channels. These are used to measure the temperatures at different locations on the module.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
3ae50e83 |
| 28-Nov-2018 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: p2888: Enable on-die RTC
The on-die RTC isn't hooked up to a backup battery, so it isn't useful to track time across reboots, but as long as power remains enabled, it keeps track of ti
arm64: tegra: p2888: Enable on-die RTC
The on-die RTC isn't hooked up to a backup battery, so it isn't useful to track time across reboots, but as long as power remains enabled, it keeps track of time accurately and can be used to wake the system from sleep, for example.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v4.19.5 |
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#
33c038e4 |
| 23-Nov-2018 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Enable HDMI on P2972-0000
Add the 5V HDMI regulator and hook up the VDD_1V0 and VDD_1V8HS supplies from the PMIC to the display block. Also enable the display hub which is responsible
arm64: tegra: Enable HDMI on P2972-0000
Add the 5V HDMI regulator and hook up the VDD_1V0 and VDD_1V8HS supplies from the PMIC to the display block. Also enable the display hub which is responsible for instantiating the display controllers. Finally, enable the third SOR that drives the TMDS signals to the HDMI connector.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v4.19.4, v4.18.20, v4.19.3, v4.18.19, v4.19.2, v4.18.18, v4.18.17, v4.19.1, v4.19, v4.18.16, v4.18.15, v4.18.14, v4.18.13, v4.18.12, v4.18.11, v4.18.10, v4.18.9, v4.18.7, v4.18.6, v4.18.5, v4.17.18, v4.18.4, v4.18.3, v4.17.17, v4.18.2, v4.17.16, v4.17.15, v4.18.1, v4.18, v4.17.14, v4.17.13, v4.17.12, v4.17.11, v4.17.10, v4.17.9, v4.17.8, v4.17.7, v4.17.6, v4.17.5, v4.17.4, v4.17.3 |
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#
f89b58ce |
| 20-Jun-2018 |
Mikko Perttunen <mperttunen@nvidia.com> |
arm64: tegra: Add ethernet controller on Tegra194
The Tegra194 contains the same ethernet controller as the Tegra186. Add the device tree node for it, and correspondingly the PHY node on the board d
arm64: tegra: Add ethernet controller on Tegra194
The Tegra194 contains the same ethernet controller as the Tegra186. Add the device tree node for it, and correspondingly the PHY node on the board device tree.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
ef633bfc |
| 20-Jun-2018 |
Mikko Perttunen <mperttunen@nvidia.com> |
arm64: tegra: Enable card detect for SD card on P2888
Now that we have a GPIO controller, enable the card detect GPIO for the SD card slot.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Si
arm64: tegra: Enable card detect for SD card on P2888
Now that we have a GPIO controller, enable the card detect GPIO for the SD card slot.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v4.17.2, v4.17.1, v4.17, v4.16 |
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#
b8656c67 |
| 20-Feb-2018 |
Mikko Perttunen <mperttunen@nvidia.com> |
arm64: tegra: Add device tree for the Tegra194 P2972-0000 board
Add device tree files for the Tegra194 P2972-0000 development board. The board consists of the P2888 compute module and the P2822 base
arm64: tegra: Add device tree for the Tegra194 P2972-0000 board
Add device tree files for the Tegra194 P2972-0000 development board. The board consists of the P2888 compute module and the P2822 baseboard.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10 |
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#
a4387f29 |
| 16-Sep-2020 |
Jon Hunter <jonathanh@nvidia.com> |
arm64: tegra: Add label properties for EEPROMs Populate the label property for the AT24 EEPROMs on the various Jetson platforms. Note that the name 'module' is used to identify the EEPRO
arm64: tegra: Add label properties for EEPROMs Populate the label property for the AT24 EEPROMs on the various Jetson platforms. Note that the name 'module' is used to identify the EEPROM on the processor module board and the name 'system' is used to identify the EEPROM on the main base board (which is sometimes referred to as the carrier board). Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56 |
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#
228f1e6a |
| 03-Aug-2020 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Add ID EEPROMs on Jetson AGX Xavier The P2888 processor module contains an EEPROM that provides means of identifying the module. The P2822 carrier board contains the same E
arm64: tegra: Add ID EEPROMs on Jetson AGX Xavier The P2888 processor module contains an EEPROM that provides means of identifying the module. The P2822 carrier board contains the same EEPROM with information identifying the carrier board. Both of them ar accessed via the GEN_I2C1 bus. Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9 |
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#
7d6dbb7b |
| 14-Jul-2020 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Sort aliases alphabetically Most device tree files already do this, so update the remaining ones for consistency. Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47 |
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#
8b3aee8f |
| 12-Jun-2020 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Rename cbb@0 to bus@0 on Tegra194 The control backbone is a simple-bus and hence its device tree node should be named "bus@<unit-address>" according to the bindings.
arm64: tegra: Rename cbb@0 to bus@0 on Tegra194 The control backbone is a simple-bus and hence its device tree node should be named "bus@<unit-address>" according to the bindings. Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
7517248a |
| 12-Jun-2020 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Remove simple regulators bus The standard way to do this is to list out the regulators at the top- level. Adopt the standard way to fix validation. Signed-off-by:
arm64: tegra: Remove simple regulators bus The standard way to do this is to list out the regulators at the top- level. Adopt the standard way to fix validation. Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
67bb17f6 |
| 11-Jun-2020 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Rename sdhci nodes to mmc The new json-schema based validation tools require SD/MMC controller nodes to be named mmc. Rename all references to them. Signed-off-by:
arm64: tegra: Rename sdhci nodes to mmc The new json-schema based validation tools require SD/MMC controller nodes to be named mmc. Rename all references to them. Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
a10b9a20 |
| 12-Jun-2020 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Add missing #phy-cells property on Jetson AGX Xavier PHYs need to have a #phy-cells property that defines how many cells are required in their specifier. The standard Ether
arm64: tegra: Add missing #phy-cells property on Jetson AGX Xavier PHYs need to have a #phy-cells property that defines how many cells are required in their specifier. The standard Ethernet PHY doesn't require a specifier, so set its #phy-cells to 0. Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40 |
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#
4012ab12 |
| 07-May-2020 |
Jon Hunter <jonathanh@nvidia.com> |
arm64: tegra: Allow the PMIC RTC to wakeup Jetson Xavier The PMIC RTC is currently unable to wakeup Tegra194 on the Jetson Xavier platform because the interrupt from the PMIC is not usin
arm64: tegra: Allow the PMIC RTC to wakeup Jetson Xavier The PMIC RTC is currently unable to wakeup Tegra194 on the Jetson Xavier platform because the interrupt from the PMIC is not usin the PMC as the interrupt parent but the GIC directly. Update the PMIC interrupt to use the PMC as the interrupt parent so that the PMIC RTC alarms can wakeup the device. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.4.39, v5.4.38, v5.4.37 |
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#
bba25915 |
| 01-May-2020 |
Jon Hunter <jonathanh@nvidia.com> |
arm64: tegra: Fix ethernet phy-mode for Jetson Xavier The 'phy-mode' property is currently defined as 'rgmii' for Jetson Xavier. This indicates that the RGMII RX and TX delays are set by
arm64: tegra: Fix ethernet phy-mode for Jetson Xavier The 'phy-mode' property is currently defined as 'rgmii' for Jetson Xavier. This indicates that the RGMII RX and TX delays are set by the MAC and the internal delays set by the PHY are not used. If the Marvell PHY driver is enabled, such that it is used and not the generic PHY, ethernet failures are seen (DHCP is failing to obtain an IP address) and this is caused because the Marvell PHY driver is disabling the internal RX and TX delays. For Jetson Xavier the internal PHY RX and TX delay should be used and so fix this by setting the 'phy-mode' to 'rgmii-id' and not 'rgmii'. Fixes: f89b58ce71a9 ("arm64: tegra: Add ethernet controller on Tegra194") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20 |
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#
92f37c0a |
| 12-Feb-2020 |
JC Kuo <jckuo@nvidia.com> |
arm64: tegra: Enable XUSB host in P2972-0000 board This commit enables XUSB host and pad controller in Tegra194 P2972-0000 board. Signed-off-by: JC Kuo <jckuo@nvidia.com> Si
arm64: tegra: Enable XUSB host in P2972-0000 board This commit enables XUSB host and pad controller in Tegra194 P2972-0000 board. Signed-off-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7 |
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#
be9b887f |
| 22-Dec-2019 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Add the memory subsystem on Tegra194 The memory subsystem on Tegra194 encompasses both the memory and external memory controllers. The EMC is represented as a subnode of th
arm64: tegra: Add the memory subsystem on Tegra194 The memory subsystem on Tegra194 encompasses both the memory and external memory controllers. The EMC is represented as a subnode of the MC and a ranges property is used to describe the register ranges. A dma-ranges property is also added to describe that all memory clients can address up to 39 bits using the memory controller client interface (MCCIF), unless otherwise limited by the DMA engines of the hardware. A memory client can technically use 40 bits of addresses, but the memory controller on Tegra194 uses bit 39 to determine the XBAR format used to access memory. Use of this bit needs to be explicitly controlled by the operating system drivers for devices that can use this on-the-fly format conversion. Using the dma-ranges property prevents the operating system from using the bit implicitly, for example in I/O virtual address mappings. Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11, v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5, v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16 |
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#
c90b8f15 |
| 27-Jun-2019 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: p2888: Rename regulators for consistency Some of the PMIC regulators had names that don't match the schematics. Rename them so that it is easier to cross-reference with the
arm64: tegra: p2888: Rename regulators for consistency Some of the PMIC regulators had names that don't match the schematics. Rename them so that it is easier to cross-reference with the hardware documentation. Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
2b6b3940 |
| 01-Oct-2019 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Add ethernet alias on Jetson AGX Xavier The Tegra194 EQOS controller is used as primary Ethernet interface. Set the ethernet0 alias to reflect that. Generic bootlo
arm64: tegra: Add ethernet alias on Jetson AGX Xavier The Tegra194 EQOS controller is used as primary Ethernet interface. Set the ethernet0 alias to reflect that. Generic bootloader code can use this to find the primary Ethernet device and set the MAC address, for example. Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
eef97c2a |
| 26-Jul-2019 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Add unit-address for CBB on Tegra194 The control back-bone (CBB) starts at physical address 0, so give it a unit-address to comply with standard naming practices checked fo
arm64: tegra: Add unit-address for CBB on Tegra194 The control back-bone (CBB) starts at physical address 0, so give it a unit-address to comply with standard naming practices checked for by the device tree compiler. Signed-off-by: Thierry Reding <treding@nvidia.com>
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