Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80 |
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#
79ed18d9 |
| 22-Nov-2022 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Sort nodes by unit-address, then alphabetically
Nodes in device tree should be sorted by unit-address, followed by nodes without a unit-address, sorted alphabetically. Some exceptions
arm64: tegra: Sort nodes by unit-address, then alphabetically
Nodes in device tree should be sorted by unit-address, followed by nodes without a unit-address, sorted alphabetically. Some exceptions are the top-level aliases, chosen, firmware, memory and reserved-memory nodes, which are expected to come first.
These rules apply recursively with some exceptions, such as pinmux nodes or regulator nodes, which often follow more complicated ordering (often by "importance").
While at it, change the name of some of the nodes to follow standard naming conventions, which helps with the sorting order and reduces the amount of warnings from the DT validation tools.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6 |
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#
501c9e7c |
| 28-Oct-2022 |
Jon Hunter <jonathanh@nvidia.com> |
arm64: tegra: Update console for Jetson Xavier and Orin
The Tegra Combined UART (TCU) is the default serial interface for Jetson Xavier and Orin platforms and so update the bootargs for these platfo
arm64: tegra: Update console for Jetson Xavier and Orin
The Tegra Combined UART (TCU) is the default serial interface for Jetson Xavier and Orin platforms and so update the bootargs for these platforms to use the TCU.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47 |
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#
b415bb7c |
| 12-Jun-2022 |
Tamás Szűcs <tszucs@protonmail.ch> |
arm64: tegra: Fix SDMMC1 CD on P2888
Hook SDMMC1 CD up with CVM GPIO02 (SOC_GPIO11) used for card detection on J4 (uSD socket) on the carrier.
Fixes: ef633bfc21e9 ("arm64: tegra: Enable card detect
arm64: tegra: Fix SDMMC1 CD on P2888
Hook SDMMC1 CD up with CVM GPIO02 (SOC_GPIO11) used for card detection on J4 (uSD socket) on the carrier.
Fixes: ef633bfc21e9 ("arm64: tegra: Enable card detect for SD card on P2888") Signed-off-by: Tamás Szűcs <tszucs@protonmail.ch> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36 |
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#
2f477ee3 |
| 25-Apr-2022 |
Arnd Bergmann <arnd@arndb.de> |
Revert "arm64: dts: tegra: Fix boolean properties with values"
This reverts commit 1a67653de0dd, which caused a boot regression.
The behavior of the "drive-push-pull" in the kernel does not match w
Revert "arm64: dts: tegra: Fix boolean properties with values"
This reverts commit 1a67653de0dd, which caused a boot regression.
The behavior of the "drive-push-pull" in the kernel does not match what the binding document describes. Revert Rob's patch to make the DT match the kernel again, rather than the binding.
Link: https://lore.kernel.org/lkml/YlVAy95eF%2F9b1nmu@orome/ Reported-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Revision tags: v5.15.35, v5.15.34, v5.15.33 |
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1a67653d |
| 06-Apr-2022 |
Rob Herring <robh@kernel.org> |
arm64: dts: tegra: Fix boolean properties with values
Boolean properties in DT are present or not present and don't take a value. A property such as 'foo = <0>;' evaluated to true. IOW, the value do
arm64: dts: tegra: Fix boolean properties with values
Boolean properties in DT are present or not present and don't take a value. A property such as 'foo = <0>;' evaluated to true. IOW, the value doesn't matter.
It may have been intended that 0 values are false, but there is no change in behavior with this patch.
Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/Yk3nShkFzNJaI3/Z@robh.at.kernel.org' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Revision tags: v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8 |
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#
553f0736 |
| 08-Dec-2021 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Rename Ethernet PHY nodes
Name the Ethernet PHY device tree nodes as expected by the DT schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.15.7 |
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097e01c6 |
| 06-Dec-2021 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Rename top-level regulators
Regulators defined at the top level in device tree are no longer part of a simple bus and therefore don't have a reg property. Nodes without a reg property
arm64: tegra: Rename top-level regulators
Regulators defined at the top level in device tree are no longer part of a simple bus and therefore don't have a reg property. Nodes without a reg property shouldn't have a unit-address either, so drop the unit address from the node names. To ensure nodes aren't duplicated (in which case they would end up merged in the final DTB), append the name of the regulator to the node name.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
a34982fd |
| 12-Jun-2022 |
Tamás Szűcs <tszucs@protonmail.ch> |
arm64: tegra: Fix SDMMC1 CD on P2888
[ Upstream commit b415bb7c976f1d595ed752001c0938f702645dab ]
Hook SDMMC1 CD up with CVM GPIO02 (SOC_GPIO11) used for card detection on J4 (uSD socket) on the ca
arm64: tegra: Fix SDMMC1 CD on P2888
[ Upstream commit b415bb7c976f1d595ed752001c0938f702645dab ]
Hook SDMMC1 CD up with CVM GPIO02 (SOC_GPIO11) used for card detection on J4 (uSD socket) on the carrier.
Fixes: ef633bfc21e9 ("arm64: tegra: Enable card detect for SD card on P2888") Signed-off-by: Tamás Szűcs <tszucs@protonmail.ch> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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Revision tags: v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50 |
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#
dbb096d3 |
| 11-Jul-2021 |
Dmitry Osipenko <digetx@gmail.com> |
arm64: tegra194: p2888: Correct interrupt trigger type of temperature sensor
The LM90 temperature sensor should use edge-triggered interrupt because LM90 hardware doesn't deassert interrupt line unt
arm64: tegra194: p2888: Correct interrupt trigger type of temperature sensor
The LM90 temperature sensor should use edge-triggered interrupt because LM90 hardware doesn't deassert interrupt line until temperature is back to normal state, which results in interrupt storm. Correct the interrupt trigger type.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14 |
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40b4d824 |
| 18-Jan-2021 |
JC Kuo <jckuo@nvidia.com> |
arm64: tegra: Enable Jetson-Xavier J512 USB host
This commit enables USB host mode at J512 type-C port of Jetson-Xavier.
Signed-off-by: JC Kuo <jckuo@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvi
arm64: tegra: Enable Jetson-Xavier J512 USB host
This commit enables USB host mode at J512 type-C port of Jetson-Xavier.
Signed-off-by: JC Kuo <jckuo@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10 |
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#
a4387f29 |
| 16-Sep-2020 |
Jon Hunter <jonathanh@nvidia.com> |
arm64: tegra: Add label properties for EEPROMs
Populate the label property for the AT24 EEPROMs on the various Jetson platforms. Note that the name 'module' is used to identify the EEPROM on the pro
arm64: tegra: Add label properties for EEPROMs
Populate the label property for the AT24 EEPROMs on the various Jetson platforms. Note that the name 'module' is used to identify the EEPROM on the processor module board and the name 'system' is used to identify the EEPROM on the main base board (which is sometimes referred to as the carrier board).
Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56 |
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228f1e6a |
| 03-Aug-2020 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Add ID EEPROMs on Jetson AGX Xavier
The P2888 processor module contains an EEPROM that provides means of identifying the module. The P2822 carrier board contains the same EEPROM with i
arm64: tegra: Add ID EEPROMs on Jetson AGX Xavier
The P2888 processor module contains an EEPROM that provides means of identifying the module. The P2822 carrier board contains the same EEPROM with information identifying the carrier board. Both of them ar accessed via the GEN_I2C1 bus.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9 |
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7d6dbb7b |
| 14-Jul-2020 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Sort aliases alphabetically
Most device tree files already do this, so update the remaining ones for consistency.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47 |
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8b3aee8f |
| 12-Jun-2020 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Rename cbb@0 to bus@0 on Tegra194
The control backbone is a simple-bus and hence its device tree node should be named "bus@<unit-address>" according to the bindings.
Signed-off-by: Th
arm64: tegra: Rename cbb@0 to bus@0 on Tegra194
The control backbone is a simple-bus and hence its device tree node should be named "bus@<unit-address>" according to the bindings.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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7517248a |
| 12-Jun-2020 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Remove simple regulators bus
The standard way to do this is to list out the regulators at the top- level. Adopt the standard way to fix validation.
Signed-off-by: Thierry Reding <tred
arm64: tegra: Remove simple regulators bus
The standard way to do this is to list out the regulators at the top- level. Adopt the standard way to fix validation.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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67bb17f6 |
| 11-Jun-2020 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Rename sdhci nodes to mmc
The new json-schema based validation tools require SD/MMC controller nodes to be named mmc. Rename all references to them.
Signed-off-by: Thierry Reding <tre
arm64: tegra: Rename sdhci nodes to mmc
The new json-schema based validation tools require SD/MMC controller nodes to be named mmc. Rename all references to them.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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a10b9a20 |
| 12-Jun-2020 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Add missing #phy-cells property on Jetson AGX Xavier
PHYs need to have a #phy-cells property that defines how many cells are required in their specifier. The standard Ethernet PHY does
arm64: tegra: Add missing #phy-cells property on Jetson AGX Xavier
PHYs need to have a #phy-cells property that defines how many cells are required in their specifier. The standard Ethernet PHY doesn't require a specifier, so set its #phy-cells to 0.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40 |
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4012ab12 |
| 07-May-2020 |
Jon Hunter <jonathanh@nvidia.com> |
arm64: tegra: Allow the PMIC RTC to wakeup Jetson Xavier
The PMIC RTC is currently unable to wakeup Tegra194 on the Jetson Xavier platform because the interrupt from the PMIC is not usin the PMC as
arm64: tegra: Allow the PMIC RTC to wakeup Jetson Xavier
The PMIC RTC is currently unable to wakeup Tegra194 on the Jetson Xavier platform because the interrupt from the PMIC is not usin the PMC as the interrupt parent but the GIC directly. Update the PMIC interrupt to use the PMC as the interrupt parent so that the PMIC RTC alarms can wakeup the device.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.4.39, v5.4.38, v5.4.37 |
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#
bba25915 |
| 01-May-2020 |
Jon Hunter <jonathanh@nvidia.com> |
arm64: tegra: Fix ethernet phy-mode for Jetson Xavier
The 'phy-mode' property is currently defined as 'rgmii' for Jetson Xavier. This indicates that the RGMII RX and TX delays are set by the MAC and
arm64: tegra: Fix ethernet phy-mode for Jetson Xavier
The 'phy-mode' property is currently defined as 'rgmii' for Jetson Xavier. This indicates that the RGMII RX and TX delays are set by the MAC and the internal delays set by the PHY are not used.
If the Marvell PHY driver is enabled, such that it is used and not the generic PHY, ethernet failures are seen (DHCP is failing to obtain an IP address) and this is caused because the Marvell PHY driver is disabling the internal RX and TX delays. For Jetson Xavier the internal PHY RX and TX delay should be used and so fix this by setting the 'phy-mode' to 'rgmii-id' and not 'rgmii'.
Fixes: f89b58ce71a9 ("arm64: tegra: Add ethernet controller on Tegra194") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20 |
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92f37c0a |
| 12-Feb-2020 |
JC Kuo <jckuo@nvidia.com> |
arm64: tegra: Enable XUSB host in P2972-0000 board
This commit enables XUSB host and pad controller in Tegra194 P2972-0000 board.
Signed-off-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Red
arm64: tegra: Enable XUSB host in P2972-0000 board
This commit enables XUSB host and pad controller in Tegra194 P2972-0000 board.
Signed-off-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7 |
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be9b887f |
| 22-Dec-2019 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Add the memory subsystem on Tegra194
The memory subsystem on Tegra194 encompasses both the memory and external memory controllers. The EMC is represented as a subnode of the MC and a r
arm64: tegra: Add the memory subsystem on Tegra194
The memory subsystem on Tegra194 encompasses both the memory and external memory controllers. The EMC is represented as a subnode of the MC and a ranges property is used to describe the register ranges.
A dma-ranges property is also added to describe that all memory clients can address up to 39 bits using the memory controller client interface (MCCIF), unless otherwise limited by the DMA engines of the hardware. A memory client can technically use 40 bits of addresses, but the memory controller on Tegra194 uses bit 39 to determine the XBAR format used to access memory. Use of this bit needs to be explicitly controlled by the operating system drivers for devices that can use this on-the-fly format conversion. Using the dma-ranges property prevents the operating system from using the bit implicitly, for example in I/O virtual address mappings.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11, v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5, v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16 |
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#
c90b8f15 |
| 27-Jun-2019 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: p2888: Rename regulators for consistency
Some of the PMIC regulators had names that don't match the schematics. Rename them so that it is easier to cross-reference with the hardware do
arm64: tegra: p2888: Rename regulators for consistency
Some of the PMIC regulators had names that don't match the schematics. Rename them so that it is easier to cross-reference with the hardware documentation.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
2b6b3940 |
| 01-Oct-2019 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Add ethernet alias on Jetson AGX Xavier
The Tegra194 EQOS controller is used as primary Ethernet interface. Set the ethernet0 alias to reflect that.
Generic bootloader code can use th
arm64: tegra: Add ethernet alias on Jetson AGX Xavier
The Tegra194 EQOS controller is used as primary Ethernet interface. Set the ethernet0 alias to reflect that.
Generic bootloader code can use this to find the primary Ethernet device and set the MAC address, for example.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
eef97c2a |
| 26-Jul-2019 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Add unit-address for CBB on Tegra194
The control back-bone (CBB) starts at physical address 0, so give it a unit-address to comply with standard naming practices checked for by the dev
arm64: tegra: Add unit-address for CBB on Tegra194
The control back-bone (CBB) starts at physical address 0, so give it a unit-address to comply with standard naming practices checked for by the device tree compiler.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
d440538e |
| 25-Sep-2019 |
Jon Hunter <jonathanh@nvidia.com> |
arm64: tegra: Fix 'active-low' warning for Jetson Xavier regulator
Commit 4fdbfd60a3a2 ("arm64: tegra: Add PCIe slot supply information in p2972-0000 platform") added regulators for the PCIe slot on
arm64: tegra: Fix 'active-low' warning for Jetson Xavier regulator
Commit 4fdbfd60a3a2 ("arm64: tegra: Add PCIe slot supply information in p2972-0000 platform") added regulators for the PCIe slot on the Jetson Xavier platform. One of these regulators has an active-low enable and this commit incorrectly added an active-low specifier for the GPIO which causes the following warning to occur on boot ...
WARNING KERN regulator@3 GPIO handle specifies active low - ignored
The fixed-regulator binding does not use the active-low flag from the gpio specifier and purely relies of the presence of the 'enable-active-high' property to determine if it is active high or low (if this property is omitted). Fix this warning by setting the GPIO to active-high in the GPIO specifier. Finally, remove the 'enable-active-low' as this is not a valid property.
Fixes: 4fdbfd60a3a2 ("arm64: tegra: Add PCIe slot supply information in p2972-0000 platform") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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