a34ebb17 | 21-Feb-2023 |
Robert Marko <robert.marko@sartura.hr> |
arm64: dts: microchip: sparx5: correct CPU address-cells
There is no reason for CPU node #address-cells to be set at 2, so lets change them to 1 and update the reg property accordingly.
Signed-off-
arm64: dts: microchip: sparx5: correct CPU address-cells
There is no reason for CPU node #address-cells to be set at 2, so lets change them to 1 and update the reg property accordingly.
Signed-off-by: Robert Marko <robert.marko@sartura.hr> Link: https://lore.kernel.org/r/20230221105039.316819-2-robert.marko@sartura.hr Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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70be8370 | 21-Feb-2023 |
Robert Marko <robert.marko@sartura.hr> |
arm64: dts: microchip: sparx5: do not use PSCI on reference boards
PSCI is not implemented on SparX-5 at all, there is no ATF and U-boot that is shipped does not implement it as well.
I have tried
arm64: dts: microchip: sparx5: do not use PSCI on reference boards
PSCI is not implemented on SparX-5 at all, there is no ATF and U-boot that is shipped does not implement it as well.
I have tried flashing the latest BSP 2022.12 U-boot which did not work. After contacting Microchip, they confirmed that there is no ATF for the SoC nor PSCI implementation which is unfortunate in 2023.
So, disable PSCI as otherwise kernel crashes as soon as it tries probing PSCI with, and the crash is only visible if earlycon is used.
Since PSCI is not implemented, switch core bringup to use spin-tables which are implemented in the vendor U-boot and actually work.
Tested on PCB134 with eMMC (VSC5640EV).
Fixes: 6694aee00a4b ("arm64: dts: sparx5: Add basic cpu support") Signed-off-by: Robert Marko <robert.marko@sartura.hr> Acked-by: Steen Hegelund <Steen.Hegelund@microchip.com> Link: https://lore.kernel.org/r/20230221105039.316819-1-robert.marko@sartura.hr Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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08ee16e9 | 24-Aug-2020 |
Lars Povlsen <lars.povlsen@microchip.com> |
arm64: dts: sparx5: Add SPI controller and associated mmio-mux
This adds a SPI controller to the Microchip Sparx5 SoC, as well as the mmio-mux that is required to select the right SPI interface for
arm64: dts: sparx5: Add SPI controller and associated mmio-mux
This adds a SPI controller to the Microchip Sparx5 SoC, as well as the mmio-mux that is required to select the right SPI interface for a given SPI device.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200824203010.2033-4-lars.povlsen@microchip.com
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d14f6a1a | 28-Apr-2020 |
Lars Povlsen <lars.povlsen@microchip.com> |
arm64: dts: sparx5: Add hwmon temperature sensor
This adds a hwmon temperature node sensor to the Sparx5 SoC.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/
arm64: dts: sparx5: Add hwmon temperature sensor
This adds a hwmon temperature node sensor to the Sparx5 SoC.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200618135951.25441-3-lars.povlsen@microchip.com
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e4e06a50 | 15-Jun-2020 |
Lars Povlsen <lars.povlsen@microchip.com> |
arm64: dts: sparx5: Add Sparx5 SoC DPLL clock
This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock to misc peripherals, specifically the SDHCI/eMMC controller.
Link: https://lore.
arm64: dts: sparx5: Add Sparx5 SoC DPLL clock
This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock to misc peripherals, specifically the SDHCI/eMMC controller.
Link: https://lore.kernel.org/r/20200615133242.24911-10-lars.povlsen@microchip.com Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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