|
Revision tags: v6.6.36, v6.6.35, v6.6.34, v6.6.33, v6.6.32 |
|
| #
f4cff445 |
| 20-May-2024 |
Rafał Miłecki <rafal@milecki.pl> |
ARM: dts: aspeed: convert ASRock SPC621D8HM3 NVMEM content to layout syntax
Use cleaner (and non-deprecated) bindings syntax. See commit
bd912c991d2e ("dt-bindings: nvmem: layouts: add fixed-layout"
ARM: dts: aspeed: convert ASRock SPC621D8HM3 NVMEM content to layout syntax
Use cleaner (and non-deprecated) bindings syntax. See commit
bd912c991d2e ("dt-bindings: nvmem: layouts: add fixed-layout") for
details.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Acked-by: Zev Weiss <zev@bewilderbeest.net>
Link: https://lore.kernel.org/r/20240520063044.4885-1-zajec5@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
show more ...
|
|
Revision tags: v6.6.31, v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24, v6.6.23 |
|
| #
cdeefb40 |
| 12-Feb-2024 |
Zev Weiss <zev@bewilderbeest.net> |
ARM: dts: aspeed: asrock: Add BIOS SPI flash chips
On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
externa
ARM: dts: aspeed: asrock: Add BIOS SPI flash chips
On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
external GPIO-controlled mux switching the flash chip between the host
and the BMC.
The default state of the mux GPIO leaves it connected to the host, so
the BMC's attempt to bind a driver to it during its boot sequence will
fail, but a write to a sysfs 'bind' file after toggling the mux GPIO
(along with whatever other preparatory steps are required) can later
allow it to be attached and accessed by the BMC. It's not an ideal
arrangement, but in the absence of DT overlays or any other
alternative it is at least a functional one, if somewhat clumsily so.
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
show more ...
|
|
Revision tags: v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5 |
|
| #
db63e417 |
| 05-Dec-2023 |
Zev Weiss <zev@bewilderbeest.net> |
ARM: dts: aspeed: Add ASRock SPC621D8HM3 BMC
This is a Xeon board broadly similar (aside from CPU vendor) to the
already-support romed8hm3 (half-width, single-socket, ast2500). It
doesn't require a
ARM: dts: aspeed: Add ASRock SPC621D8HM3 BMC
This is a Xeon board broadly similar (aside from CPU vendor) to the
already-support romed8hm3 (half-width, single-socket, ast2500). It
doesn't require anything terribly special for OpenBMC support, so this
device-tree should provide everything necessary for basic
functionality with it.
OpenBMC-Staging-Count: 1
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Link: https://lore.kernel.org/r/20231114112819.28572-6-zev@bewilderbeest.net
Signed-off-by: Joel Stanley <joel@jms.id.au>
show more ...
|
|
Revision tags: v6.6.31, v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24, v6.6.23 |
|
| #
cdeefb40 |
| 12-Feb-2024 |
Zev Weiss <zev@bewilderbeest.net> |
ARM: dts: aspeed: asrock: Add BIOS SPI flash chips
On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
externa
ARM: dts: aspeed: asrock: Add BIOS SPI flash chips
On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
external GPIO-controlled mux switching the flash chip between the host
and the BMC.
The default state of the mux GPIO leaves it connected to the host, so
the BMC's attempt to bind a driver to it during its boot sequence will
fail, but a write to a sysfs 'bind' file after toggling the mux GPIO
(along with whatever other preparatory steps are required) can later
allow it to be attached and accessed by the BMC. It's not an ideal
arrangement, but in the absence of DT overlays or any other
alternative it is at least a functional one, if somewhat clumsily so.
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
show more ...
|
|
Revision tags: v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5 |
|
| #
db63e417 |
| 05-Dec-2023 |
Zev Weiss <zev@bewilderbeest.net> |
ARM: dts: aspeed: Add ASRock SPC621D8HM3 BMC
This is a Xeon board broadly similar (aside from CPU vendor) to the
already-support romed8hm3 (half-width, single-socket, ast2500). It
doesn't require a
ARM: dts: aspeed: Add ASRock SPC621D8HM3 BMC
This is a Xeon board broadly similar (aside from CPU vendor) to the
already-support romed8hm3 (half-width, single-socket, ast2500). It
doesn't require anything terribly special for OpenBMC support, so this
device-tree should provide everything necessary for basic
functionality with it.
OpenBMC-Staging-Count: 1
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Link: https://lore.kernel.org/r/20231114112819.28572-6-zev@bewilderbeest.net
Signed-off-by: Joel Stanley <joel@jms.id.au>
show more ...
|
|
Revision tags: v6.6.31, v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24, v6.6.23 |
|
| #
cdeefb40 |
| 12-Feb-2024 |
Zev Weiss <zev@bewilderbeest.net> |
ARM: dts: aspeed: asrock: Add BIOS SPI flash chips
On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
externa
ARM: dts: aspeed: asrock: Add BIOS SPI flash chips
On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
external GPIO-controlled mux switching the flash chip between the host
and the BMC.
The default state of the mux GPIO leaves it connected to the host, so
the BMC's attempt to bind a driver to it during its boot sequence will
fail, but a write to a sysfs 'bind' file after toggling the mux GPIO
(along with whatever other preparatory steps are required) can later
allow it to be attached and accessed by the BMC. It's not an ideal
arrangement, but in the absence of DT overlays or any other
alternative it is at least a functional one, if somewhat clumsily so.
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
show more ...
|
|
Revision tags: v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5 |
|
| #
db63e417 |
| 05-Dec-2023 |
Zev Weiss <zev@bewilderbeest.net> |
ARM: dts: aspeed: Add ASRock SPC621D8HM3 BMC
This is a Xeon board broadly similar (aside from CPU vendor) to the
already-support romed8hm3 (half-width, single-socket, ast2500). It
doesn't require a
ARM: dts: aspeed: Add ASRock SPC621D8HM3 BMC
This is a Xeon board broadly similar (aside from CPU vendor) to the
already-support romed8hm3 (half-width, single-socket, ast2500). It
doesn't require anything terribly special for OpenBMC support, so this
device-tree should provide everything necessary for basic
functionality with it.
OpenBMC-Staging-Count: 1
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Link: https://lore.kernel.org/r/20231114112819.28572-6-zev@bewilderbeest.net
Signed-off-by: Joel Stanley <joel@jms.id.au>
show more ...
|
|
Revision tags: v6.6.31, v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24, v6.6.23 |
|
| #
cdeefb40 |
| 12-Feb-2024 |
Zev Weiss <zev@bewilderbeest.net> |
ARM: dts: aspeed: asrock: Add BIOS SPI flash chips
On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
externa
ARM: dts: aspeed: asrock: Add BIOS SPI flash chips
On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
external GPIO-controlled mux switching the flash chip between the host
and the BMC.
The default state of the mux GPIO leaves it connected to the host, so
the BMC's attempt to bind a driver to it during its boot sequence will
fail, but a write to a sysfs 'bind' file after toggling the mux GPIO
(along with whatever other preparatory steps are required) can later
allow it to be attached and accessed by the BMC. It's not an ideal
arrangement, but in the absence of DT overlays or any other
alternative it is at least a functional one, if somewhat clumsily so.
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
show more ...
|
|
Revision tags: v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5 |
|
| #
db63e417 |
| 05-Dec-2023 |
Zev Weiss <zev@bewilderbeest.net> |
ARM: dts: aspeed: Add ASRock SPC621D8HM3 BMC
This is a Xeon board broadly similar (aside from CPU vendor) to the
already-support romed8hm3 (half-width, single-socket, ast2500). It
doesn't require a
ARM: dts: aspeed: Add ASRock SPC621D8HM3 BMC
This is a Xeon board broadly similar (aside from CPU vendor) to the
already-support romed8hm3 (half-width, single-socket, ast2500). It
doesn't require anything terribly special for OpenBMC support, so this
device-tree should provide everything necessary for basic
functionality with it.
OpenBMC-Staging-Count: 1
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Link: https://lore.kernel.org/r/20231114112819.28572-6-zev@bewilderbeest.net
Signed-off-by: Joel Stanley <joel@jms.id.au>
show more ...
|
|
Revision tags: v6.6.31, v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24, v6.6.23 |
|
| #
cdeefb40 |
| 12-Feb-2024 |
Zev Weiss <zev@bewilderbeest.net> |
ARM: dts: aspeed: asrock: Add BIOS SPI flash chips
On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
externa
ARM: dts: aspeed: asrock: Add BIOS SPI flash chips
On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
external GPIO-controlled mux switching the flash chip between the host
and the BMC.
The default state of the mux GPIO leaves it connected to the host, so
the BMC's attempt to bind a driver to it during its boot sequence will
fail, but a write to a sysfs 'bind' file after toggling the mux GPIO
(along with whatever other preparatory steps are required) can later
allow it to be attached and accessed by the BMC. It's not an ideal
arrangement, but in the absence of DT overlays or any other
alternative it is at least a functional one, if somewhat clumsily so.
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
show more ...
|
|
Revision tags: v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5 |
|
| #
db63e417 |
| 05-Dec-2023 |
Zev Weiss <zev@bewilderbeest.net> |
ARM: dts: aspeed: Add ASRock SPC621D8HM3 BMC
This is a Xeon board broadly similar (aside from CPU vendor) to the
already-support romed8hm3 (half-width, single-socket, ast2500). It
doesn't require a
ARM: dts: aspeed: Add ASRock SPC621D8HM3 BMC
This is a Xeon board broadly similar (aside from CPU vendor) to the
already-support romed8hm3 (half-width, single-socket, ast2500). It
doesn't require anything terribly special for OpenBMC support, so this
device-tree should provide everything necessary for basic
functionality with it.
OpenBMC-Staging-Count: 1
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Link: https://lore.kernel.org/r/20231114112819.28572-6-zev@bewilderbeest.net
Signed-off-by: Joel Stanley <joel@jms.id.au>
show more ...
|
|
Revision tags: v6.6.31, v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24, v6.6.23 |
|
| #
cdeefb40 |
| 12-Feb-2024 |
Zev Weiss <zev@bewilderbeest.net> |
ARM: dts: aspeed: asrock: Add BIOS SPI flash chips
On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
externa
ARM: dts: aspeed: asrock: Add BIOS SPI flash chips
On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
external GPIO-controlled mux switching the flash chip between the host
and the BMC.
The default state of the mux GPIO leaves it connected to the host, so
the BMC's attempt to bind a driver to it during its boot sequence will
fail, but a write to a sysfs 'bind' file after toggling the mux GPIO
(along with whatever other preparatory steps are required) can later
allow it to be attached and accessed by the BMC. It's not an ideal
arrangement, but in the absence of DT overlays or any other
alternative it is at least a functional one, if somewhat clumsily so.
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
show more ...
|
|
Revision tags: v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5 |
|
| #
db63e417 |
| 05-Dec-2023 |
Zev Weiss <zev@bewilderbeest.net> |
ARM: dts: aspeed: Add ASRock SPC621D8HM3 BMC
This is a Xeon board broadly similar (aside from CPU vendor) to the
already-support romed8hm3 (half-width, single-socket, ast2500). It
doesn't require a
ARM: dts: aspeed: Add ASRock SPC621D8HM3 BMC
This is a Xeon board broadly similar (aside from CPU vendor) to the
already-support romed8hm3 (half-width, single-socket, ast2500). It
doesn't require anything terribly special for OpenBMC support, so this
device-tree should provide everything necessary for basic
functionality with it.
OpenBMC-Staging-Count: 1
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Link: https://lore.kernel.org/r/20231114112819.28572-6-zev@bewilderbeest.net
Signed-off-by: Joel Stanley <joel@jms.id.au>
show more ...
|
|
Revision tags: v6.6.31, v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24, v6.6.23 |
|
| #
cdeefb40 |
| 12-Feb-2024 |
Zev Weiss <zev@bewilderbeest.net> |
ARM: dts: aspeed: asrock: Add BIOS SPI flash chips
On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
externa
ARM: dts: aspeed: asrock: Add BIOS SPI flash chips
On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
external GPIO-controlled mux switching the flash chip between the host
and the BMC.
The default state of the mux GPIO leaves it connected to the host, so
the BMC's attempt to bind a driver to it during its boot sequence will
fail, but a write to a sysfs 'bind' file after toggling the mux GPIO
(along with whatever other preparatory steps are required) can later
allow it to be attached and accessed by the BMC. It's not an ideal
arrangement, but in the absence of DT overlays or any other
alternative it is at least a functional one, if somewhat clumsily so.
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
show more ...
|
|
Revision tags: v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5 |
|
| #
db63e417 |
| 05-Dec-2023 |
Zev Weiss <zev@bewilderbeest.net> |
ARM: dts: aspeed: Add ASRock SPC621D8HM3 BMC
This is a Xeon board broadly similar (aside from CPU vendor) to the
already-support romed8hm3 (half-width, single-socket, ast2500). It
doesn't require a
ARM: dts: aspeed: Add ASRock SPC621D8HM3 BMC
This is a Xeon board broadly similar (aside from CPU vendor) to the
already-support romed8hm3 (half-width, single-socket, ast2500). It
doesn't require anything terribly special for OpenBMC support, so this
device-tree should provide everything necessary for basic
functionality with it.
OpenBMC-Staging-Count: 1
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Link: https://lore.kernel.org/r/20231114112819.28572-6-zev@bewilderbeest.net
Signed-off-by: Joel Stanley <joel@jms.id.au>
show more ...
|
|
Revision tags: v6.6.31, v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24, v6.6.23 |
|
| #
cdeefb40 |
| 12-Feb-2024 |
Zev Weiss <zev@bewilderbeest.net> |
ARM: dts: aspeed: asrock: Add BIOS SPI flash chips
On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
externa
ARM: dts: aspeed: asrock: Add BIOS SPI flash chips
On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
external GPIO-controlled mux switching the flash chip between the host
and the BMC.
The default state of the mux GPIO leaves it connected to the host, so
the BMC's attempt to bind a driver to it during its boot sequence will
fail, but a write to a sysfs 'bind' file after toggling the mux GPIO
(along with whatever other preparatory steps are required) can later
allow it to be attached and accessed by the BMC. It's not an ideal
arrangement, but in the absence of DT overlays or any other
alternative it is at least a functional one, if somewhat clumsily so.
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
show more ...
|
|
Revision tags: v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5 |
|
| #
db63e417 |
| 05-Dec-2023 |
Zev Weiss <zev@bewilderbeest.net> |
ARM: dts: aspeed: Add ASRock SPC621D8HM3 BMC
This is a Xeon board broadly similar (aside from CPU vendor) to the
already-support romed8hm3 (half-width, single-socket, ast2500). It
doesn't require a
ARM: dts: aspeed: Add ASRock SPC621D8HM3 BMC
This is a Xeon board broadly similar (aside from CPU vendor) to the
already-support romed8hm3 (half-width, single-socket, ast2500). It
doesn't require anything terribly special for OpenBMC support, so this
device-tree should provide everything necessary for basic
functionality with it.
OpenBMC-Staging-Count: 1
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Link: https://lore.kernel.org/r/20231114112819.28572-6-zev@bewilderbeest.net
Signed-off-by: Joel Stanley <joel@jms.id.au>
show more ...
|
|
Revision tags: v6.6.31, v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24, v6.6.23 |
|
| #
cdeefb40 |
| 12-Feb-2024 |
Zev Weiss <zev@bewilderbeest.net> |
ARM: dts: aspeed: asrock: Add BIOS SPI flash chips
On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
externa
ARM: dts: aspeed: asrock: Add BIOS SPI flash chips
On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
external GPIO-controlled mux switching the flash chip between the host
and the BMC.
The default state of the mux GPIO leaves it connected to the host, so
the BMC's attempt to bind a driver to it during its boot sequence will
fail, but a write to a sysfs 'bind' file after toggling the mux GPIO
(along with whatever other preparatory steps are required) can later
allow it to be attached and accessed by the BMC. It's not an ideal
arrangement, but in the absence of DT overlays or any other
alternative it is at least a functional one, if somewhat clumsily so.
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
show more ...
|
|
Revision tags: v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5 |
|
| #
db63e417 |
| 05-Dec-2023 |
Zev Weiss <zev@bewilderbeest.net> |
ARM: dts: aspeed: Add ASRock SPC621D8HM3 BMC
This is a Xeon board broadly similar (aside from CPU vendor) to the
already-support romed8hm3 (half-width, single-socket, ast2500). It
doesn't require a
ARM: dts: aspeed: Add ASRock SPC621D8HM3 BMC
This is a Xeon board broadly similar (aside from CPU vendor) to the
already-support romed8hm3 (half-width, single-socket, ast2500). It
doesn't require anything terribly special for OpenBMC support, so this
device-tree should provide everything necessary for basic
functionality with it.
OpenBMC-Staging-Count: 1
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Link: https://lore.kernel.org/r/20231114112819.28572-6-zev@bewilderbeest.net
Signed-off-by: Joel Stanley <joel@jms.id.au>
show more ...
|
|
Revision tags: v6.6.31, v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24, v6.6.23 |
|
| #
cdeefb40 |
| 12-Feb-2024 |
Zev Weiss <zev@bewilderbeest.net> |
ARM: dts: aspeed: asrock: Add BIOS SPI flash chips
On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
externa
ARM: dts: aspeed: asrock: Add BIOS SPI flash chips
On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
external GPIO-controlled mux switching the flash chip between the host
and the BMC.
The default state of the mux GPIO leaves it connected to the host, so
the BMC's attempt to bind a driver to it during its boot sequence will
fail, but a write to a sysfs 'bind' file after toggling the mux GPIO
(along with whatever other preparatory steps are required) can later
allow it to be attached and accessed by the BMC. It's not an ideal
arrangement, but in the absence of DT overlays or any other
alternative it is at least a functional one, if somewhat clumsily so.
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
show more ...
|
|
Revision tags: v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5 |
|
| #
db63e417 |
| 05-Dec-2023 |
Zev Weiss <zev@bewilderbeest.net> |
ARM: dts: aspeed: Add ASRock SPC621D8HM3 BMC
This is a Xeon board broadly similar (aside from CPU vendor) to the
already-support romed8hm3 (half-width, single-socket, ast2500). It
doesn't require a
ARM: dts: aspeed: Add ASRock SPC621D8HM3 BMC
This is a Xeon board broadly similar (aside from CPU vendor) to the
already-support romed8hm3 (half-width, single-socket, ast2500). It
doesn't require anything terribly special for OpenBMC support, so this
device-tree should provide everything necessary for basic
functionality with it.
OpenBMC-Staging-Count: 1
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Link: https://lore.kernel.org/r/20231114112819.28572-6-zev@bewilderbeest.net
Signed-off-by: Joel Stanley <joel@jms.id.au>
show more ...
|
|
Revision tags: v6.6.31, v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24, v6.6.23 |
|
| #
cdeefb40 |
| 12-Feb-2024 |
Zev Weiss <zev@bewilderbeest.net> |
ARM: dts: aspeed: asrock: Add BIOS SPI flash chips
On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
externa
ARM: dts: aspeed: asrock: Add BIOS SPI flash chips
On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
external GPIO-controlled mux switching the flash chip between the host
and the BMC.
The default state of the mux GPIO leaves it connected to the host, so
the BMC's attempt to bind a driver to it during its boot sequence will
fail, but a write to a sysfs 'bind' file after toggling the mux GPIO
(along with whatever other preparatory steps are required) can later
allow it to be attached and accessed by the BMC. It's not an ideal
arrangement, but in the absence of DT overlays or any other
alternative it is at least a functional one, if somewhat clumsily so.
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
show more ...
|
|
Revision tags: v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5 |
|
| #
db63e417 |
| 05-Dec-2023 |
Zev Weiss <zev@bewilderbeest.net> |
ARM: dts: aspeed: Add ASRock SPC621D8HM3 BMC
This is a Xeon board broadly similar (aside from CPU vendor) to the
already-support romed8hm3 (half-width, single-socket, ast2500). It
doesn't require a
ARM: dts: aspeed: Add ASRock SPC621D8HM3 BMC
This is a Xeon board broadly similar (aside from CPU vendor) to the
already-support romed8hm3 (half-width, single-socket, ast2500). It
doesn't require anything terribly special for OpenBMC support, so this
device-tree should provide everything necessary for basic
functionality with it.
OpenBMC-Staging-Count: 1
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Link: https://lore.kernel.org/r/20231114112819.28572-6-zev@bewilderbeest.net
Signed-off-by: Joel Stanley <joel@jms.id.au>
show more ...
|
|
Revision tags: v6.6.31, v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24, v6.6.23 |
|
| #
cdeefb40 |
| 12-Feb-2024 |
Zev Weiss <zev@bewilderbeest.net> |
ARM: dts: aspeed: asrock: Add BIOS SPI flash chips
On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
externa
ARM: dts: aspeed: asrock: Add BIOS SPI flash chips
On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
external GPIO-controlled mux switching the flash chip between the host
and the BMC.
The default state of the mux GPIO leaves it connected to the host, so
the BMC's attempt to bind a driver to it during its boot sequence will
fail, but a write to a sysfs 'bind' file after toggling the mux GPIO
(along with whatever other preparatory steps are required) can later
allow it to be attached and accessed by the BMC. It's not an ideal
arrangement, but in the absence of DT overlays or any other
alternative it is at least a functional one, if somewhat clumsily so.
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
show more ...
|
|
Revision tags: v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5 |
|
| #
db63e417 |
| 05-Dec-2023 |
Zev Weiss <zev@bewilderbeest.net> |
ARM: dts: aspeed: Add ASRock SPC621D8HM3 BMC
This is a Xeon board broadly similar (aside from CPU vendor) to the
already-support romed8hm3 (half-width, single-socket, ast2500). It
doesn't require a
ARM: dts: aspeed: Add ASRock SPC621D8HM3 BMC
This is a Xeon board broadly similar (aside from CPU vendor) to the
already-support romed8hm3 (half-width, single-socket, ast2500). It
doesn't require anything terribly special for OpenBMC support, so this
device-tree should provide everything necessary for basic
functionality with it.
OpenBMC-Staging-Count: 1
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Link: https://lore.kernel.org/r/20231114112819.28572-6-zev@bewilderbeest.net
Signed-off-by: Joel Stanley <joel@jms.id.au>
show more ...
|