ARC: [plat-hsdk] use actual clk driver to manage cpu clk

With corresponding clk driver now merged upstream, switch to it.

- core_clk now represent the PLL (vs. fixed clk before)

ARC: [plat-hsdk] use actual clk driver to manage cpu clk

With corresponding clk driver now merged upstream, switch to it.

- core_clk now represent the PLL (vs. fixed clk before)
- input_clk represent the clk signal src for PLL (basically xtal)

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

show more ...

ARC: [plat-hsdk] sdio: Temporary fix of sdio ciu frequency

DW sdio controller has external ciu clock divider controlled via
register in SDIO IP. Due to its unexpected default value
(

ARC: [plat-hsdk] sdio: Temporary fix of sdio ciu frequency

DW sdio controller has external ciu clock divider controlled via
register in SDIO IP. Due to its unexpected default value
(it should divide by 1 but it divides by 8)
SDIO IP uses wrong ciu clock and works unstable

So add temporary fix and change clock frequency from 100000000
to 12500000 Hz until we fix dw sdio driver itself.

Fixes SNPS STAR 9001204800

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

show more ...

ARC: [plat-hsdk] initial port for HSDK board

This initial port adds support of ARC HS Development Kit board with some
basic features such serial port, USB, SD/MMC and Ethernet.

ARC: [plat-hsdk] initial port for HSDK board

This initial port adds support of ARC HS Development Kit board with some
basic features such serial port, USB, SD/MMC and Ethernet.

Essentially we run Linux kernel on all 4 cores (i.e. utilize SMP) and
heavily use IO Coherency for speeding-up DMA-aware peripherals.

Note as opposed to other ARC boards we link Linux kernel to
0x9000_0000 intentionally because cores 1 and 3 configured with DCCM
situated at our more usual link base 0x8000_0000. We still can use
memory region starting at 0x8000_0000 as we reallocate DCCM in our
platform code.

Note that PAE remapping for DMA clients does not work due to an RTL bug,
so CREG_PAE register must be programmed to all zeroes, otherwise it will
cause problems with DMA to/from peripherals even if PAE40 is not used.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

show more ...