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Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9 |
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33fd5fb1 |
| 22-Dec-2023 |
David E. Box <david.e.box@linux.intel.com> |
platform/x86/intel/pmc: Move GBE LTR ignore to suspend callback
[ Upstream commit 70681aa0746ae61d7668b9f651221fad5e30c71e ]
Commit 804951203aa5 ("platform/x86:intel/pmc: Combine core_init() and
co
platform/x86/intel/pmc: Move GBE LTR ignore to suspend callback
[ Upstream commit 70681aa0746ae61d7668b9f651221fad5e30c71e ]
Commit 804951203aa5 ("platform/x86:intel/pmc: Combine core_init() and
core_configure()") caused a network performance regression due to the GBE
LTR ignore that it added at probe. This was needed in order to allow the
SoC to enter the deepest Package C state. To fix the regression and at
least support PC10 during suspend, move the LTR ignore from probe to the
suspend callback, and enable it again on resume. This solution will allow
PC10 during suspend but restrict Package C entry at runtime to no deeper
than PC8/9 while a network cable it attach to the PCH LAN.
Fixes: 804951203aa5 ("platform/x86:intel/pmc: Combine core_init() and core_configure()")
Signed-off-by: "David E. Box" <david.e.box@linux.intel.com>
Link: https://lore.kernel.org/r/20231223032548.1680738-6-david.e.box@linux.intel.com
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
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91dcd5ee |
| 22-Dec-2023 |
David E. Box <david.e.box@linux.intel.com> |
platform/x86/intel/pmc: Allow reenabling LTRs
[ Upstream commit 6f9cc5c1f94daa98846b2073733d03ced709704b ]
Commit 804951203aa5 ("platform/x86:intel/pmc: Combine core_init() and
core_configure()") c
platform/x86/intel/pmc: Allow reenabling LTRs
[ Upstream commit 6f9cc5c1f94daa98846b2073733d03ced709704b ]
Commit 804951203aa5 ("platform/x86:intel/pmc: Combine core_init() and
core_configure()") caused a network performance regression due to the GBE
LTR ignore that it added during probe. The fix will move the ignore to
occur at suspend-time (so as to not affect suspend power). This will
require the ability to enable the LTR again on resume. Modify
pmc_core_send_ltr_ignore() to allow enabling an LTR.
Fixes: 804951203aa5 ("platform/x86:intel/pmc: Combine core_init() and core_configure()")
Signed-off-by: "David E. Box" <david.e.box@linux.intel.com>
Link: https://lore.kernel.org/r/20231223032548.1680738-5-david.e.box@linux.intel.com
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
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Revision tags: v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34 |
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1c709ae1 |
| 13-Jun-2023 |
Xi Pardee <xi.pardee@intel.com> |
platform/x86:intel/pmc: Add support to handle multiple PMCs
To support platforms with multiple PMCs, add a PMC device structure to
support each PMC instance.
Signed-off-by: Xi Pardee <xi.pardee@int
platform/x86:intel/pmc: Add support to handle multiple PMCs
To support platforms with multiple PMCs, add a PMC device structure to
support each PMC instance.
Signed-off-by: Xi Pardee <xi.pardee@intel.com>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Link: https://lore.kernel.org/r/20230613225347.2720665-4-rajvi.jingar@linux.intel.com
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
show more ...
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| #
80495120 |
| 13-Jun-2023 |
Xi Pardee <xi.pardee@intel.com> |
platform/x86:intel/pmc: Combine core_init() and core_configure()
Combine core_init() and core_configure() functions to have a
cleaner setup for platforms.
Signed-off-by: Xi Pardee <xi.pardee@intel.
platform/x86:intel/pmc: Combine core_init() and core_configure()
Combine core_init() and core_configure() functions to have a
cleaner setup for platforms.
Signed-off-by: Xi Pardee <xi.pardee@intel.com>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Link: https://lore.kernel.org/r/20230613225347.2720665-3-rajvi.jingar@linux.intel.com
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
show more ...
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Revision tags: v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79 |
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d6cd0cc8 |
| 14-Nov-2022 |
Xi Pardee <xi.pardee@intel.com> |
platform/x86: intel/pmc: Relocate Cannon Lake Point PCH support
Create cnp.c for Cannon Lake Point PCH specific structures and init().
This file supports Cannon Lake and Comet Lake platforms.
There
platform/x86: intel/pmc: Relocate Cannon Lake Point PCH support
Create cnp.c for Cannon Lake Point PCH specific structures and init().
This file supports Cannon Lake and Comet Lake platforms.
There are no functional changes involved.
Cc: David E Box <david.e.box@linux.intel.com>
Reviewed-by: "David E. Box" <david.e.box@linux.intel.com>
Signed-off-by: Xi Pardee <xi.pardee@intel.com>
Signed-off-by: "David E. Box" <david.e.box@linux.intel.com>
Link: https://lore.kernel.org/r/20221114183257.2067662-5-gayatri.kammela@linux.intel.com
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
show more ...
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