phy: lantiq: convert to devm_platform_ioremap_resource

Use devm_platform_ioremap_resource to simplify code

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lore.kernel.org/r/16

phy: lantiq: convert to devm_platform_ioremap_resource

Use devm_platform_ioremap_resource to simplify code

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lore.kernel.org/r/1604642930-29019-6-git-send-email-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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phy: lantiq: vrx200-pcie: Constify ltq_vrx200_pcie_phy_ops

The only usage is to pass its address to devm_phy_create() which takes a
const pointer. Make it const to allow the compiler to put it in
re

phy: lantiq: vrx200-pcie: Constify ltq_vrx200_pcie_phy_ops

The only usage is to pass its address to devm_phy_create() which takes a
const pointer. Make it const to allow the compiler to put it in
read-only memory.

Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20200823220025.17588-6-rikard.falkeborn@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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phy: lantiq: vrx200-pcie: Remove unneeded semicolon

Fixes coccicheck warning:

drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c:389:2-3: Unneeded semicolon

Fixes: e52a632195bf ("phy: lantiq: vrx200-pcie

phy: lantiq: vrx200-pcie: Remove unneeded semicolon

Fixes coccicheck warning:

drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c:389:2-3: Unneeded semicolon

Fixes: e52a632195bf ("phy: lantiq: vrx200-pcie: add a driver for the Lantiq VRX200 PCIe PHY")

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Ma Feng <mafeng.ma@huawei.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

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phy: lantiq: vrx200-pcie: fix error return code in ltq_vrx200_pcie_phy_power_on()

Fix to return a negative error code from the error handling
case instead of 0, as done elsewhere in this function.

phy: lantiq: vrx200-pcie: fix error return code in ltq_vrx200_pcie_phy_power_on()

Fix to return a negative error code from the error handling
case instead of 0, as done elsewhere in this function.

Fixes: e52a632195bf ("phy: lantiq: vrx200-pcie: add a driver for the Lantiq VRX200 PCIe PHY")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

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phy: lantiq: vrx200-pcie: add a driver for the Lantiq VRX200 PCIe PHY

The Lantiq VRX200 SoCs embed a PCIe PHY in the "sram" bus. Unlike most
other IP blocks on this SoC the register values are only

phy: lantiq: vrx200-pcie: add a driver for the Lantiq VRX200 PCIe PHY

The Lantiq VRX200 SoCs embed a PCIe PHY in the "sram" bus. Unlike most
other IP blocks on this SoC the register values are only 16-bit wide.
Like other IP blocks on this SoC the register values are in big endian.

The PHY embeds a PLL which can be configured in various modes. Only the
36MHz mode is supported for now, the other modes can be implemented when
there's a board which actually needs them. OpenWrt uses the out-of-tree
vendor driver and all supported boards there only need the 36MHz mode.

There are two input clocks:
- the "pdi" clock enables the register access
- the "phy" clock is the clock input and enables the internal PLL

There are two reset lines:
- "phy" resets the PHY itself
- the "pcie" reset line is shared between the PHY and the PCIe
controller

While the VRX200 SoC has only one PCIe controller and PHY the ARX300
uses two identical PCIe controllers and PHYs which are compatible with
the PCIe controller and PHY on VRX200.
Add a driver for this PHY so PCIe support can be enabled on these SoCs.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

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phy: lantiq: vrx200-pcie: Constify ltq_vrx200_pcie_phy_ops

The only usage is to pass its address to devm_phy_create() which takes a
const pointer. Make it const to allow the compiler to

phy: lantiq: vrx200-pcie: Constify ltq_vrx200_pcie_phy_ops

The only usage is to pass its address to devm_phy_create() which takes a
const pointer. Make it const to allow the compiler to put it in
read-only memory.

Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20200823220025.17588-6-rikard.falkeborn@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

show more ...

phy: lantiq: vrx200-pcie: Remove unneeded semicolon

Fixes coccicheck warning:

drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c:389:2-3: Unneeded semicolon

Fixes: e52a632195bf ("

phy: lantiq: vrx200-pcie: Remove unneeded semicolon

Fixes coccicheck warning:

drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c:389:2-3: Unneeded semicolon

Fixes: e52a632195bf ("phy: lantiq: vrx200-pcie: add a driver for the Lantiq VRX200 PCIe PHY")

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Ma Feng <mafeng.ma@huawei.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

show more ...

phy: lantiq: vrx200-pcie: fix error return code in ltq_vrx200_pcie_phy_power_on()

Fix to return a negative error code from the error handling
case instead of 0, as done elsewhere in this

phy: lantiq: vrx200-pcie: fix error return code in ltq_vrx200_pcie_phy_power_on()

Fix to return a negative error code from the error handling
case instead of 0, as done elsewhere in this function.

Fixes: e52a632195bf ("phy: lantiq: vrx200-pcie: add a driver for the Lantiq VRX200 PCIe PHY")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

show more ...

phy: lantiq: vrx200-pcie: add a driver for the Lantiq VRX200 PCIe PHY

The Lantiq VRX200 SoCs embed a PCIe PHY in the "sram" bus. Unlike most
other IP blocks on this SoC the register valu

phy: lantiq: vrx200-pcie: add a driver for the Lantiq VRX200 PCIe PHY

The Lantiq VRX200 SoCs embed a PCIe PHY in the "sram" bus. Unlike most
other IP blocks on this SoC the register values are only 16-bit wide.
Like other IP blocks on this SoC the register values are in big endian.

The PHY embeds a PLL which can be configured in various modes. Only the
36MHz mode is supported for now, the other modes can be implemented when
there's a board which actually needs them. OpenWrt uses the out-of-tree
vendor driver and all supported boards there only need the 36MHz mode.

There are two input clocks:
- the "pdi" clock enables the register access
- the "phy" clock is the clock input and enables the internal PLL

There are two reset lines:
- "phy" resets the PHY itself
- the "pcie" reset line is shared between the PHY and the PCIe
controller

While the VRX200 SoC has only one PCIe controller and PHY the ARX300
uses two identical PCIe controllers and PHYs which are compatible with
the PCIe controller and PHY on VRX200.
Add a driver for this PHY so PCIe support can be enabled on these SoCs.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

show more ...