| e466b899 | 04-Nov-2024 |
Siddharth Vadapalli <s-vadapalli@ti.com> |
PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS milliseconds
[ Upstream commit 22a9120479a40a56c13c5e473a0100fad2e017c0 ]
According to Section 2.2 of the PCI Express Card Electromecha
PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS milliseconds
[ Upstream commit 22a9120479a40a56c13c5e473a0100fad2e017c0 ]
According to Section 2.2 of the PCI Express Card Electromechanical
Specification (Revision 5.1), in order to ensure that the power and the
reference clock are stable, PERST# has to be deasserted after a delay of
100 milliseconds (TPVPERL).
Currently, it is being assumed that the power is already stable, which
is not necessarily true.
Hence, change the delay to PCIE_T_PVPERL_MS to guarantee that power and
reference clock are stable.
Fixes: f3e25911a430 ("PCI: j721e: Add TI J721E PCIe driver")
Fixes: f96b69713733 ("PCI: j721e: Use T_PERST_CLK_US macro")
Link: https://lore.kernel.org/r/20241104074420.1862932-1-s-vadapalli@ti.com
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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| 9621a3d5 | 19-Jun-2024 |
Théo Lebrun <theo.lebrun@bootlin.com> |
PCI: j721e: Add suspend and resume support
[ Upstream commit c538d40f365b5b6d7433d371710f58e8b266fb19 ]
Add suspend and resume support. Only the Root Complex mode is supported.
During the suspend
PCI: j721e: Add suspend and resume support
[ Upstream commit c538d40f365b5b6d7433d371710f58e8b266fb19 ]
Add suspend and resume support. Only the Root Complex mode is supported.
During the suspend stage PERST# is asserted, then deasserted during the
resume stage.
Link: https://lore.kernel.org/linux-pci/20240102-j7200-pcie-s2r-v7-7-a2f9156da6c3@bootlin.com
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
[kwilczynski: commit log, update references to the PCI SIG specification]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Stable-dep-of: 22a9120479a4 ("PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS milliseconds")
Signed-off-by: Sasha Levin <sashal@kernel.org>
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| bea0c0e4 | 19-Jun-2024 |
Thomas Richard <thomas.richard@bootlin.com> |
PCI: j721e: Use T_PERST_CLK_US macro
[ Upstream commit f96b6971373382855bc964f1c067bd6dc41cf0ab ]
Use the T_PERST_CLK_US macro, and the fsleep() function instead of
usleep_range().
Link: https://l
PCI: j721e: Use T_PERST_CLK_US macro
[ Upstream commit f96b6971373382855bc964f1c067bd6dc41cf0ab ]
Use the T_PERST_CLK_US macro, and the fsleep() function instead of
usleep_range().
Link: https://lore.kernel.org/linux-pci/20240102-j7200-pcie-s2r-v7-6-a2f9156da6c3@bootlin.com
Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Stable-dep-of: 22a9120479a4 ("PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS milliseconds")
Signed-off-by: Sasha Levin <sashal@kernel.org>
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| 0a289ca9 | 19-Jun-2024 |
Théo Lebrun <theo.lebrun@bootlin.com> |
PCI: j721e: Add reset GPIO to struct j721e_pcie
[ Upstream commit b8600b8791cb2b7c8be894846b1ecddba7291680 ]
Add reset GPIO to struct j721e_pcie, so it can be used at suspend and
resume stages.
Li
PCI: j721e: Add reset GPIO to struct j721e_pcie
[ Upstream commit b8600b8791cb2b7c8be894846b1ecddba7291680 ]
Add reset GPIO to struct j721e_pcie, so it can be used at suspend and
resume stages.
Link: https://lore.kernel.org/linux-pci/20240102-j7200-pcie-s2r-v7-4-a2f9156da6c3@bootlin.com
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Stable-dep-of: 22a9120479a4 ("PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS milliseconds")
Signed-off-by: Sasha Levin <sashal@kernel.org>
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| 762de299 | 19-Jun-2024 |
Thomas Richard <thomas.richard@bootlin.com> |
PCI: cadence: Set cdns_pcie_host_init() global
[ Upstream commit 063c938928dc80c2bfd66f34df48344db22e009b ]
During the resume sequence of the host, cdns_pcie_host_init() needs to be
called, so set
PCI: cadence: Set cdns_pcie_host_init() global
[ Upstream commit 063c938928dc80c2bfd66f34df48344db22e009b ]
During the resume sequence of the host, cdns_pcie_host_init() needs to be
called, so set it global.
The dev function parameter is removed, as it isn't used.
Link: https://lore.kernel.org/linux-pci/20240102-j7200-pcie-s2r-v7-2-a2f9156da6c3@bootlin.com
Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Stable-dep-of: 22a9120479a4 ("PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS milliseconds")
Signed-off-by: Sasha Levin <sashal@kernel.org>
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| 4231df76 | 19-Jun-2024 |
Thomas Richard <thomas.richard@bootlin.com> |
PCI: cadence: Extract link setup sequence from cdns_pcie_host_setup()
[ Upstream commit d1b6f2e2ce4d8b17d9f3558c98a1517b864bfd03 ]
The function cdns_pcie_host_setup() mixes probe structure and link
PCI: cadence: Extract link setup sequence from cdns_pcie_host_setup()
[ Upstream commit d1b6f2e2ce4d8b17d9f3558c98a1517b864bfd03 ]
The function cdns_pcie_host_setup() mixes probe structure and link setup.
The link setup must be done during the resume sequence. So extract it from
cdns_pcie_host_setup() and create a dedicated function.
Link: https://lore.kernel.org/linux-pci/20240102-j7200-pcie-s2r-v7-1-a2f9156da6c3@bootlin.com
Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Stable-dep-of: 22a9120479a4 ("PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS milliseconds")
Signed-off-by: Sasha Levin <sashal@kernel.org>
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| 5261d258 | 27-Nov-2023 |
Matt Ranostay <mranostay@ti.com> |
PCI: j721e: Add PCIe 4x lane selection support
[ Upstream commit 4490f559f75514d5a6f0e729e85235a7be6216bf ]
Add support for setting of two-bit field that allows selection of 4x lane
PCIe which was
PCI: j721e: Add PCIe 4x lane selection support
[ Upstream commit 4490f559f75514d5a6f0e729e85235a7be6216bf ]
Add support for setting of two-bit field that allows selection of 4x lane
PCIe which was previously limited to only 2x lanes.
Link: https://lore.kernel.org/linux-pci/20231128054402.2155183-5-s-vadapalli@ti.com
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Achal Verma <a-verma1@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Stable-dep-of: 22a9120479a4 ("PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS milliseconds")
Signed-off-by: Sasha Levin <sashal@kernel.org>
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| 95b00f68 | 25-Oct-2021 |
Parshuram Thombare <pthombar@cadence.com> |
PCI: cadence: Clear FLR in device capabilities register
Clear FLR (Function Level Reset) from device capabilities
registers for all physical functions.
During FLR, the Margining Lane Status and Mar
PCI: cadence: Clear FLR in device capabilities register
Clear FLR (Function Level Reset) from device capabilities
registers for all physical functions.
During FLR, the Margining Lane Status and Margining Lane Control
registers should not be reset, as per PCIe specification.
However, the controller incorrectly resets these registers upon FLR.
This causes PCISIG compliance FLR test to fail. Hence preventing
all functions from advertising FLR support if flag quirk_disable_flr
is set.
Link: https://lore.kernel.org/r/1635165075-89864-1-git-send-email-pthombar@cadence.com
Signed-off-by: Parshuram Thombare <pthombar@cadence.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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| a1f67bc1 | 12-May-2022 |
Christian Gmeiner <christian.gmeiner@gmail.com> |
PCI: cadence: Allow PTM Responder to be enabled
This enables the Controller [RP] to automatically respond with
Response/ResponseD messages if CDNS_PCIE_LM_TPM_CTRL_PTMRSEN
and PCI_PTM_CTRL_ENABLE bi
PCI: cadence: Allow PTM Responder to be enabled
This enables the Controller [RP] to automatically respond with
Response/ResponseD messages if CDNS_PCIE_LM_TPM_CTRL_PTMRSEN
and PCI_PTM_CTRL_ENABLE bits are both set.
Link: https://lore.kernel.org/r/20220512055539.1782437-1-christian.gmeiner@gmail.com
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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| 87c71931 | 13-Jan-2022 |
Bjorn Helgaas <bhelgaas@google.com> |
Merge branch 'pci/driver-cleanup'
- Use of_device_get_match_data(), not of_match_device(), when we only need
the device data in altera, artpec6, cadence, designware-plat, dra7xx,
keystone, kirin
Merge branch 'pci/driver-cleanup'
- Use of_device_get_match_data(), not of_match_device(), when we only need
the device data in altera, artpec6, cadence, designware-plat, dra7xx,
keystone, kirin (Fan Fei)
- Drop pointless of_device_get_match_data() cast in j721e (Bjorn Helgaas)
- Drop redundant struct device * from j721e since struct cdns_pcie already
has one (Bjorn Helgaas)
- Rename driver structs to *_pcie in intel-gw, iproc, ls-gen4,
mediatek-gen3, microchip, mt7621, rcar-gen2, tegra194, uniphier, xgene,
xilinx, xilinx-cpm for consistency across drivers (Fan Fei)
- Fix invalid address space conversions in hisi, spear13xx (Bjorn Helgaas)
* pci/driver-cleanup:
PCI: spear13xx: Avoid invalid address space conversions
PCI: hisi: Avoid invalid address space conversions
PCI: xilinx-cpm: Rename xilinx_cpm_pcie_port to xilinx_cpm_pcie
PCI: xilinx: Rename xilinx_pcie_port to xilinx_pcie
PCI: xgene: Rename xgene_pcie_port to xgene_pcie
PCI: uniphier: Rename uniphier_pcie_priv to uniphier_pcie
PCI: tegra194: Rename tegra_pcie_dw to tegra194_pcie
PCI: rcar-gen2: Rename rcar_pci_priv to rcar_pci
PCI: mt7621: Rename mt7621_pci_ to mt7621_pcie_
PCI: microchip: Rename mc_port to mc_pcie
PCI: mediatek-gen3: Rename mtk_pcie_port to mtk_gen3_pcie
PCI: ls-gen4: Rename ls_pcie_g4 to ls_g4_pcie
PCI: iproc: Rename iproc_pcie_pltfm_ to iproc_pltfm_pcie_
PCI: iproc: Rename iproc_pcie_bcma_ to iproc_bcma_pcie_
PCI: intel-gw: Rename intel_pcie_port to intel_pcie
PCI: j721e: Drop redundant struct device *
PCI: j721e: Drop pointless of_device_get_match_data() cast
PCI: kirin: Prefer of_device_get_match_data()
PCI: keystone: Prefer of_device_get_match_data()
PCI: dra7xx: Prefer of_device_get_match_data()
PCI: designware-plat: Prefer of_device_get_match_data()
PCI: cadence: Prefer of_device_get_match_data()
PCI: artpec6: Prefer of_device_get_match_data()
PCI: altera: Prefer of_device_get_match_data()
# Conflicts:
# drivers/pci/controller/pcie-mt7621.c
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| 19e86382 | 22-Dec-2021 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: j721e: Drop redundant struct device *
The struct cdns_pcie already contains the struct device for the j721e PCIe
controller. There's no need to store another copy in struct j721e_pcie.
Remove
PCI: j721e: Drop redundant struct device *
The struct cdns_pcie already contains the struct device for the j721e PCIe
controller. There's no need to store another copy in struct j721e_pcie.
Remove the redundant copy from struct j721e_pcie.
Link: https://lore.kernel.org/r/20211223011054.1227810-10-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Tom Joseph <tjoseph@cadence.com>
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| 72de208f | 22-Dec-2021 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: j721e: Drop pointless of_device_get_match_data() cast
of_device_get_match_data() returns "void *", so no cast is needed when
assigning the result to a pointer type. Drop the unnecessary cast.
PCI: j721e: Drop pointless of_device_get_match_data() cast
of_device_get_match_data() returns "void *", so no cast is needed when
assigning the result to a pointer type. Drop the unnecessary cast.
Link: https://lore.kernel.org/r/20211223011054.1227810-9-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Tom Joseph <tjoseph@cadence.com>
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