Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64 |
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#
2533e726 |
| 29-Aug-2022 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Split chunk allocation to HW-dependent ways
This way we are able to allocate chunk for modify_headers from 2 types: STEv0 that is allocated from the action area, and STEv1 that is allo
net/mlx5: DR, Split chunk allocation to HW-dependent ways
This way we are able to allocate chunk for modify_headers from 2 types: STEv0 that is allocated from the action area, and STEv1 that is allocating the chunks from the special area for patterns.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
1207a772 |
| 29-Nov-2022 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Add function that tells if STE miss addr has been initialized
Up until now miss address in all the STEs was used to connect miss lists and to link the last STE in the list to end ancho
net/mlx5: DR, Add function that tells if STE miss addr has been initialized
Up until now miss address in all the STEs was used to connect miss lists and to link the last STE in the list to end anchor. Match range STE will require special handling because its miss address is part of the 'action'. That is, range action has hit and miss addresses. Since the range action is always the last action, need to make sure that its miss address isn't overwritten by the end anchor.
Adding new function mlx5dr_ste_is_miss_addr_set() to answer the question whether the STE's miss address has already been set as part of STE initialization. Use a callback that always returns false right now. Once match range is added, a different callback will be used for that STE type.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Erez Shitrit <erezsh@nvidia.com> Reviewed-by: Mark Bloch <mbloch@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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Revision tags: v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26 |
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#
6862c787 |
| 23-Feb-2022 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Add support for ConnectX-7 steering
Add support for a new SW format version that is implemented by ConnectX-7.
Except for several differences, the STEv2 is identical to STEv1, so for
net/mlx5: DR, Add support for ConnectX-7 steering
Add support for a new SW format version that is implemented by ConnectX-7.
Except for several differences, the STEv2 is identical to STEv1, so for most callbacks the STEv2 context struct will call STEv1 functions.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
638a07f1 |
| 23-Feb-2022 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Refactor ste_ctx handling for STE v0/1
As preparation for supporting ConnectX-7, this patches changes handling of ste_ctx handling for existing STE v0 and V1: - each context is now a
net/mlx5: DR, Refactor ste_ctx handling for STE v0/1
As preparation for supporting ConnectX-7, this patches changes handling of ste_ctx handling for existing STE v0 and V1: - each context is now a static struct, and it has a corresponding getter - v0 and v1 were extended to contain the fields that are required for integrating STEv2.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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Revision tags: v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2 |
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#
f59464e2 |
| 07-Nov-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Add support for matching on geneve_tlv_option_0_exist field
Match on geneve_tlv_option_0_exist field on devices that support STEv1.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.co
net/mlx5: DR, Add support for matching on geneve_tlv_option_0_exist field
Match on geneve_tlv_option_0_exist field on devices that support STEv1.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
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Revision tags: v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63 |
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#
09753bab |
| 05-Sep-2021 |
Muhammad Sammar <muhammads@nvidia.com> |
net/mlx5: DR, Support matching on tunnel headers 0 and 1
Tunnel headers are generic encapsulation headers, applies for all tunneling protocols identified by the device native parser or by the progra
net/mlx5: DR, Support matching on tunnel headers 0 and 1
Tunnel headers are generic encapsulation headers, applies for all tunneling protocols identified by the device native parser or by the programmable parser, this support will enable raw matching headers 0 and 1.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
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Revision tags: v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49 |
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#
46f2a8ae |
| 04-Jul-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Remove HW specific STE type from nic domain
Instead of using the HW specific STEv0 type, it is better to use an enum to indicate if this is an RX or TX nic domain. This means that now
net/mlx5: DR, Remove HW specific STE type from nic domain
Instead of using the HW specific STEv0 type, it is better to use an enum to indicate if this is an RX or TX nic domain. This means that now we will need to convert the nic domain type to the corresponding STE type.
Signed-off-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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Revision tags: v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23 |
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#
d7418b4e |
| 09-Mar-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Allow encap action for RX for supporting devices
Encap actions on RX flow were not supported on older devices. However, this is no longer the case in devices that support STEv1. This p
net/mlx5: DR, Allow encap action for RX for supporting devices
Encap actions on RX flow were not supported on older devices. However, this is no longer the case in devices that support STEv1. This patch adds support for encap l3/l2 on RX flow for supported devices: update actions state machine by adding the newely supported transitions and add the required support in STEv0/1 files. The new transitions that are supported are: - from decap/modify-header/pop-vlan to encap - from encap to termination table
Signed-off-by: Erez Shitrit <erezsh@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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Revision tags: v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14 |
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#
df9dd15a |
| 06-Feb-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Add support for matching tunnel GTP-U
Enable matching on tunnel GTP-U and GTP-U first extension header using dynamic flex parser.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com>
net/mlx5: DR, Add support for matching tunnel GTP-U
Enable matching on tunnel GTP-U and GTP-U first extension header using dynamic flex parser.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
35ba005d |
| 06-Feb-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Set flex parser for TNL_MPLS dynamically
Query the flex_parser id that's intended for TNL_MPLS and use an appropriate flex parser for MPLS over UDP/GRE.
Signed-off-by: Muhammad Sammar
net/mlx5: DR, Set flex parser for TNL_MPLS dynamically
Query the flex_parser id that's intended for TNL_MPLS and use an appropriate flex parser for MPLS over UDP/GRE.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
3442e033 |
| 06-Feb-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Add support for matching on geneve TLV option
Enable matching on tunnel geneve TLV option using the flex parser.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Y
net/mlx5: DR, Add support for matching on geneve TLV option
Enable matching on tunnel geneve TLV option using the flex parser.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
4923938d |
| 06-Feb-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Set STEv0 ICMP flex parser dynamically
Set the flex parser ID dynamicly for ICMP instead of relying on hardcoded values.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-o
net/mlx5: DR, Set STEv0 ICMP flex parser dynamically
Set the flex parser ID dynamicly for ICMP instead of relying on hardcoded values.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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Revision tags: v5.10 |
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#
160e9cb3 |
| 24-Nov-2020 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Add support for dynamic flex parser
Flex parser is a HW parser that can support protocols that are not natively supported by the HCA, such as Geneve (TLV options) and GTP-U. There are
net/mlx5: DR, Add support for dynamic flex parser
Flex parser is a HW parser that can support protocols that are not natively supported by the HCA, such as Geneve (TLV options) and GTP-U. There are 8 such parsers, and each of them can be assigned to parse a specific set of protocols. This patch adds misc4 match params which allows using a correct flex parser that was programmed to the required protocol.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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Revision tags: v5.8.17 |
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#
323b91ac |
| 21-Oct-2020 |
Muhammad Sammar <muhammads@nvidia.com> |
net/mlx5: DR, Remove protocol-specific flex_parser_3 definitions
Remove MPLS specific fields from flex parser 3 layout. Flex parser can be used for multiple protocols and should not be hardcoded to
net/mlx5: DR, Remove protocol-specific flex_parser_3 definitions
Remove MPLS specific fields from flex parser 3 layout. Flex parser can be used for multiple protocols and should not be hardcoded to a specific type.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
4fe45e1d |
| 06-Dec-2020 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Use HW specific logic API when writing STE
STEv0 format and STEv1 HW format are different, each has a different order: STEv0: CTRL 32B, TAG 16B, BITMASK 16B STEv1: CTRL 32B, BITMASK 16
net/mlx5: DR, Use HW specific logic API when writing STE
STEv0 format and STEv1 HW format are different, each has a different order: STEv0: CTRL 32B, TAG 16B, BITMASK 16B STEv1: CTRL 32B, BITMASK 16B, TAG 16B
To make this transparent to upper layers we introduce a new ste_ctx function to format the STE prior to writing it.
Signed-off-by: Erez Shitrit <erezsh@nvidia.com> Signed-off-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
10b69418 |
| 01-Dec-2020 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Add HW STEv1 match logic
Add STEv1 match logic to a new file. This file will be used for HW specific STEv1.
Signed-off-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Yevgeny Klitey
net/mlx5: DR, Add HW STEv1 match logic
Add STEv1 match logic to a new file. This file will be used for HW specific STEv1.
Signed-off-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
4781df92 |
| 18-Nov-2020 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Move STEv0 modify header logic
Move HW specific modify header fields and logic to STEv0 file and use the new STE context callbacks. Since STEv0 and STEv1 modify actions values are diff
net/mlx5: DR, Move STEv0 modify header logic
Move HW specific modify header fields and logic to STEv0 file and use the new STE context callbacks. Since STEv0 and STEv1 modify actions values are different, each version has its own implementation.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
3ad5838f |
| 18-Nov-2020 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Add STE modify header actions per-device API
Extend the STE context struct with per-device modify header actions.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Sa
net/mlx5: DR, Add STE modify header actions per-device API
Extend the STE context struct with per-device modify header actions.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
8f9a822e |
| 18-Nov-2020 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Add STE tx/rx actions per-device API
Extend the STE context struct with per-device tx/rx actions.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Saeed Mahameed <sa
net/mlx5: DR, Add STE tx/rx actions per-device API
Extend the STE context struct with per-device tx/rx actions.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
6c1f0e4d |
| 18-Nov-2020 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Add STE setters and getters per-device API
Extend the STE context struct with various per-device setters and getters.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by
net/mlx5: DR, Add STE setters and getters per-device API
Extend the STE context struct with various per-device setters and getters.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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Revision tags: v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11 |
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#
46779098 |
| 21-Sep-2020 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Merge similar DR STE SET macros
Merge DR_STE_STE macros for better code reuse, the macro DR_STE_SET_MASK_V and DR_STE_SET_TAG are merged to avoid tag and bit_mask function creation whi
net/mlx5: DR, Merge similar DR STE SET macros
Merge DR_STE_STE macros for better code reuse, the macro DR_STE_SET_MASK_V and DR_STE_SET_TAG are merged to avoid tag and bit_mask function creation which are usually the same.
Signed-off-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
d65e841d |
| 18-Nov-2020 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Move HW STEv0 match logic to a separate file
Move current STE match logic to a seprate file. This file will be used for HW specific STEv0.
Future patches will add functionality for v1
net/mlx5: DR, Move HW STEv0 match logic to a separate file
Move current STE match logic to a seprate file. This file will be used for HW specific STEv0.
Future patches will add functionality for v1 steering.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
5212f9c6 |
| 18-Nov-2020 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Use the new HW specific STE infrastructure
Split the STE builders functionality into the common part and device-specific part. All the device-specific part (with 'v0' in the function n
net/mlx5: DR, Use the new HW specific STE infrastructure
Split the STE builders functionality into the common part and device-specific part. All the device-specific part (with 'v0' in the function names) is accessed through the STE context structure.
Subsequent patches will have the device-specific logic moved to a separate file.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
75699246 |
| 18-Nov-2020 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Move macros from dr_ste.c to header
Move some macros from dr_ste.c to header - these macros will be used by all the format-specific functions.
Signed-off-by: Yevgeny Kliteynik <klitey
net/mlx5: DR, Move macros from dr_ste.c to header
Move some macros from dr_ste.c to header - these macros will be used by all the format-specific functions.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
4bdba39b |
| 18-Nov-2020 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Add infrastructure for supporting several steering formats
Add a struct of device specific callbacks for STE layer below dr_ste. Each device will implement its HW-specific function, an
net/mlx5: DR, Add infrastructure for supporting several steering formats
Add a struct of device specific callbacks for STE layer below dr_ste. Each device will implement its HW-specific function, and a comon logic from the DR code will access these functions through the new ste_ctx API.
More callbacks will follow in the subsequent patches.
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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