d9edc4bc | 11-Apr-2022 |
Han Xu <han.xu@nxp.com> |
mtd: rawnand: gpmi: Add large oob bch setting support
The code change proposes a new way to set bch geometry for large oob NAND (oobsize > 1KB). In this case, previous implementation can NOT guarant
mtd: rawnand: gpmi: Add large oob bch setting support
The code change proposes a new way to set bch geometry for large oob NAND (oobsize > 1KB). In this case, previous implementation can NOT guarantee the bad block mark always locates in data chunk, so we need a new way to do it. The general idea is,
1.Try all ECC strength from the maximum ecc that controller can support to minimum value required by NAND chip, any ECC strength makes the BBM locate in data chunk can be eligible.
2.If none of them works, using separate ECC for meta, which will add one extra ecc with the same ECC strength as other data chunks. This extra ECC can guarantee BBM located in data chunk, also we need to check if oob can afford it.
Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220412025246.24269-6-han.xu@nxp.com
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2fb038ea | 11-Apr-2022 |
Han Xu <han.xu@nxp.com> |
mtd: rawnand: gpmi: Rename the variable ecc_chunk_size
There is only one variable ecc_chunk_size in bch_geometry data structure but two different field in BCH registers. The data0_size in BCH_FLASH0
mtd: rawnand: gpmi: Rename the variable ecc_chunk_size
There is only one variable ecc_chunk_size in bch_geometry data structure but two different field in BCH registers. The data0_size in BCH_FLASH0LAYOUT0 and datan_size in BCH_FLASH0LAYOUT1 should have dedicate variable since they might set to different values in some cases. For instance, if need dedicate ecc for meta area, the data0_size should be 0 rather than datan_size, but for all other cases, data0_size still equals to datan_size and it won't bring any function change.
Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220412025246.24269-5-han.xu@nxp.com
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10915857 | 11-Apr-2022 |
Han Xu <han.xu@nxp.com> |
mtd: rawnand: gpmi: Uninline the gpmi_check_ecc function
The gpmi_check_ecc() is not small after adding more strict ecc check, uninline it.
Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Miq
mtd: rawnand: gpmi: Uninline the gpmi_check_ecc function
The gpmi_check_ecc() is not small after adding more strict ecc check, uninline it.
Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220412025246.24269-4-han.xu@nxp.com
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ac178a21 | 18-Jan-2022 |
Dario Binacchi <dario.binacchi@amarulasolutions.com> |
mtd: rawnand: gpmi: support fast edo timings for mx28
In the i.MX28 manual (MCIMX28RM, Rev. 1, 2010) you can find an example (15.2.4 High-Speed NAND Timing) of how to configure the GPMI controller t
mtd: rawnand: gpmi: support fast edo timings for mx28
In the i.MX28 manual (MCIMX28RM, Rev. 1, 2010) you can find an example (15.2.4 High-Speed NAND Timing) of how to configure the GPMI controller to manage High-Speed NAND devices, so it was wrong to assume that only i.MX6 can achieve EDO timings.
This patch has been tested on a 2048/64 byte NAND (Micron MT29F2G08ABAEAH4). Kernel mtd tests: - mtd_nandbiterrs - mtd_nandecctest - mtd_oobtest - mtd_pagetest - mtd_readtest - mtd_speedtest - mtd_stresstest - mtd_subpagetest - mtd_torturetest [cycles_count = 10000000] run without errors.
Before this patch (mode 0): --------------------------- eraseblock write speed is 2098 KiB/s eraseblock read speed is 2680 KiB/s page write speed is 1689 KiB/s page read speed is 2522 KiB/s 2 page write speed is 1899 KiB/s 2 page read speed is 2579 KiB/s erase speed is 128000 KiB/s 2x multi-block erase speed is 73142 KiB/s 4x multi-block erase speed is 204800 KiB/s 8x multi-block erase speed is 256000 KiB/s 16x multi-block erase speed is 256000 KiB/s 32x multi-block erase speed is 256000 KiB/s 64x multi-block erase speed is 256000 KiB/s
After this patch (mode 5): ------------------------- eraseblock write speed is 3390 KiB/s eraseblock read speed is 5688 KiB/s page write speed is 2680 KiB/s page read speed is 4876 KiB/s 2 page write speed is 2909 KiB/s 2 page read speed is 5224 KiB/s erase speed is 170666 KiB/s 2x multi-block erase speed is 204800 KiB/s 4x multi-block erase speed is 256000 KiB/s 8x multi-block erase speed is 256000 KiB/s 16x multi-block erase speed is 256000 KiB/s 32x multi-block erase speed is 256000 KiB/s 64x multi-block erase speed is 256000 KiB/s
Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Tested-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220118095434.35081-5-dario.binacchi@amarulasolutions.com
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15e27d19 | 18-Jan-2022 |
Dario Binacchi <dario.binacchi@amarulasolutions.com> |
mtd: rawnand: gpmi: validate controller clock rate
What to do when the real rate of the gpmi clock is not equal to the required one? The solutions proposed in [1] did not lead to a conclusion on how
mtd: rawnand: gpmi: validate controller clock rate
What to do when the real rate of the gpmi clock is not equal to the required one? The solutions proposed in [1] did not lead to a conclusion on how to validate the clock rate, so, inspired by the document [2], I consider the rate correct only if not lower or equal to the rate of the previous edo mode. In fact, in chapter 4.16.2 (NV-DDR) of the document [2], it is written that "If the host selects timing mode n, then its clock period shall be faster than the clock period of timing mode n-1 and slower than or equal to the clock period of timing mode n.". I thought that it could therefore also be used in this case, without therefore having to define the valid rate ranges empirically.
For example, suppose that gpmi_nfc_compute_timings() is called to set edo mode 5 (100MHz) but the rate returned by clk_round_rate() is 80MHz (edo mode 4). In this case gpmi_nfc_compute_timings() will return error, and will be called again to set edo mode 4, which this time will be successful.
[1] https://lore.kernel.org/r/20210702065350.209646-5-ebiggers@kernel.org [2] http://www.onfi.org/-/media/client/onfi/specs/onfi_3_0_gold.pdf?la=en
Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Tested-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220118095434.35081-4-dario.binacchi@amarulasolutions.com
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ecb78b29 | 21-Dec-2021 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
mtd: rawnand: gpmi: Use platform_get_irq_byname() to get the interrupt
platform_get_resource_byname(pdev, IORESOURCE_IRQ, ..) relies on static allocation of IRQ resources in DT core code, this cause
mtd: rawnand: gpmi: Use platform_get_irq_byname() to get the interrupt
platform_get_resource_byname(pdev, IORESOURCE_IRQ, ..) relies on static allocation of IRQ resources in DT core code, this causes an issue when using hierarchical interrupt domains using "interrupts" property in the node as this bypasses the hierarchical setup and messes up the irq chaining.
In preparation for removal of static setup of IRQ resource from DT core code use platform_get_irq_byname().
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211221212609.31290-3-prabhakar.mahadev-lad.rj@bp.renesas.com
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f53d4c10 | 02-Nov-2021 |
Christian Eggers <ceggers@arri.de> |
mtd: rawnand: gpmi: Add ERR007117 protection for nfc_apply_timings
gpmi_io clock needs to be gated off when changing the parent/dividers of enfc_clk_root (i.MX6Q/i.MX6UL) respectively qspi2_clk_root
mtd: rawnand: gpmi: Add ERR007117 protection for nfc_apply_timings
gpmi_io clock needs to be gated off when changing the parent/dividers of enfc_clk_root (i.MX6Q/i.MX6UL) respectively qspi2_clk_root (i.MX6SX). Otherwise this rate change can lead to an unresponsive GPMI core which results in DMA timeouts and failed driver probe:
[ 4.072318] gpmi-nand 112000.gpmi-nand: DMA timeout, last DMA ... [ 4.370355] gpmi-nand 112000.gpmi-nand: Chip: 0, Error -110 ... [ 4.375988] gpmi-nand 112000.gpmi-nand: Chip: 0, Error -22 [ 4.381524] gpmi-nand 112000.gpmi-nand: Error in ECC-based read: -22 [ 4.387988] gpmi-nand 112000.gpmi-nand: Chip: 0, Error -22 [ 4.393535] gpmi-nand 112000.gpmi-nand: Chip: 0, Error -22 ...
Other than stated in i.MX 6 erratum ERR007117, it should be sufficient to gate only gpmi_io because all other bch/nand clocks are derived from different clock roots.
The i.MX6 reference manuals state that changing clock muxers can cause glitches but are silent about changing dividers. But tests showed that these glitches can definitely happen on i.MX6ULL. For i.MX7D/8MM in turn, the manual guarantees that no glitches can happen when changing dividers.
Co-developed-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Christian Eggers <ceggers@arri.de> Cc: stable@vger.kernel.org Acked-by: Han Xu <han.xu@nxp.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211102202022.15551-2-ceggers@arri.de
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ea7110b8 | 08-Dec-2020 |
Fabio Estevam <festevam@gmail.com> |
mtd: rawnand: gpmi: Use a single line for of_device_id
The .compatible and .data pairs can be stored in a single line, which makes the code more concise.
Signed-off-by: Fabio Estevam <festevam@gmai
mtd: rawnand: gpmi: Use a single line for of_device_id
The .compatible and .data pairs can be stored in a single line, which makes the code more concise.
Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20201208221243.3255-1-festevam@gmail.com
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