Revision tags: v4.4.1 |
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aed26fca |
| 29-Jan-2016 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Enable eMMC HS-DDR (MMC_CAP_1_8V_DDR) support Now that clock delay settings for 8 bit DDR are correct, and vqmmc support is available, we can enable MMC_CAP_1_8V_DDR support.
mmc: sunxi: Enable eMMC HS-DDR (MMC_CAP_1_8V_DDR) support Now that clock delay settings for 8 bit DDR are correct, and vqmmc support is available, we can enable MMC_CAP_1_8V_DDR support. This enables MMC HS-DDR at up to 52 MHz, even if signal voltage switching is not available. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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2a7aa63a |
| 29-Jan-2016 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Support 8 bit eMMC DDR transfer modes Allwinner's MMC controller needs to run at double the card clock rate for 8 bit DDR transfer modes. Interestingly, this is not needed fo
mmc: sunxi: Support 8 bit eMMC DDR transfer modes Allwinner's MMC controller needs to run at double the card clock rate for 8 bit DDR transfer modes. Interestingly, this is not needed for 4 bit DDR transfers. Different clock delays are needed for 8 bit eMMC DDR, due to the increased module clock rate. For the A80 though, the same values for 4 bit and 8 bit are shared. The new values for the other SoCs were from A83T user manual's "new timing mode" default values, which describes them in clock phase, rather than delay periods. These values were used without any modification. They may not be correct, but they work. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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2dcb305a |
| 29-Jan-2016 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Support MMC_DDR52 timing modes DDR transfer modes include UHS-1 DDR50 and MMC HS-DDR (or MMC_DDR52). Consider MMC_DDR52 when setting clock delays. Since MMC high spe
mmc: sunxi: Support MMC_DDR52 timing modes DDR transfer modes include UHS-1 DDR50 and MMC HS-DDR (or MMC_DDR52). Consider MMC_DDR52 when setting clock delays. Since MMC high speed mode goes up to 52 MHz instead of 50 MHz for SD, and this number is visible in the capability macro, increase the clock rate upper limit to 52 MHz. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: openbmc-20160127-1 |
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f771f6e8 |
| 20-Jan-2016 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Support vqmmc regulator eMMC chips require 2 power supplies, vmmc for internal logic, and vqmmc for driving output buffers. vqmmc also controls signaling voltage. Most bo
mmc: sunxi: Support vqmmc regulator eMMC chips require 2 power supplies, vmmc for internal logic, and vqmmc for driving output buffers. vqmmc also controls signaling voltage. Most boards we've seen use the same regulator for both, nevertheless the 2 have different usages, and should be set separately. This patch adds support for vqmmc regulator supply, including voltage switching. The MMC core can use this to try different signaling voltages for eMMC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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4159215a |
| 20-Jan-2016 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Return error on mmc_regulator_set_ocr() fail in .set_ios op Let .set_ios() fail if mmc_regulator_set_ocr() fails to enable and set a proper voltage for vmmc. Signed-
mmc: sunxi: Return error on mmc_regulator_set_ocr() fail in .set_ios op Let .set_ios() fail if mmc_regulator_set_ocr() fails to enable and set a proper voltage for vmmc. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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0314cbd4 |
| 20-Jan-2016 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Document host init sequence sunxi_mmc_init_host() originated from Allwinner kernel sources. The magic numbers written to various registers was never documented. Add
mmc: sunxi: Document host init sequence sunxi_mmc_init_host() originated from Allwinner kernel sources. The magic numbers written to various registers was never documented. Add comments for values found in Allwinner user manuals. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: openbmc-20160120-1, v4.4, openbmc-20151217-1, openbmc-20151210-1, openbmc-20151202-1, openbmc-20151123-1, openbmc-20151118-1, openbmc-20151104-1, v4.3, openbmc-20151102-1, openbmc-20151028-1 |
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c1590dd8 |
| 22-Sep-2015 |
Hans de Goede <hdegoede@redhat.com> |
mmc: sunxi: Add card busy detection Some sdio wifi modules have not been working reliable with the sunxi-mmc host code. This turns out to be caused by starting new io-rw commands while
mmc: sunxi: Add card busy detection Some sdio wifi modules have not been working reliable with the sunxi-mmc host code. This turns out to be caused by starting new io-rw commands while the card signals that it is still busy processing a previous command. This commit adds card-busy detection to the sunxi-mmc driver which together with recent core changes to check card-busy before starting io-rw commands fixes the wifi reliability issues on the Cubietruck and other sunxi boards using sdio wifi. Reported-by: Eugene K <sigintmailru@gmail.com> Suggested-by: Eugene K <sigintmailru@gmail.com> Cc: Eugene K <sigintmailru@gmail.com> Cc: Arend van Spriel <arend@broadcom.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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51424b28 |
| 23-Sep-2015 |
Hans de Goede <hdegoede@redhat.com> |
mmc: sunxi: Fix clk-delay settings In recent allwinner kernel sources the mmc clk-delay settings have been slightly tweaked, and for sun9i they are completely different then what we
mmc: sunxi: Fix clk-delay settings In recent allwinner kernel sources the mmc clk-delay settings have been slightly tweaked, and for sun9i they are completely different then what we are using. This commit brings us in sync with what allwinner does, fixing problems accessing sdcards on some A33 devices (and likely others). For pre sun9i hardware this makes the following changes: -At 400Khz change the sample delay from 7 to 0 (introduced in A31 sdk) -At 50 Mhz change the sample delay from 5 to 4 (introduced in A23 sdk) This also drops the clk-delay calculation for clocks > 50 MHz, we do not need this as we've: mmc->f_max = 50000000, and the delays in the old code were not correct (at 100 MHz the delay must be a multiple of 60, at 200 MHz a multiple of 120). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v4.3-rc1, v4.2, v4.2-rc8, v4.2-rc7 |
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7bb9c244 |
| 12-Aug-2015 |
Michal Suchanek <hramrach@gmail.com> |
mmc: sunxi: fix timeout in sunxi_mmc_oclk_onoff The 250ms timeout is too short. On my system enabling the oclk takes under 50ms and disabling slightly over 100ms when idle. Unde
mmc: sunxi: fix timeout in sunxi_mmc_oclk_onoff The 250ms timeout is too short. On my system enabling the oclk takes under 50ms and disabling slightly over 100ms when idle. Under load disabling the clock can take over 350ms. This does not make mmc clock gating look like good option to have on sunxi but the system should not crash with mmc clock gating enabled nonetheless. This patch sets the timeout to 750ms. Signed-off-by: Michal Suchanek <hramrach@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v4.2-rc6, v4.2-rc5, v4.2-rc4, v4.2-rc3, v4.2-rc2, v4.2-rc1, v4.1, v4.1-rc8, v4.1-rc7, v4.1-rc6, v4.1-rc5, v4.1-rc4, v4.1-rc3, v4.1-rc2, v4.1-rc1, v4.0, v4.0-rc7, v4.0-rc6, v4.0-rc5, v4.0-rc4 |
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a4101dcb |
| 10-Mar-2015 |
Hans de Goede <hdegoede@redhat.com> |
mmc: sunxi: add MMC_CAP_SDIO_IRQ capability When the sunxi mmc-controller code was initially merged MMC_CAP_SDIO_IRQ was not added to the host caps because of issues with some sdio wifi
mmc: sunxi: add MMC_CAP_SDIO_IRQ capability When the sunxi mmc-controller code was initially merged MMC_CAP_SDIO_IRQ was not added to the host caps because of issues with some sdio wifi modules. It turns out that these issues have nothing to do with using sdio-irq support, they also happen with oob interrupts. Since the hardware supports sdio-irq everywhere, and since the one reason to not claim the capability is gone, add MMC_CAP_SDIO_IRQ to the default host caps. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v4.0-rc3, v4.0-rc2 |
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d34712d2 |
| 24-Feb-2015 |
Arnd Bergmann <arnd@arndb.de> |
mmc: sunxi: avoid invalid pointer calculation The sunxi mmc driver tries to calculate a dma address by using pointer arithmetic, which causes a warning when dma_addr_t is wider than a po
mmc: sunxi: avoid invalid pointer calculation The sunxi mmc driver tries to calculate a dma address by using pointer arithmetic, which causes a warning when dma_addr_t is wider than a pointer: drivers/mmc/host/sunxi-mmc.c: In function 'sunxi_mmc_init_idma_des': drivers/mmc/host/sunxi-mmc.c:296:35: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] struct sunxi_idma_des *pdes_pa = (struct sunxi_idma_des *)host->sg_dma; ^ To avoid this warning and to simplify the logic, this changes the code to avoid the cast and calculate the correct address manually. The behavior should be unchanged. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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9e71c589 |
| 02-Mar-2015 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Use devm_reset_control_get_optional() for reset control The reset control for the sunxi mmc controller is optional. Some newer platforms (sun6i, sun8i, sun9i) have it, while
mmc: sunxi: Use devm_reset_control_get_optional() for reset control The reset control for the sunxi mmc controller is optional. Some newer platforms (sun6i, sun8i, sun9i) have it, while older ones (sun4i, sun5i, sun7i) don't. Use the properly stubbed _optional version so the driver does not fail to compile when RESET_CONTROLLER=n. This patch also adds a check for deferred probing on the reset control. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Cc: <stable@vger.kernel.org> # 3.16+ Acked-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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18a8d499 |
| 21-Feb-2015 |
Linus Torvalds <torvalds@linux-foundation.org> |
Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux Pull clock framework updates from Mike Turquette: "The clock framework changes contain the usual drive
Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux Pull clock framework updates from Mike Turquette: "The clock framework changes contain the usual driver additions, enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based devices. Additionally the framework core underwent a bit of surgery with two major changes: - The boundary between the clock core and clock providers (e.g clock drivers) is now more well defined with dedicated provider helper functions. struct clk no longer maps 1:1 with the hardware clock but is a true per-user cookie which helps us tracker users of hardware clocks and debug bad behavior. - The addition of rate constraints for clocks. Rate ranges are now supported which are analogous to the voltage ranges in the regulator framework. Unfortunately these changes to the core created some breakeage. We think we fixed it all up but for this reason there are lots of last minute commits trying to undo the damage" * tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits) clk: Only recalculate the rate if needed Revert "clk: mxs: Fix invalid 32-bit access to frac registers" clk: qoriq: Add support for the platform PLL powerpc/corenet: Enable CLK_QORIQ clk: Replace explicit clk assignment with __clk_hw_set_clk clk: Add __clk_hw_set_clk helper function clk: Don't dereference parent clock if is NULL MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr clkdev: Always allocate a struct clk and call __clk_get() w/ CCF clk: shmobile: div6: Avoid division by zero in .round_rate() clk: mxs: Fix invalid 32-bit access to frac registers clk: omap: compile legacy omap3 clocks conditionally clkdev: Export clk_register_clkdev clk: Add rate constraints to clocks clk: remove clk-private.h pci: xgene: do not use clk-private.h arm: omap2+ remove dead clock code clk: Make clk API return per-user struct clk instances clk: tegra: Define PLLD_DSI and remove dsia(b)_mux clk: tegra: Add support for the Tegra132 CAR IP block ...
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Revision tags: v4.0-rc1, v3.19, v3.19-rc7, v3.19-rc6, v3.19-rc5, v3.19-rc4, v3.19-rc3, v3.19-rc2, v3.19-rc1 |
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de0673cd |
| 16-Dec-2014 |
David Lanzendörfer <david.lanzendoerfer@o2s.ch> |
mmc: sunxi: Removing unused code Removing a relict from reverse engineering of the Android driver code in sunxi_mmc_clk_set_rate. Signed-off-by: David Lanzendörfer <david.lanzen
mmc: sunxi: Removing unused code Removing a relict from reverse engineering of the Android driver code in sunxi_mmc_clk_set_rate. Signed-off-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch> Reported-by: <lixiang@allwinnertech.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
0f0fcd37 |
| 16-Dec-2014 |
David Lanzendörfer <david.lanzendoerfer@o2s.ch> |
mmc: sunxi: Correcting SDXC_HARDWARE_RESET bit Fixing the register name in sunxi_mmc_reset_host since the SDXC_HARDWARE_RESET bit is actually located within REG_GCTRL and not REG_CMD
mmc: sunxi: Correcting SDXC_HARDWARE_RESET bit Fixing the register name in sunxi_mmc_reset_host since the SDXC_HARDWARE_RESET bit is actually located within REG_GCTRL and not REG_CMDR as it was pointed out by Allwinner. Signed-off-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch> Reported-by: <lixiang@allwinnertech.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
dd9b3803 |
| 16-Dec-2014 |
David Lanzendörfer <david.lanzendoerfer@o2s.ch> |
mmc: sunxi: Lock fix 1) Adding a comment in order to clarify the choice of the locks within sunxi_mmc_handle_manual_stop 2) As <lixiang@allwinnertech.com> has pointed out the wa
mmc: sunxi: Lock fix 1) Adding a comment in order to clarify the choice of the locks within sunxi_mmc_handle_manual_stop 2) As <lixiang@allwinnertech.com> has pointed out the wait_dma variable was not accessed within the spin lock block in sunxi_mmc_request and so (even if it should never happend) it would have theoretically been possible that some other function would access the variable at the same time as the function. This has been changed now and the function is using local variables outside the lock and copys the value over during the lock phase. Signed-off-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch> Reported-by: <lixiang@allwinnertech.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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e8a59049 |
| 16-Dec-2014 |
Hans de Goede <hdegoede@redhat.com> |
mmc: sunxi: Fix setup of last descriptor of dma transfer The last descriptor might be the first descriptor as well, so use masking to add the LD (last descriptor) bit and drop the DIC (d
mmc: sunxi: Fix setup of last descriptor of dma transfer The last descriptor might be the first descriptor as well, so use masking to add the LD (last descriptor) bit and drop the DIC (disable interrupt on completion) bit rather then hard assignment as hard assignment will override the FD (first descriptor) bit if there is only 1 descriptor. Also set the ER (end of ring) bit and clear buf_addr_ptr2 on the last descriptor, like the android kernel code does. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch> Reported-by: <lixiang@allwinnertech.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v3.18, v3.18-rc7, v3.18-rc6, v3.18-rc5, v3.18-rc4, v3.18-rc3, v3.18-rc2, v3.18-rc1, v3.17, v3.17-rc7, v3.17-rc6, v3.17-rc5, v3.17-rc4, v3.17-rc3, v3.17-rc2, v3.17-rc1, v3.16, v3.16-rc7, v3.16-rc6, v3.16-rc5 |
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#
6c09bb85 |
| 12-Jul-2014 |
Maxime Ripard <maxime.ripard@free-electrons.com> |
mmc: sunxi: Convert MMC driver to the standard clock phase API Now that we have proper support to use the generic phase API in our clock driver, switch the MMC driver to use it.
mmc: sunxi: Convert MMC driver to the standard clock phase API Now that we have proper support to use the generic phase API in our clock driver, switch the MMC driver to use it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Chen-Yu Tsai <wens@csie.org>
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#
05e07d8b |
| 03-Oct-2014 |
Tomeu Vizoso <tomeu.vizoso@collabora.com> |
mmc: sunxi: Remove unused includes of linux/clk-private.h Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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3df01a93 |
| 20-Aug-2014 |
Chen-Yu Tsai <wens@csie.org> |
mmc: sunxi: Declare ERASE capability Declare ERASE capability so we can use filesystems with the discard option and the fstrim tool. Signed-off-by: Chen-Yu Tsai <wens@csie.org>
mmc: sunxi: Declare ERASE capability Declare ERASE capability so we can use filesystems with the discard option and the fstrim tool. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
2137f5d3 |
| 12-Aug-2014 |
Peter Griffin <peter.griffin@linaro.org> |
mmc: remove .owner field for drivers using module_platform_driver This patch removes the superflous .owner field for drivers which use the module_platform_driver API, as this is override
mmc: remove .owner field for drivers using module_platform_driver This patch removes the superflous .owner field for drivers which use the module_platform_driver API, as this is overriden in platform_driver_register anyway. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v3.16-rc4, v3.16-rc3, v3.16-rc2, v3.16-rc1, v3.15, v3.15-rc8, v3.15-rc7, v3.15-rc6 |
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#
3cbcb160 |
| 12-May-2014 |
David Lanzendörfer <david.lanzendoerfer@o2s.ch> |
mmc: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs The Allwinner sunxi mmc host uses dma in bus-master mode using a built-in designware idmac controller, which is iden
mmc: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs The Allwinner sunxi mmc host uses dma in bus-master mode using a built-in designware idmac controller, which is identical to the one found in the mmc-dw hosts. However the rest of the host is not identical to mmc-dw, it deals with sending stop commands in hardware which makes it significantly different from the mmc-dw devices. Signed-off-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch> [hdegoede@redhat.com: various cleanups and fixes] Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Chris Ball <chris@printf.net> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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