1 /* 2 * Driver for sunxi SD/MMC host controllers 3 * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd. 4 * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com> 5 * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch> 6 * (C) Copyright 2013-2014 David Lanzend�rfer <david.lanzendoerfer@o2s.ch> 7 * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/io.h> 18 #include <linux/device.h> 19 #include <linux/interrupt.h> 20 #include <linux/delay.h> 21 #include <linux/err.h> 22 23 #include <linux/clk.h> 24 #include <linux/clk/sunxi.h> 25 26 #include <linux/gpio.h> 27 #include <linux/platform_device.h> 28 #include <linux/spinlock.h> 29 #include <linux/scatterlist.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/slab.h> 32 #include <linux/reset.h> 33 34 #include <linux/of_address.h> 35 #include <linux/of_gpio.h> 36 #include <linux/of_platform.h> 37 38 #include <linux/mmc/host.h> 39 #include <linux/mmc/sd.h> 40 #include <linux/mmc/sdio.h> 41 #include <linux/mmc/mmc.h> 42 #include <linux/mmc/core.h> 43 #include <linux/mmc/card.h> 44 #include <linux/mmc/slot-gpio.h> 45 46 /* register offset definitions */ 47 #define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */ 48 #define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */ 49 #define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */ 50 #define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */ 51 #define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */ 52 #define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */ 53 #define SDXC_REG_CMDR (0x18) /* SMC Command Register */ 54 #define SDXC_REG_CARG (0x1C) /* SMC Argument Register */ 55 #define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */ 56 #define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */ 57 #define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */ 58 #define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */ 59 #define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */ 60 #define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */ 61 #define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */ 62 #define SDXC_REG_STAS (0x3C) /* SMC Status Register */ 63 #define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */ 64 #define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */ 65 #define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */ 66 #define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */ 67 #define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */ 68 #define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */ 69 #define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */ 70 #define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */ 71 #define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */ 72 #define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */ 73 #define SDXC_REG_CHDA (0x90) 74 #define SDXC_REG_CBDA (0x94) 75 76 #define mmc_readl(host, reg) \ 77 readl((host)->reg_base + SDXC_##reg) 78 #define mmc_writel(host, reg, value) \ 79 writel((value), (host)->reg_base + SDXC_##reg) 80 81 /* global control register bits */ 82 #define SDXC_SOFT_RESET BIT(0) 83 #define SDXC_FIFO_RESET BIT(1) 84 #define SDXC_DMA_RESET BIT(2) 85 #define SDXC_INTERRUPT_ENABLE_BIT BIT(4) 86 #define SDXC_DMA_ENABLE_BIT BIT(5) 87 #define SDXC_DEBOUNCE_ENABLE_BIT BIT(8) 88 #define SDXC_POSEDGE_LATCH_DATA BIT(9) 89 #define SDXC_DDR_MODE BIT(10) 90 #define SDXC_MEMORY_ACCESS_DONE BIT(29) 91 #define SDXC_ACCESS_DONE_DIRECT BIT(30) 92 #define SDXC_ACCESS_BY_AHB BIT(31) 93 #define SDXC_ACCESS_BY_DMA (0 << 31) 94 #define SDXC_HARDWARE_RESET \ 95 (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET) 96 97 /* clock control bits */ 98 #define SDXC_CARD_CLOCK_ON BIT(16) 99 #define SDXC_LOW_POWER_ON BIT(17) 100 101 /* bus width */ 102 #define SDXC_WIDTH1 0 103 #define SDXC_WIDTH4 1 104 #define SDXC_WIDTH8 2 105 106 /* smc command bits */ 107 #define SDXC_RESP_EXPIRE BIT(6) 108 #define SDXC_LONG_RESPONSE BIT(7) 109 #define SDXC_CHECK_RESPONSE_CRC BIT(8) 110 #define SDXC_DATA_EXPIRE BIT(9) 111 #define SDXC_WRITE BIT(10) 112 #define SDXC_SEQUENCE_MODE BIT(11) 113 #define SDXC_SEND_AUTO_STOP BIT(12) 114 #define SDXC_WAIT_PRE_OVER BIT(13) 115 #define SDXC_STOP_ABORT_CMD BIT(14) 116 #define SDXC_SEND_INIT_SEQUENCE BIT(15) 117 #define SDXC_UPCLK_ONLY BIT(21) 118 #define SDXC_READ_CEATA_DEV BIT(22) 119 #define SDXC_CCS_EXPIRE BIT(23) 120 #define SDXC_ENABLE_BIT_BOOT BIT(24) 121 #define SDXC_ALT_BOOT_OPTIONS BIT(25) 122 #define SDXC_BOOT_ACK_EXPIRE BIT(26) 123 #define SDXC_BOOT_ABORT BIT(27) 124 #define SDXC_VOLTAGE_SWITCH BIT(28) 125 #define SDXC_USE_HOLD_REGISTER BIT(29) 126 #define SDXC_START BIT(31) 127 128 /* interrupt bits */ 129 #define SDXC_RESP_ERROR BIT(1) 130 #define SDXC_COMMAND_DONE BIT(2) 131 #define SDXC_DATA_OVER BIT(3) 132 #define SDXC_TX_DATA_REQUEST BIT(4) 133 #define SDXC_RX_DATA_REQUEST BIT(5) 134 #define SDXC_RESP_CRC_ERROR BIT(6) 135 #define SDXC_DATA_CRC_ERROR BIT(7) 136 #define SDXC_RESP_TIMEOUT BIT(8) 137 #define SDXC_DATA_TIMEOUT BIT(9) 138 #define SDXC_VOLTAGE_CHANGE_DONE BIT(10) 139 #define SDXC_FIFO_RUN_ERROR BIT(11) 140 #define SDXC_HARD_WARE_LOCKED BIT(12) 141 #define SDXC_START_BIT_ERROR BIT(13) 142 #define SDXC_AUTO_COMMAND_DONE BIT(14) 143 #define SDXC_END_BIT_ERROR BIT(15) 144 #define SDXC_SDIO_INTERRUPT BIT(16) 145 #define SDXC_CARD_INSERT BIT(30) 146 #define SDXC_CARD_REMOVE BIT(31) 147 #define SDXC_INTERRUPT_ERROR_BIT \ 148 (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \ 149 SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \ 150 SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR) 151 #define SDXC_INTERRUPT_DONE_BIT \ 152 (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \ 153 SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE) 154 155 /* status */ 156 #define SDXC_RXWL_FLAG BIT(0) 157 #define SDXC_TXWL_FLAG BIT(1) 158 #define SDXC_FIFO_EMPTY BIT(2) 159 #define SDXC_FIFO_FULL BIT(3) 160 #define SDXC_CARD_PRESENT BIT(8) 161 #define SDXC_CARD_DATA_BUSY BIT(9) 162 #define SDXC_DATA_FSM_BUSY BIT(10) 163 #define SDXC_DMA_REQUEST BIT(31) 164 #define SDXC_FIFO_SIZE 16 165 166 /* Function select */ 167 #define SDXC_CEATA_ON (0xceaa << 16) 168 #define SDXC_SEND_IRQ_RESPONSE BIT(0) 169 #define SDXC_SDIO_READ_WAIT BIT(1) 170 #define SDXC_ABORT_READ_DATA BIT(2) 171 #define SDXC_SEND_CCSD BIT(8) 172 #define SDXC_SEND_AUTO_STOPCCSD BIT(9) 173 #define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10) 174 175 /* IDMA controller bus mod bit field */ 176 #define SDXC_IDMAC_SOFT_RESET BIT(0) 177 #define SDXC_IDMAC_FIX_BURST BIT(1) 178 #define SDXC_IDMAC_IDMA_ON BIT(7) 179 #define SDXC_IDMAC_REFETCH_DES BIT(31) 180 181 /* IDMA status bit field */ 182 #define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0) 183 #define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1) 184 #define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2) 185 #define SDXC_IDMAC_DESTINATION_INVALID BIT(4) 186 #define SDXC_IDMAC_CARD_ERROR_SUM BIT(5) 187 #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8) 188 #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9) 189 #define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10) 190 #define SDXC_IDMAC_IDLE (0 << 13) 191 #define SDXC_IDMAC_SUSPEND (1 << 13) 192 #define SDXC_IDMAC_DESC_READ (2 << 13) 193 #define SDXC_IDMAC_DESC_CHECK (3 << 13) 194 #define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13) 195 #define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13) 196 #define SDXC_IDMAC_READ (6 << 13) 197 #define SDXC_IDMAC_WRITE (7 << 13) 198 #define SDXC_IDMAC_DESC_CLOSE (8 << 13) 199 200 /* 201 * If the idma-des-size-bits of property is ie 13, bufsize bits are: 202 * Bits 0-12: buf1 size 203 * Bits 13-25: buf2 size 204 * Bits 26-31: not used 205 * Since we only ever set buf1 size, we can simply store it directly. 206 */ 207 #define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */ 208 #define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */ 209 #define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */ 210 #define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */ 211 #define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */ 212 #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */ 213 #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */ 214 215 struct sunxi_idma_des { 216 u32 config; 217 u32 buf_size; 218 u32 buf_addr_ptr1; 219 u32 buf_addr_ptr2; 220 }; 221 222 struct sunxi_mmc_host { 223 struct mmc_host *mmc; 224 struct reset_control *reset; 225 226 /* IO mapping base */ 227 void __iomem *reg_base; 228 229 /* clock management */ 230 struct clk *clk_ahb; 231 struct clk *clk_mmc; 232 233 /* irq */ 234 spinlock_t lock; 235 int irq; 236 u32 int_sum; 237 u32 sdio_imask; 238 239 /* dma */ 240 u32 idma_des_size_bits; 241 dma_addr_t sg_dma; 242 void *sg_cpu; 243 bool wait_dma; 244 245 struct mmc_request *mrq; 246 struct mmc_request *manual_stop_mrq; 247 int ferror; 248 }; 249 250 static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host) 251 { 252 unsigned long expire = jiffies + msecs_to_jiffies(250); 253 u32 rval; 254 255 mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET); 256 do { 257 rval = mmc_readl(host, REG_GCTRL); 258 } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET)); 259 260 if (rval & SDXC_HARDWARE_RESET) { 261 dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n"); 262 return -EIO; 263 } 264 265 return 0; 266 } 267 268 static int sunxi_mmc_init_host(struct mmc_host *mmc) 269 { 270 u32 rval; 271 struct sunxi_mmc_host *host = mmc_priv(mmc); 272 273 if (sunxi_mmc_reset_host(host)) 274 return -EIO; 275 276 mmc_writel(host, REG_FTRGL, 0x20070008); 277 mmc_writel(host, REG_TMOUT, 0xffffffff); 278 mmc_writel(host, REG_IMASK, host->sdio_imask); 279 mmc_writel(host, REG_RINTR, 0xffffffff); 280 mmc_writel(host, REG_DBGC, 0xdeb); 281 mmc_writel(host, REG_FUNS, SDXC_CEATA_ON); 282 mmc_writel(host, REG_DLBA, host->sg_dma); 283 284 rval = mmc_readl(host, REG_GCTRL); 285 rval |= SDXC_INTERRUPT_ENABLE_BIT; 286 rval &= ~SDXC_ACCESS_DONE_DIRECT; 287 mmc_writel(host, REG_GCTRL, rval); 288 289 return 0; 290 } 291 292 static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host, 293 struct mmc_data *data) 294 { 295 struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu; 296 struct sunxi_idma_des *pdes_pa = (struct sunxi_idma_des *)host->sg_dma; 297 int i, max_len = (1 << host->idma_des_size_bits); 298 299 for (i = 0; i < data->sg_len; i++) { 300 pdes[i].config = SDXC_IDMAC_DES0_CH | SDXC_IDMAC_DES0_OWN | 301 SDXC_IDMAC_DES0_DIC; 302 303 if (data->sg[i].length == max_len) 304 pdes[i].buf_size = 0; /* 0 == max_len */ 305 else 306 pdes[i].buf_size = data->sg[i].length; 307 308 pdes[i].buf_addr_ptr1 = sg_dma_address(&data->sg[i]); 309 pdes[i].buf_addr_ptr2 = (u32)&pdes_pa[i + 1]; 310 } 311 312 pdes[0].config |= SDXC_IDMAC_DES0_FD; 313 pdes[i - 1].config |= SDXC_IDMAC_DES0_LD | SDXC_IDMAC_DES0_ER; 314 pdes[i - 1].config &= ~SDXC_IDMAC_DES0_DIC; 315 pdes[i - 1].buf_addr_ptr2 = 0; 316 317 /* 318 * Avoid the io-store starting the idmac hitting io-mem before the 319 * descriptors hit the main-mem. 320 */ 321 wmb(); 322 } 323 324 static enum dma_data_direction sunxi_mmc_get_dma_dir(struct mmc_data *data) 325 { 326 if (data->flags & MMC_DATA_WRITE) 327 return DMA_TO_DEVICE; 328 else 329 return DMA_FROM_DEVICE; 330 } 331 332 static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host, 333 struct mmc_data *data) 334 { 335 u32 i, dma_len; 336 struct scatterlist *sg; 337 338 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 339 sunxi_mmc_get_dma_dir(data)); 340 if (dma_len == 0) { 341 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n"); 342 return -ENOMEM; 343 } 344 345 for_each_sg(data->sg, sg, data->sg_len, i) { 346 if (sg->offset & 3 || sg->length & 3) { 347 dev_err(mmc_dev(host->mmc), 348 "unaligned scatterlist: os %x length %d\n", 349 sg->offset, sg->length); 350 return -EINVAL; 351 } 352 } 353 354 return 0; 355 } 356 357 static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host, 358 struct mmc_data *data) 359 { 360 u32 rval; 361 362 sunxi_mmc_init_idma_des(host, data); 363 364 rval = mmc_readl(host, REG_GCTRL); 365 rval |= SDXC_DMA_ENABLE_BIT; 366 mmc_writel(host, REG_GCTRL, rval); 367 rval |= SDXC_DMA_RESET; 368 mmc_writel(host, REG_GCTRL, rval); 369 370 mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET); 371 372 if (!(data->flags & MMC_DATA_WRITE)) 373 mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT); 374 375 mmc_writel(host, REG_DMAC, 376 SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON); 377 } 378 379 static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host, 380 struct mmc_request *req) 381 { 382 u32 arg, cmd_val, ri; 383 unsigned long expire = jiffies + msecs_to_jiffies(1000); 384 385 cmd_val = SDXC_START | SDXC_RESP_EXPIRE | 386 SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC; 387 388 if (req->cmd->opcode == SD_IO_RW_EXTENDED) { 389 cmd_val |= SD_IO_RW_DIRECT; 390 arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 391 ((req->cmd->arg >> 28) & 0x7); 392 } else { 393 cmd_val |= MMC_STOP_TRANSMISSION; 394 arg = 0; 395 } 396 397 mmc_writel(host, REG_CARG, arg); 398 mmc_writel(host, REG_CMDR, cmd_val); 399 400 do { 401 ri = mmc_readl(host, REG_RINTR); 402 } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) && 403 time_before(jiffies, expire)); 404 405 if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) { 406 dev_err(mmc_dev(host->mmc), "send stop command failed\n"); 407 if (req->stop) 408 req->stop->resp[0] = -ETIMEDOUT; 409 } else { 410 if (req->stop) 411 req->stop->resp[0] = mmc_readl(host, REG_RESP0); 412 } 413 414 mmc_writel(host, REG_RINTR, 0xffff); 415 } 416 417 static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host) 418 { 419 struct mmc_command *cmd = host->mrq->cmd; 420 struct mmc_data *data = host->mrq->data; 421 422 /* For some cmds timeout is normal with sd/mmc cards */ 423 if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) == 424 SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND || 425 cmd->opcode == SD_IO_RW_DIRECT)) 426 return; 427 428 dev_err(mmc_dev(host->mmc), 429 "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n", 430 host->mmc->index, cmd->opcode, 431 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "", 432 host->int_sum & SDXC_RESP_ERROR ? " RE" : "", 433 host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "", 434 host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "", 435 host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "", 436 host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "", 437 host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "", 438 host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "", 439 host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "", 440 host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : "" 441 ); 442 } 443 444 /* Called in interrupt context! */ 445 static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host) 446 { 447 struct mmc_request *mrq = host->mrq; 448 struct mmc_data *data = mrq->data; 449 u32 rval; 450 451 mmc_writel(host, REG_IMASK, host->sdio_imask); 452 mmc_writel(host, REG_IDIE, 0); 453 454 if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) { 455 sunxi_mmc_dump_errinfo(host); 456 mrq->cmd->error = -ETIMEDOUT; 457 458 if (data) { 459 data->error = -ETIMEDOUT; 460 host->manual_stop_mrq = mrq; 461 } 462 463 if (mrq->stop) 464 mrq->stop->error = -ETIMEDOUT; 465 } else { 466 if (mrq->cmd->flags & MMC_RSP_136) { 467 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3); 468 mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2); 469 mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1); 470 mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0); 471 } else { 472 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0); 473 } 474 475 if (data) 476 data->bytes_xfered = data->blocks * data->blksz; 477 } 478 479 if (data) { 480 mmc_writel(host, REG_IDST, 0x337); 481 mmc_writel(host, REG_DMAC, 0); 482 rval = mmc_readl(host, REG_GCTRL); 483 rval |= SDXC_DMA_RESET; 484 mmc_writel(host, REG_GCTRL, rval); 485 rval &= ~SDXC_DMA_ENABLE_BIT; 486 mmc_writel(host, REG_GCTRL, rval); 487 rval |= SDXC_FIFO_RESET; 488 mmc_writel(host, REG_GCTRL, rval); 489 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 490 sunxi_mmc_get_dma_dir(data)); 491 } 492 493 mmc_writel(host, REG_RINTR, 0xffff); 494 495 host->mrq = NULL; 496 host->int_sum = 0; 497 host->wait_dma = false; 498 499 return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED; 500 } 501 502 static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id) 503 { 504 struct sunxi_mmc_host *host = dev_id; 505 struct mmc_request *mrq; 506 u32 msk_int, idma_int; 507 bool finalize = false; 508 bool sdio_int = false; 509 irqreturn_t ret = IRQ_HANDLED; 510 511 spin_lock(&host->lock); 512 513 idma_int = mmc_readl(host, REG_IDST); 514 msk_int = mmc_readl(host, REG_MISTA); 515 516 dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n", 517 host->mrq, msk_int, idma_int); 518 519 mrq = host->mrq; 520 if (mrq) { 521 if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT) 522 host->wait_dma = false; 523 524 host->int_sum |= msk_int; 525 526 /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */ 527 if ((host->int_sum & SDXC_RESP_TIMEOUT) && 528 !(host->int_sum & SDXC_COMMAND_DONE)) 529 mmc_writel(host, REG_IMASK, 530 host->sdio_imask | SDXC_COMMAND_DONE); 531 /* Don't wait for dma on error */ 532 else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) 533 finalize = true; 534 else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) && 535 !host->wait_dma) 536 finalize = true; 537 } 538 539 if (msk_int & SDXC_SDIO_INTERRUPT) 540 sdio_int = true; 541 542 mmc_writel(host, REG_RINTR, msk_int); 543 mmc_writel(host, REG_IDST, idma_int); 544 545 if (finalize) 546 ret = sunxi_mmc_finalize_request(host); 547 548 spin_unlock(&host->lock); 549 550 if (finalize && ret == IRQ_HANDLED) 551 mmc_request_done(host->mmc, mrq); 552 553 if (sdio_int) 554 mmc_signal_sdio_irq(host->mmc); 555 556 return ret; 557 } 558 559 static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id) 560 { 561 struct sunxi_mmc_host *host = dev_id; 562 struct mmc_request *mrq; 563 unsigned long iflags; 564 565 spin_lock_irqsave(&host->lock, iflags); 566 mrq = host->manual_stop_mrq; 567 spin_unlock_irqrestore(&host->lock, iflags); 568 569 if (!mrq) { 570 dev_err(mmc_dev(host->mmc), "no request for manual stop\n"); 571 return IRQ_HANDLED; 572 } 573 574 dev_err(mmc_dev(host->mmc), "data error, sending stop command\n"); 575 576 /* 577 * We will never have more than one outstanding request, 578 * and we do not complete the request until after 579 * we've cleared host->manual_stop_mrq so we do not need to 580 * spin lock this function. 581 * Additionally we have wait states within this function 582 * so having it in a lock is a very bad idea. 583 */ 584 sunxi_mmc_send_manual_stop(host, mrq); 585 586 spin_lock_irqsave(&host->lock, iflags); 587 host->manual_stop_mrq = NULL; 588 spin_unlock_irqrestore(&host->lock, iflags); 589 590 mmc_request_done(host->mmc, mrq); 591 592 return IRQ_HANDLED; 593 } 594 595 static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en) 596 { 597 unsigned long expire = jiffies + msecs_to_jiffies(250); 598 u32 rval; 599 600 rval = mmc_readl(host, REG_CLKCR); 601 rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON); 602 603 if (oclk_en) 604 rval |= SDXC_CARD_CLOCK_ON; 605 606 mmc_writel(host, REG_CLKCR, rval); 607 608 rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER; 609 mmc_writel(host, REG_CMDR, rval); 610 611 do { 612 rval = mmc_readl(host, REG_CMDR); 613 } while (time_before(jiffies, expire) && (rval & SDXC_START)); 614 615 /* clear irq status bits set by the command */ 616 mmc_writel(host, REG_RINTR, 617 mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT); 618 619 if (rval & SDXC_START) { 620 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n"); 621 return -EIO; 622 } 623 624 return 0; 625 } 626 627 static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, 628 struct mmc_ios *ios) 629 { 630 u32 rate, oclk_dly, rval, sclk_dly; 631 int ret; 632 633 rate = clk_round_rate(host->clk_mmc, ios->clock); 634 dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %d\n", 635 ios->clock, rate); 636 637 /* setting clock rate */ 638 ret = clk_set_rate(host->clk_mmc, rate); 639 if (ret) { 640 dev_err(mmc_dev(host->mmc), "error setting clk to %d: %d\n", 641 rate, ret); 642 return ret; 643 } 644 645 ret = sunxi_mmc_oclk_onoff(host, 0); 646 if (ret) 647 return ret; 648 649 /* clear internal divider */ 650 rval = mmc_readl(host, REG_CLKCR); 651 rval &= ~0xff; 652 mmc_writel(host, REG_CLKCR, rval); 653 654 /* determine delays */ 655 if (rate <= 400000) { 656 oclk_dly = 0; 657 sclk_dly = 7; 658 } else if (rate <= 25000000) { 659 oclk_dly = 0; 660 sclk_dly = 5; 661 } else if (rate <= 50000000) { 662 if (ios->timing == MMC_TIMING_UHS_DDR50) { 663 oclk_dly = 2; 664 sclk_dly = 4; 665 } else { 666 oclk_dly = 3; 667 sclk_dly = 5; 668 } 669 } else { 670 /* rate > 50000000 */ 671 oclk_dly = 2; 672 sclk_dly = 4; 673 } 674 675 clk_sunxi_mmc_phase_control(host->clk_mmc, sclk_dly, oclk_dly); 676 677 return sunxi_mmc_oclk_onoff(host, 1); 678 } 679 680 static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 681 { 682 struct sunxi_mmc_host *host = mmc_priv(mmc); 683 u32 rval; 684 685 /* Set the power state */ 686 switch (ios->power_mode) { 687 case MMC_POWER_ON: 688 break; 689 690 case MMC_POWER_UP: 691 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 692 693 host->ferror = sunxi_mmc_init_host(mmc); 694 if (host->ferror) 695 return; 696 697 dev_dbg(mmc_dev(mmc), "power on!\n"); 698 break; 699 700 case MMC_POWER_OFF: 701 dev_dbg(mmc_dev(mmc), "power off!\n"); 702 sunxi_mmc_reset_host(host); 703 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 704 break; 705 } 706 707 /* set bus width */ 708 switch (ios->bus_width) { 709 case MMC_BUS_WIDTH_1: 710 mmc_writel(host, REG_WIDTH, SDXC_WIDTH1); 711 break; 712 case MMC_BUS_WIDTH_4: 713 mmc_writel(host, REG_WIDTH, SDXC_WIDTH4); 714 break; 715 case MMC_BUS_WIDTH_8: 716 mmc_writel(host, REG_WIDTH, SDXC_WIDTH8); 717 break; 718 } 719 720 /* set ddr mode */ 721 rval = mmc_readl(host, REG_GCTRL); 722 if (ios->timing == MMC_TIMING_UHS_DDR50) 723 rval |= SDXC_DDR_MODE; 724 else 725 rval &= ~SDXC_DDR_MODE; 726 mmc_writel(host, REG_GCTRL, rval); 727 728 /* set up clock */ 729 if (ios->clock && ios->power_mode) { 730 host->ferror = sunxi_mmc_clk_set_rate(host, ios); 731 /* Android code had a usleep_range(50000, 55000); here */ 732 } 733 } 734 735 static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 736 { 737 struct sunxi_mmc_host *host = mmc_priv(mmc); 738 unsigned long flags; 739 u32 imask; 740 741 spin_lock_irqsave(&host->lock, flags); 742 743 imask = mmc_readl(host, REG_IMASK); 744 if (enable) { 745 host->sdio_imask = SDXC_SDIO_INTERRUPT; 746 imask |= SDXC_SDIO_INTERRUPT; 747 } else { 748 host->sdio_imask = 0; 749 imask &= ~SDXC_SDIO_INTERRUPT; 750 } 751 mmc_writel(host, REG_IMASK, imask); 752 spin_unlock_irqrestore(&host->lock, flags); 753 } 754 755 static void sunxi_mmc_hw_reset(struct mmc_host *mmc) 756 { 757 struct sunxi_mmc_host *host = mmc_priv(mmc); 758 mmc_writel(host, REG_HWRST, 0); 759 udelay(10); 760 mmc_writel(host, REG_HWRST, 1); 761 udelay(300); 762 } 763 764 static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 765 { 766 struct sunxi_mmc_host *host = mmc_priv(mmc); 767 struct mmc_command *cmd = mrq->cmd; 768 struct mmc_data *data = mrq->data; 769 unsigned long iflags; 770 u32 imask = SDXC_INTERRUPT_ERROR_BIT; 771 u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f); 772 bool wait_dma = host->wait_dma; 773 int ret; 774 775 /* Check for set_ios errors (should never happen) */ 776 if (host->ferror) { 777 mrq->cmd->error = host->ferror; 778 mmc_request_done(mmc, mrq); 779 return; 780 } 781 782 if (data) { 783 ret = sunxi_mmc_map_dma(host, data); 784 if (ret < 0) { 785 dev_err(mmc_dev(mmc), "map DMA failed\n"); 786 cmd->error = ret; 787 data->error = ret; 788 mmc_request_done(mmc, mrq); 789 return; 790 } 791 } 792 793 if (cmd->opcode == MMC_GO_IDLE_STATE) { 794 cmd_val |= SDXC_SEND_INIT_SEQUENCE; 795 imask |= SDXC_COMMAND_DONE; 796 } 797 798 if (cmd->flags & MMC_RSP_PRESENT) { 799 cmd_val |= SDXC_RESP_EXPIRE; 800 if (cmd->flags & MMC_RSP_136) 801 cmd_val |= SDXC_LONG_RESPONSE; 802 if (cmd->flags & MMC_RSP_CRC) 803 cmd_val |= SDXC_CHECK_RESPONSE_CRC; 804 805 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) { 806 cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER; 807 if (cmd->data->flags & MMC_DATA_STREAM) { 808 imask |= SDXC_AUTO_COMMAND_DONE; 809 cmd_val |= SDXC_SEQUENCE_MODE | 810 SDXC_SEND_AUTO_STOP; 811 } 812 813 if (cmd->data->stop) { 814 imask |= SDXC_AUTO_COMMAND_DONE; 815 cmd_val |= SDXC_SEND_AUTO_STOP; 816 } else { 817 imask |= SDXC_DATA_OVER; 818 } 819 820 if (cmd->data->flags & MMC_DATA_WRITE) 821 cmd_val |= SDXC_WRITE; 822 else 823 wait_dma = true; 824 } else { 825 imask |= SDXC_COMMAND_DONE; 826 } 827 } else { 828 imask |= SDXC_COMMAND_DONE; 829 } 830 831 dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n", 832 cmd_val & 0x3f, cmd_val, cmd->arg, imask, 833 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0); 834 835 spin_lock_irqsave(&host->lock, iflags); 836 837 if (host->mrq || host->manual_stop_mrq) { 838 spin_unlock_irqrestore(&host->lock, iflags); 839 840 if (data) 841 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, 842 sunxi_mmc_get_dma_dir(data)); 843 844 dev_err(mmc_dev(mmc), "request already pending\n"); 845 mrq->cmd->error = -EBUSY; 846 mmc_request_done(mmc, mrq); 847 return; 848 } 849 850 if (data) { 851 mmc_writel(host, REG_BLKSZ, data->blksz); 852 mmc_writel(host, REG_BCNTR, data->blksz * data->blocks); 853 sunxi_mmc_start_dma(host, data); 854 } 855 856 host->mrq = mrq; 857 host->wait_dma = wait_dma; 858 mmc_writel(host, REG_IMASK, host->sdio_imask | imask); 859 mmc_writel(host, REG_CARG, cmd->arg); 860 mmc_writel(host, REG_CMDR, cmd_val); 861 862 spin_unlock_irqrestore(&host->lock, iflags); 863 } 864 865 static const struct of_device_id sunxi_mmc_of_match[] = { 866 { .compatible = "allwinner,sun4i-a10-mmc", }, 867 { .compatible = "allwinner,sun5i-a13-mmc", }, 868 { /* sentinel */ } 869 }; 870 MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match); 871 872 static struct mmc_host_ops sunxi_mmc_ops = { 873 .request = sunxi_mmc_request, 874 .set_ios = sunxi_mmc_set_ios, 875 .get_ro = mmc_gpio_get_ro, 876 .get_cd = mmc_gpio_get_cd, 877 .enable_sdio_irq = sunxi_mmc_enable_sdio_irq, 878 .hw_reset = sunxi_mmc_hw_reset, 879 }; 880 881 static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host, 882 struct platform_device *pdev) 883 { 884 struct device_node *np = pdev->dev.of_node; 885 int ret; 886 887 if (of_device_is_compatible(np, "allwinner,sun4i-a10-mmc")) 888 host->idma_des_size_bits = 13; 889 else 890 host->idma_des_size_bits = 16; 891 892 ret = mmc_regulator_get_supply(host->mmc); 893 if (ret) { 894 if (ret != -EPROBE_DEFER) 895 dev_err(&pdev->dev, "Could not get vmmc supply\n"); 896 return ret; 897 } 898 899 host->reg_base = devm_ioremap_resource(&pdev->dev, 900 platform_get_resource(pdev, IORESOURCE_MEM, 0)); 901 if (IS_ERR(host->reg_base)) 902 return PTR_ERR(host->reg_base); 903 904 host->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 905 if (IS_ERR(host->clk_ahb)) { 906 dev_err(&pdev->dev, "Could not get ahb clock\n"); 907 return PTR_ERR(host->clk_ahb); 908 } 909 910 host->clk_mmc = devm_clk_get(&pdev->dev, "mmc"); 911 if (IS_ERR(host->clk_mmc)) { 912 dev_err(&pdev->dev, "Could not get mmc clock\n"); 913 return PTR_ERR(host->clk_mmc); 914 } 915 916 host->reset = devm_reset_control_get(&pdev->dev, "ahb"); 917 918 ret = clk_prepare_enable(host->clk_ahb); 919 if (ret) { 920 dev_err(&pdev->dev, "Enable ahb clk err %d\n", ret); 921 return ret; 922 } 923 924 ret = clk_prepare_enable(host->clk_mmc); 925 if (ret) { 926 dev_err(&pdev->dev, "Enable mmc clk err %d\n", ret); 927 goto error_disable_clk_ahb; 928 } 929 930 if (!IS_ERR(host->reset)) { 931 ret = reset_control_deassert(host->reset); 932 if (ret) { 933 dev_err(&pdev->dev, "reset err %d\n", ret); 934 goto error_disable_clk_mmc; 935 } 936 } 937 938 /* 939 * Sometimes the controller asserts the irq on boot for some reason, 940 * make sure the controller is in a sane state before enabling irqs. 941 */ 942 ret = sunxi_mmc_reset_host(host); 943 if (ret) 944 goto error_assert_reset; 945 946 host->irq = platform_get_irq(pdev, 0); 947 return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq, 948 sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host); 949 950 error_assert_reset: 951 if (!IS_ERR(host->reset)) 952 reset_control_assert(host->reset); 953 error_disable_clk_mmc: 954 clk_disable_unprepare(host->clk_mmc); 955 error_disable_clk_ahb: 956 clk_disable_unprepare(host->clk_ahb); 957 return ret; 958 } 959 960 static int sunxi_mmc_probe(struct platform_device *pdev) 961 { 962 struct sunxi_mmc_host *host; 963 struct mmc_host *mmc; 964 int ret; 965 966 mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev); 967 if (!mmc) { 968 dev_err(&pdev->dev, "mmc alloc host failed\n"); 969 return -ENOMEM; 970 } 971 972 host = mmc_priv(mmc); 973 host->mmc = mmc; 974 spin_lock_init(&host->lock); 975 976 ret = sunxi_mmc_resource_request(host, pdev); 977 if (ret) 978 goto error_free_host; 979 980 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 981 &host->sg_dma, GFP_KERNEL); 982 if (!host->sg_cpu) { 983 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n"); 984 ret = -ENOMEM; 985 goto error_free_host; 986 } 987 988 mmc->ops = &sunxi_mmc_ops; 989 mmc->max_blk_count = 8192; 990 mmc->max_blk_size = 4096; 991 mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des); 992 mmc->max_seg_size = (1 << host->idma_des_size_bits); 993 mmc->max_req_size = mmc->max_seg_size * mmc->max_segs; 994 /* 400kHz ~ 50MHz */ 995 mmc->f_min = 400000; 996 mmc->f_max = 50000000; 997 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 998 MMC_CAP_ERASE; 999 1000 ret = mmc_of_parse(mmc); 1001 if (ret) 1002 goto error_free_dma; 1003 1004 ret = mmc_add_host(mmc); 1005 if (ret) 1006 goto error_free_dma; 1007 1008 dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq); 1009 platform_set_drvdata(pdev, mmc); 1010 return 0; 1011 1012 error_free_dma: 1013 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 1014 error_free_host: 1015 mmc_free_host(mmc); 1016 return ret; 1017 } 1018 1019 static int sunxi_mmc_remove(struct platform_device *pdev) 1020 { 1021 struct mmc_host *mmc = platform_get_drvdata(pdev); 1022 struct sunxi_mmc_host *host = mmc_priv(mmc); 1023 1024 mmc_remove_host(mmc); 1025 disable_irq(host->irq); 1026 sunxi_mmc_reset_host(host); 1027 1028 if (!IS_ERR(host->reset)) 1029 reset_control_assert(host->reset); 1030 1031 clk_disable_unprepare(host->clk_mmc); 1032 clk_disable_unprepare(host->clk_ahb); 1033 1034 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 1035 mmc_free_host(mmc); 1036 1037 return 0; 1038 } 1039 1040 static struct platform_driver sunxi_mmc_driver = { 1041 .driver = { 1042 .name = "sunxi-mmc", 1043 .of_match_table = of_match_ptr(sunxi_mmc_of_match), 1044 }, 1045 .probe = sunxi_mmc_probe, 1046 .remove = sunxi_mmc_remove, 1047 }; 1048 module_platform_driver(sunxi_mmc_driver); 1049 1050 MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver"); 1051 MODULE_LICENSE("GPL v2"); 1052 MODULE_AUTHOR("David Lanzend�rfer <david.lanzendoerfer@o2s.ch>"); 1053 MODULE_ALIAS("platform:sunxi-mmc"); 1054