| #
c038e409 |
| 04-May-2022 |
Yifeng Zhao <yifeng.zhao@rock-chips.com> |
mmc: sdhci-of-dwcmshc: add reset call back for rockchip Socs
[ Upstream commit 70f832206fe72e9998b46363e8e59e89b0b757bc ]
The reset function build in the SDHCI will not reset the logic
circuit rela
mmc: sdhci-of-dwcmshc: add reset call back for rockchip Socs
[ Upstream commit 70f832206fe72e9998b46363e8e59e89b0b757bc ]
The reset function build in the SDHCI will not reset the logic
circuit related to the tuning function, which may cause data
reading errors. Resetting the complete SDHCI controller through
the reset controller fixes the issue.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
[rebase, use optional variant of reset getter]
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20220504213251.264819-10-sebastian.reichel@collabora.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
|
| #
71beead9 |
| 09-Aug-2022 |
Liming Sun <limings@nvidia.com> |
mmc: sdhci-of-dwcmshc: Re-enable support for the BlueField-3 SoC
[ Upstream commit a0753ef66c34c1739580219dca664eda648164b7 ]
The commit 08f3dff799d4 (mmc: sdhci-of-dwcmshc: add rockchip platform
s
mmc: sdhci-of-dwcmshc: Re-enable support for the BlueField-3 SoC
[ Upstream commit a0753ef66c34c1739580219dca664eda648164b7 ]
The commit 08f3dff799d4 (mmc: sdhci-of-dwcmshc: add rockchip platform
support") introduces the use of_device_get_match_data() to check for some
chips. Unfortunately, it also breaks the BlueField-3 FW, which uses ACPI.
To fix the problem, let's add the ACPI match data and the corresponding
quirks to re-enable the support for the BlueField-3 SoC.
Reviewed-by: David Woods <davwoods@nvidia.com>
Signed-off-by: Liming Sun <limings@nvidia.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Fixes: 08f3dff799d4 ("mmc: sdhci-of-dwcmshc: add rockchip platform support")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20220809173742.178440-1-limings@nvidia.com
[Ulf: Clarified the commit message a bit]
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
|
| #
68b6cbaa |
| 04-May-2022 |
Sebastian Reichel <sebastian.reichel@collabora.com> |
mmc: sdhci-of-dwcmshc: rename rk3568 to rk35xx
[ Upstream commit 86e1a8e1f9b555af342c53ae06284eeeab9a4263 ]
Prepare driver for rk3588 support by renaming the internal data
structures.
Acked-by: Ad
mmc: sdhci-of-dwcmshc: rename rk3568 to rk35xx
[ Upstream commit 86e1a8e1f9b555af342c53ae06284eeeab9a4263 ]
Prepare driver for rk3588 support by renaming the internal data
structures.
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20220504213251.264819-11-sebastian.reichel@collabora.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
|
| #
c038e409 |
| 04-May-2022 |
Yifeng Zhao <yifeng.zhao@rock-chips.com> |
mmc: sdhci-of-dwcmshc: add reset call back for rockchip Socs
[ Upstream commit 70f832206fe72e9998b46363e8e59e89b0b757bc ]
The reset function build in the SDHCI will not reset the logic
circuit rela
mmc: sdhci-of-dwcmshc: add reset call back for rockchip Socs
[ Upstream commit 70f832206fe72e9998b46363e8e59e89b0b757bc ]
The reset function build in the SDHCI will not reset the logic
circuit related to the tuning function, which may cause data
reading errors. Resetting the complete SDHCI controller through
the reset controller fixes the issue.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
[rebase, use optional variant of reset getter]
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20220504213251.264819-10-sebastian.reichel@collabora.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
|
| #
71beead9 |
| 09-Aug-2022 |
Liming Sun <limings@nvidia.com> |
mmc: sdhci-of-dwcmshc: Re-enable support for the BlueField-3 SoC
[ Upstream commit a0753ef66c34c1739580219dca664eda648164b7 ]
The commit 08f3dff799d4 (mmc: sdhci-of-dwcmshc: add rockchip platform
s
mmc: sdhci-of-dwcmshc: Re-enable support for the BlueField-3 SoC
[ Upstream commit a0753ef66c34c1739580219dca664eda648164b7 ]
The commit 08f3dff799d4 (mmc: sdhci-of-dwcmshc: add rockchip platform
support") introduces the use of_device_get_match_data() to check for some
chips. Unfortunately, it also breaks the BlueField-3 FW, which uses ACPI.
To fix the problem, let's add the ACPI match data and the corresponding
quirks to re-enable the support for the BlueField-3 SoC.
Reviewed-by: David Woods <davwoods@nvidia.com>
Signed-off-by: Liming Sun <limings@nvidia.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Fixes: 08f3dff799d4 ("mmc: sdhci-of-dwcmshc: add rockchip platform support")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20220809173742.178440-1-limings@nvidia.com
[Ulf: Clarified the commit message a bit]
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
|
| #
68b6cbaa |
| 04-May-2022 |
Sebastian Reichel <sebastian.reichel@collabora.com> |
mmc: sdhci-of-dwcmshc: rename rk3568 to rk35xx
[ Upstream commit 86e1a8e1f9b555af342c53ae06284eeeab9a4263 ]
Prepare driver for rk3588 support by renaming the internal data
structures.
Acked-by: Ad
mmc: sdhci-of-dwcmshc: rename rk3568 to rk35xx
[ Upstream commit 86e1a8e1f9b555af342c53ae06284eeeab9a4263 ]
Prepare driver for rk3588 support by renaming the internal data
structures.
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20220504213251.264819-11-sebastian.reichel@collabora.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
|
| #
c038e409 |
| 04-May-2022 |
Yifeng Zhao <yifeng.zhao@rock-chips.com> |
mmc: sdhci-of-dwcmshc: add reset call back for rockchip Socs
[ Upstream commit 70f832206fe72e9998b46363e8e59e89b0b757bc ]
The reset function build in the SDHCI will not reset the logic
circuit rela
mmc: sdhci-of-dwcmshc: add reset call back for rockchip Socs
[ Upstream commit 70f832206fe72e9998b46363e8e59e89b0b757bc ]
The reset function build in the SDHCI will not reset the logic
circuit related to the tuning function, which may cause data
reading errors. Resetting the complete SDHCI controller through
the reset controller fixes the issue.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
[rebase, use optional variant of reset getter]
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20220504213251.264819-10-sebastian.reichel@collabora.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
|
| #
71beead9 |
| 09-Aug-2022 |
Liming Sun <limings@nvidia.com> |
mmc: sdhci-of-dwcmshc: Re-enable support for the BlueField-3 SoC
[ Upstream commit a0753ef66c34c1739580219dca664eda648164b7 ]
The commit 08f3dff799d4 (mmc: sdhci-of-dwcmshc: add rockchip platform
s
mmc: sdhci-of-dwcmshc: Re-enable support for the BlueField-3 SoC
[ Upstream commit a0753ef66c34c1739580219dca664eda648164b7 ]
The commit 08f3dff799d4 (mmc: sdhci-of-dwcmshc: add rockchip platform
support") introduces the use of_device_get_match_data() to check for some
chips. Unfortunately, it also breaks the BlueField-3 FW, which uses ACPI.
To fix the problem, let's add the ACPI match data and the corresponding
quirks to re-enable the support for the BlueField-3 SoC.
Reviewed-by: David Woods <davwoods@nvidia.com>
Signed-off-by: Liming Sun <limings@nvidia.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Fixes: 08f3dff799d4 ("mmc: sdhci-of-dwcmshc: add rockchip platform support")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20220809173742.178440-1-limings@nvidia.com
[Ulf: Clarified the commit message a bit]
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
|
| #
68b6cbaa |
| 04-May-2022 |
Sebastian Reichel <sebastian.reichel@collabora.com> |
mmc: sdhci-of-dwcmshc: rename rk3568 to rk35xx
[ Upstream commit 86e1a8e1f9b555af342c53ae06284eeeab9a4263 ]
Prepare driver for rk3588 support by renaming the internal data
structures.
Acked-by: Ad
mmc: sdhci-of-dwcmshc: rename rk3568 to rk35xx
[ Upstream commit 86e1a8e1f9b555af342c53ae06284eeeab9a4263 ]
Prepare driver for rk3588 support by renaming the internal data
structures.
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20220504213251.264819-11-sebastian.reichel@collabora.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
|
| #
c038e409 |
| 04-May-2022 |
Yifeng Zhao <yifeng.zhao@rock-chips.com> |
mmc: sdhci-of-dwcmshc: add reset call back for rockchip Socs
[ Upstream commit 70f832206fe72e9998b46363e8e59e89b0b757bc ]
The reset function build in the SDHCI will not reset the logic
circuit rela
mmc: sdhci-of-dwcmshc: add reset call back for rockchip Socs
[ Upstream commit 70f832206fe72e9998b46363e8e59e89b0b757bc ]
The reset function build in the SDHCI will not reset the logic
circuit related to the tuning function, which may cause data
reading errors. Resetting the complete SDHCI controller through
the reset controller fixes the issue.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
[rebase, use optional variant of reset getter]
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20220504213251.264819-10-sebastian.reichel@collabora.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
|
| #
71beead9 |
| 09-Aug-2022 |
Liming Sun <limings@nvidia.com> |
mmc: sdhci-of-dwcmshc: Re-enable support for the BlueField-3 SoC
[ Upstream commit a0753ef66c34c1739580219dca664eda648164b7 ]
The commit 08f3dff799d4 (mmc: sdhci-of-dwcmshc: add rockchip platform
s
mmc: sdhci-of-dwcmshc: Re-enable support for the BlueField-3 SoC
[ Upstream commit a0753ef66c34c1739580219dca664eda648164b7 ]
The commit 08f3dff799d4 (mmc: sdhci-of-dwcmshc: add rockchip platform
support") introduces the use of_device_get_match_data() to check for some
chips. Unfortunately, it also breaks the BlueField-3 FW, which uses ACPI.
To fix the problem, let's add the ACPI match data and the corresponding
quirks to re-enable the support for the BlueField-3 SoC.
Reviewed-by: David Woods <davwoods@nvidia.com>
Signed-off-by: Liming Sun <limings@nvidia.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Fixes: 08f3dff799d4 ("mmc: sdhci-of-dwcmshc: add rockchip platform support")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20220809173742.178440-1-limings@nvidia.com
[Ulf: Clarified the commit message a bit]
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
|
| #
68b6cbaa |
| 04-May-2022 |
Sebastian Reichel <sebastian.reichel@collabora.com> |
mmc: sdhci-of-dwcmshc: rename rk3568 to rk35xx
[ Upstream commit 86e1a8e1f9b555af342c53ae06284eeeab9a4263 ]
Prepare driver for rk3588 support by renaming the internal data
structures.
Acked-by: Ad
mmc: sdhci-of-dwcmshc: rename rk3568 to rk35xx
[ Upstream commit 86e1a8e1f9b555af342c53ae06284eeeab9a4263 ]
Prepare driver for rk3588 support by renaming the internal data
structures.
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20220504213251.264819-11-sebastian.reichel@collabora.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
|
| #
c038e409 |
| 04-May-2022 |
Yifeng Zhao <yifeng.zhao@rock-chips.com> |
mmc: sdhci-of-dwcmshc: add reset call back for rockchip Socs
[ Upstream commit 70f832206fe72e9998b46363e8e59e89b0b757bc ]
The reset function build in the SDHCI will not reset the logic
circuit rela
mmc: sdhci-of-dwcmshc: add reset call back for rockchip Socs
[ Upstream commit 70f832206fe72e9998b46363e8e59e89b0b757bc ]
The reset function build in the SDHCI will not reset the logic
circuit related to the tuning function, which may cause data
reading errors. Resetting the complete SDHCI controller through
the reset controller fixes the issue.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
[rebase, use optional variant of reset getter]
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20220504213251.264819-10-sebastian.reichel@collabora.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
|
| #
71beead9 |
| 09-Aug-2022 |
Liming Sun <limings@nvidia.com> |
mmc: sdhci-of-dwcmshc: Re-enable support for the BlueField-3 SoC
[ Upstream commit a0753ef66c34c1739580219dca664eda648164b7 ]
The commit 08f3dff799d4 (mmc: sdhci-of-dwcmshc: add rockchip platform
s
mmc: sdhci-of-dwcmshc: Re-enable support for the BlueField-3 SoC
[ Upstream commit a0753ef66c34c1739580219dca664eda648164b7 ]
The commit 08f3dff799d4 (mmc: sdhci-of-dwcmshc: add rockchip platform
support") introduces the use of_device_get_match_data() to check for some
chips. Unfortunately, it also breaks the BlueField-3 FW, which uses ACPI.
To fix the problem, let's add the ACPI match data and the corresponding
quirks to re-enable the support for the BlueField-3 SoC.
Reviewed-by: David Woods <davwoods@nvidia.com>
Signed-off-by: Liming Sun <limings@nvidia.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Fixes: 08f3dff799d4 ("mmc: sdhci-of-dwcmshc: add rockchip platform support")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20220809173742.178440-1-limings@nvidia.com
[Ulf: Clarified the commit message a bit]
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
|
| #
68b6cbaa |
| 04-May-2022 |
Sebastian Reichel <sebastian.reichel@collabora.com> |
mmc: sdhci-of-dwcmshc: rename rk3568 to rk35xx
[ Upstream commit 86e1a8e1f9b555af342c53ae06284eeeab9a4263 ]
Prepare driver for rk3588 support by renaming the internal data
structures.
Acked-by: Ad
mmc: sdhci-of-dwcmshc: rename rk3568 to rk35xx
[ Upstream commit 86e1a8e1f9b555af342c53ae06284eeeab9a4263 ]
Prepare driver for rk3588 support by renaming the internal data
structures.
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20220504213251.264819-11-sebastian.reichel@collabora.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
|
| #
c038e409 |
| 04-May-2022 |
Yifeng Zhao <yifeng.zhao@rock-chips.com> |
mmc: sdhci-of-dwcmshc: add reset call back for rockchip Socs
[ Upstream commit 70f832206fe72e9998b46363e8e59e89b0b757bc ]
The reset function build in the SDHCI will not reset the logic
circuit rela
mmc: sdhci-of-dwcmshc: add reset call back for rockchip Socs
[ Upstream commit 70f832206fe72e9998b46363e8e59e89b0b757bc ]
The reset function build in the SDHCI will not reset the logic
circuit related to the tuning function, which may cause data
reading errors. Resetting the complete SDHCI controller through
the reset controller fixes the issue.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
[rebase, use optional variant of reset getter]
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20220504213251.264819-10-sebastian.reichel@collabora.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
|
|
Revision tags: v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26 |
|
| #
57ac3084 |
| 24-Mar-2021 |
Jisheng Zhang <Jisheng.Zhang@synaptics.com> |
mmc: sdhci-of-dwcmshc: set MMC_CAP_WAIT_WHILE_BUSY
The host supports HW busy detection of the device busy signaling over
dat0 line. Set MMC_CAP_wAIT_WHILE_BUSY host capability.
Signed-off-by: Jishe
mmc: sdhci-of-dwcmshc: set MMC_CAP_WAIT_WHILE_BUSY
The host supports HW busy detection of the device busy signaling over
dat0 line. Set MMC_CAP_wAIT_WHILE_BUSY host capability.
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Link: https://lore.kernel.org/r/20210324154703.69f97fde@xhacker.debian
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
show more ...
|
| #
34884c4f |
| 23-Mar-2021 |
Wei Yongjun <weiyongjun1@huawei.com> |
mmc: sdhci-of-dwcmshc: fix error return code in dwcmshc_probe()
Fix to return negative error code -ENOMEM from the error handling
case instead of 0, as done elsewhere in this function.
Fixes: c2c4d
mmc: sdhci-of-dwcmshc: fix error return code in dwcmshc_probe()
Fix to return negative error code -ENOMEM from the error handling
case instead of 0, as done elsewhere in this function.
Fixes: c2c4da37837e ("mmc: sdhci-of-dwcmshc: add rockchip platform support")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Link: https://lore.kernel.org/r/20210323112956.1016884-1-weiyongjun1@huawei.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
show more ...
|
| #
eb81ed51 |
| 22-Mar-2021 |
Liming Sun <limings@nvidia.com> |
mmc: sdhci-of-dwcmshc: add ACPI support for BlueField-3 SoC
This commit adds ACPI support in the sdhci-of-dwcmshc driver for
BlueField-3 SoC. It has changes to only use the clock hierarchy
for Devie
mmc: sdhci-of-dwcmshc: add ACPI support for BlueField-3 SoC
This commit adds ACPI support in the sdhci-of-dwcmshc driver for
BlueField-3 SoC. It has changes to only use the clock hierarchy
for Deviec Tree since the clk is not supported by ACPI. Instead,
ACPI can define 'clock-frequency' which is parsed by existing
sdhci_get_property(). This clock value will be returned in function
dwcmshc_get_max_clock().
Signed-off-by: Liming Sun <limings@nvidia.com>
Reviewed-by: Khalil Blaiech <kblaiech@nvidia.com>
Link: https://lore.kernel.org/r/1616453211-275165-1-git-send-email-limings@nvidia.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v5.10.25, v5.10.24 |
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08f3dff7 |
| 16-Mar-2021 |
Shawn Lin <shawn.lin@rock-chips.com> |
mmc: sdhci-of-dwcmshc: add rockchip platform support
sdhci based synopsys MMC IP is also used on some rockchip platforms,
so add a basic support here.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips
mmc: sdhci-of-dwcmshc: add rockchip platform support
sdhci based synopsys MMC IP is also used on some rockchip platforms,
so add a basic support here.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Link: https://lore.kernel.org/r/1615879102-45919-3-git-send-email-shawn.lin@rock-chips.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14, v5.10 |
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| #
5f7dfda4 |
| 10-Dec-2020 |
Jisheng Zhang <Jisheng.Zhang@synaptics.com> |
mmc: sdhci-of-dwcmshc: set SDHCI_QUIRK2_PRESET_VALUE_BROKEN
The SDHCI_PRESET_FOR_* registers are not set(all read as zeros), so
set the quirk.
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.
mmc: sdhci-of-dwcmshc: set SDHCI_QUIRK2_PRESET_VALUE_BROKEN
The SDHCI_PRESET_FOR_* registers are not set(all read as zeros), so
set the quirk.
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Link: https://lore.kernel.org/r/20201210165510.76b917e5@xhacker.debian
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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ca1219c0 |
| 29-Dec-2020 |
Jisheng Zhang <Jisheng.Zhang@synaptics.com> |
mmc: sdhci-of-dwcmshc: fix rpmb access
Commit a44f7cb93732 ("mmc: core: use mrq->sbc when sending CMD23 for
RPMB") began to use ACMD23 for RPMB if the host supports ACMD23. In
RPMB ACM23 case, we ne
mmc: sdhci-of-dwcmshc: fix rpmb access
Commit a44f7cb93732 ("mmc: core: use mrq->sbc when sending CMD23 for
RPMB") began to use ACMD23 for RPMB if the host supports ACMD23. In
RPMB ACM23 case, we need to set bit 31 to CMD23 argument, otherwise
RPMB write operation will return general fail.
However, no matter V4 is enabled or not, the dwcmshc's ARGUMENT2
register is 32-bit block count register which doesn't support stuff
bits of CMD23 argument. So let's handle this specific ACMD23 case.
From another side, this patch also prepare for future v4 enabling
for dwcmshc, because from the 4.10 spec, the ARGUMENT2 register is
redefined as 32bit block count which doesn't support stuff bits of
CMD23 argument.
Fixes: a44f7cb93732 ("mmc: core: use mrq->sbc when sending CMD23 for RPMB")
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20201229161625.38255233@xhacker.debian
Cc: stable@vger.kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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| #
5b652628 |
| 10-Dec-2020 |
Jisheng Zhang <Jisheng.Zhang@synaptics.com> |
mmc: sdhci-of-dwcmshc: set SDHCI_QUIRK2_PRESET_VALUE_BROKEN
[ Upstream commit 5f7dfda4f2cec580c135fd81d96a05006651c128 ]
The SDHCI_PRESET_FOR_* registers are not set(all read as zeros), so
set the
mmc: sdhci-of-dwcmshc: set SDHCI_QUIRK2_PRESET_VALUE_BROKEN
[ Upstream commit 5f7dfda4f2cec580c135fd81d96a05006651c128 ]
The SDHCI_PRESET_FOR_* registers are not set(all read as zeros), so
set the quirk.
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Link: https://lore.kernel.org/r/20201210165510.76b917e5@xhacker.debian
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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| #
728d8ab4 |
| 29-Dec-2020 |
Jisheng Zhang <Jisheng.Zhang@synaptics.com> |
mmc: sdhci-of-dwcmshc: fix rpmb access
commit ca1219c0a7432272324660fc9f61a9940f90c50b upstream.
Commit a44f7cb93732 ("mmc: core: use mrq->sbc when sending CMD23 for
RPMB") began to use ACMD23 for
mmc: sdhci-of-dwcmshc: fix rpmb access
commit ca1219c0a7432272324660fc9f61a9940f90c50b upstream.
Commit a44f7cb93732 ("mmc: core: use mrq->sbc when sending CMD23 for
RPMB") began to use ACMD23 for RPMB if the host supports ACMD23. In
RPMB ACM23 case, we need to set bit 31 to CMD23 argument, otherwise
RPMB write operation will return general fail.
However, no matter V4 is enabled or not, the dwcmshc's ARGUMENT2
register is 32-bit block count register which doesn't support stuff
bits of CMD23 argument. So let's handle this specific ACMD23 case.
From another side, this patch also prepare for future v4 enabling
for dwcmshc, because from the 4.10 spec, the ARGUMENT2 register is
redefined as 32bit block count which doesn't support stuff bits of
CMD23 argument.
Fixes: a44f7cb93732 ("mmc: core: use mrq->sbc when sending CMD23 for RPMB")
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20201229161625.38255233@xhacker.debian
Cc: stable@vger.kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Revision tags: v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7 |
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| #
a1a48919 |
| 03-Sep-2020 |
Douglas Anderson <dianders@chromium.org> |
mmc: Set PROBE_PREFER_ASYNCHRONOUS for drivers that existed in v4.19
This is like commit 3d3451124f3d ("mmc: sdhci-msm: Prefer asynchronous
probe") but applied to a whole pile of drivers. This batc
mmc: Set PROBE_PREFER_ASYNCHRONOUS for drivers that existed in v4.19
This is like commit 3d3451124f3d ("mmc: sdhci-msm: Prefer asynchronous
probe") but applied to a whole pile of drivers. This batch converts
the drivers that appeared to be around in the v4.19 timeframe.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200903162412.4.I84eb3e0a738635d524c90d1a688087bc295f7c32@changeid
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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