mfd: wm5102: Update to use maple tree register cache

The maple tree register cache is based on a much more modern data structure
than the rbtree cache and makes optimisation choices which are probab

mfd: wm5102: Update to use maple tree register cache

The maple tree register cache is based on a much more modern data structure
than the rbtree cache and makes optimisation choices which are probably
more appropriate for modern systems than those made by the rbtree cache. In
v6.5 it has also acquired the ability to generate multi-register writes in
sync operations, bringing performance up to parity with the rbtree cache
there.

Update the wm5102 driver to use the more modern data structure.

Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230713-mfd-cirrus-maple-v1-7-16dacae402a8@kernel.org
Signed-off-by: Lee Jones <lee@kernel.org>

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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

Based on 2 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of th

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

Based on 2 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Enrico Weigelt <info@metux.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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mfd: wm5102: Remove spurious trailing spaces

Remove the trailing spaces on the register default lines to
stop checkpatch complaining.

Signed-off-by: Richard Fitzgerald <rf@opensource.wolfsonmicro.c

mfd: wm5102: Remove spurious trailing spaces

Remove the trailing spaces on the register default lines to
stop checkpatch complaining.

Signed-off-by: Richard Fitzgerald <rf@opensource.wolfsonmicro.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

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mfd: wm5102: Fix defaults array based on testing

My automated test is back and now can check defaults against the actual
hardware. This patch updates the defaults array for the differences
detected

mfd: wm5102: Fix defaults array based on testing

My automated test is back and now can check defaults against the actual
hardware. This patch updates the defaults array for the differences
detected and removes a couple of completely unused registers.

Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

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mfd: arizona: Specify regmap endianness

Explicitly set the regmap endianness instead of relying on
the default being correct.

Signed-off-by: Richard Fitzgerald <rf@opensource.wolfsonmicro.com>
Sign

mfd: arizona: Specify regmap endianness

Explicitly set the regmap endianness instead of relying on
the default being correct.

Signed-off-by: Richard Fitzgerald <rf@opensource.wolfsonmicro.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

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mfd: arizona: Fixup register table definitions

The regmap register definitions have been a source of many small fixes
as issues are discovered. As such I made a small automated tool to
check these

mfd: arizona: Fixup register table definitions

The regmap register definitions have been a source of many small fixes
as issues are discovered. As such I made a small automated tool to
check these definitions. This patch fixes the issues (mostly harmless)
located by that tool, the issues fall into three catagories:

1) Volatile registers that have a default in the defaults table (default
has been removed from the table since it is redundant)
2) Registers that are marked as volatile but unreadable (register has
been removed from the volatile list since it is obviously not being
used)
3) Registers that arn't readable but have an entry in the defaults
table (again removed since it is redundant)
4) Readable non-volatile registers that are missing a default, these are
dangerous as they won't get synced during a cache sync. Fortunately,
most of them seem to be registers that shouldn't be there (for example
wm5102 had readable registers for DRC2 and ISRC3 which is doesn't have)

Hopefully another tool will be produced to check the actual default
values themselves but that is outside the scope of this patch.

Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

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regmap: Use reg_sequence for multi_reg_write / register_patch

Separate the functionality using sequences of register writes from the
functions that take register defaults. This change renames the ar

regmap: Use reg_sequence for multi_reg_write / register_patch

Separate the functionality using sequences of register writes from the
functions that take register defaults. This change renames the arguments
in order to support the extension of reg_sequence to take an optional
delay to be applied after any given register in a sequence is written.
This avoids adding an int to all register defaults, which could
substantially increase memory usage for regmaps with large default tables.

This also updates all the clients of multi_reg_write/register_patch.

Signed-off-by: Nariman Poushin <nariman@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

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mfd: wm5102: Remove registers for output 3R from readable list

The earpiece on 5102 is mono, thus there is no output 3R. Remove the
registers associated with the unused right channel from the readab

mfd: wm5102: Remove registers for output 3R from readable list

The earpiece on 5102 is mono, thus there is no output 3R. Remove the
registers associated with the unused right channel from the readable
registers list.

Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

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mfd: arizona: Document HP_CTRL_1L and HP_CTRL_1R registers

These registers are documented in the datasheet and used as part of the
extcon driver. Expose them properly through regmap as the datasheet

mfd: arizona: Document HP_CTRL_1L and HP_CTRL_1R registers

These registers are documented in the datasheet and used as part of the
extcon driver. Expose them properly through regmap as the datasheet
notes they should be treated as volatile do so.

Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>

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mfd: arizona: Add ASYNC_SAMPLE_RATE_2 registers

Some arizona devices have a second asynchronous sample rate, add the
registers necessary to support this.

Signed-off-by: Charles Keepax <ckeepax@open

mfd: arizona: Add ASYNC_SAMPLE_RATE_2 registers

Some arizona devices have a second asynchronous sample rate, add the
registers necessary to support this.

Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Acked-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

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mfd: arizona: Mark additional registers as volatile

Mark some additional registers as volatile. The write sequencer control
registers should not be cached, as we don't ever want their value
synchron

mfd: arizona: Mark additional registers as volatile

Mark some additional registers as volatile. The write sequencer control
registers should not be cached, as we don't ever want their value
synchronised as this might cause a write sequence to be accidentally
initiated.

Additionally, the DAC_COMP registers require special preconditions to
write so there values wouldn't be updated accurately during a register
sync.

Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

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mfd: wm5102: Mark register write sequencer control 3 readable

During init the core checks if the wm5102 has finished starting by reading
register 0x19 and looking at the value. This read always fail

mfd: wm5102: Mark register write sequencer control 3 readable

During init the core checks if the wm5102 has finished starting by reading
register 0x19 and looking at the value. This read always fails since this
is not a readable register, mark it as being one. While we're at it provide
a constant for the register name (as supplied by Charles Keepax).

Signed-off-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

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mfd: wm5102: Insert missing break in case statement

Chip identifier wm5102_reva_patch is always overwritten with
wm5102_revb_patch, even when the code is run on a Rev-A chip. Place
in the missing b

mfd: wm5102: Insert missing break in case statement

Chip identifier wm5102_reva_patch is always overwritten with
wm5102_revb_patch, even when the code is run on a Rev-A chip. Place
in the missing break to force the code into doing something sensible
instead.

Signed-off-by: Lee Jones <lee.jones@linaro.org>

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mfd: arizona: Rename thermal shutdown interrupt

Newer versions of the IP introduce short circuit protection which will
also shutdown the speaker. Rename the interrupt and associated register
bits as

mfd: arizona: Rename thermal shutdown interrupt

Newer versions of the IP introduce short circuit protection which will
also shutdown the speaker. Rename the interrupt and associated register
bits associated with thermal events to better fit the function and avoid
conflict with future interrupt additions.

Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

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mfd: wm5102: Correct default for LDO Control 2 register

Update the default value to match the patch.

Signed-off-by: Richard Fitzgerald <rf@opensource.wolfsonmicro.com>
Signed-off-by: Lee Jones <lee

mfd: wm5102: Correct default for LDO Control 2 register

Update the default value to match the patch.

Signed-off-by: Richard Fitzgerald <rf@opensource.wolfsonmicro.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

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mfd: arizona: Correct addresses of always-on trigger registers

Update the addresses and names to match current silicon.
The WM8997 regmap tables have been adjusted to match the new
names.
Missing re

mfd: arizona: Correct addresses of always-on trigger registers

Update the addresses and names to match current silicon.
The WM8997 regmap tables have been adjusted to match the new
names.
Missing registers have been added to WM5110 default value table.

Signed-off-by: Richard Fitzgerald <rf@opensource.wolfsonmicro.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

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mfd: arizona: Mark DSP clocking register as volatile

The DSPs will often control there own clock speeds whilst running as
such we should mark the registers controlling this as volatile.

Signed-off-

mfd: arizona: Mark DSP clocking register as volatile

The DSPs will often control there own clock speeds whilst running as
such we should mark the registers controlling this as volatile.

Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

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mfd: wm5102: Make additional DSP registers available to the user

Expose some DSP registers which are useful for DSP users to be able to
access whilst debugging their firmware.

Signed-off-by: Charle

mfd: wm5102: Make additional DSP registers available to the user

Expose some DSP registers which are useful for DSP users to be able to
access whilst debugging their firmware.

Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

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mfd: wm5102: Update register patch

Update the register patch based on latest evaluation of the device.

Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Lee Jones <

mfd: wm5102: Update register patch

Update the register patch based on latest evaluation of the device.

Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

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mfd: arizona: Use new regmap features for manual register patch

On the wm5102 the register patches are applied manually, rather than by
the regmap core. This application is wrapped in calls to
regca

mfd: arizona: Use new regmap features for manual register patch

On the wm5102 the register patches are applied manually, rather than by
the regmap core. This application is wrapped in calls to
regcache_cache_bypass. However, this is dangerous as other threads may
be accessing the hardware at the same time as the pm_runtime operations
and if they do so during the period whilst cache_bypass is enabled those
writes will miss the cache when they shouldn't.

Apply the register patch using the new regmap_multi_reg_write_bypassed
function to avoid this problem. Also remove the call to
regcache_cache_bypass from the hardware patch application as it is
unneeded there and creates a similar window for writes to miss the
cache.

Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Mark Brown <broonie@linaro.org>

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mfd: arizona: Mark missing AOD registers as volatile

This registers ARIZONA_AOD_WKUP_AND_TRIG and ARIZONA_AOD_IRQ_RAW_STATUS
contain interrupt status bits and thus should be volatile. They are
corre

mfd: arizona: Mark missing AOD registers as volatile

This registers ARIZONA_AOD_WKUP_AND_TRIG and ARIZONA_AOD_IRQ_RAW_STATUS
contain interrupt status bits and thus should be volatile. They are
correctly marked on wm5102 but not on wm5110, this patch changes this.
Furthermore volatile registers don't need defaults so remove those.

Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

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mfd: wm5102: Expose DRE control registers

Certain use cases may require specific DRE settings so expose the
necessary registers.

Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>

mfd: wm5102: Expose DRE control registers

Certain use cases may require specific DRE settings so expose the
necessary registers.

Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@linaro.org>

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mfd: wm5102: Map in additional FLL control registers

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>

mfd: wm5102: Update defaults to match patch

Registers which have defaults and are updated by the patch file should
have their defaults updated to match the value set by the patch file,
otherwise inc

mfd: wm5102: Update defaults to match patch

Registers which have defaults and are updated by the patch file should
have their defaults updated to match the value set by the patch file,
otherwise incorrect values will be read from the cache.

Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>

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mfd: wm5102: Manually apply register patch

Future updates will require us to manually apply the register patch for
wm5102.

Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed

mfd: wm5102: Manually apply register patch

Future updates will require us to manually apply the register patch for
wm5102.

Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>

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