|
Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6 |
|
| #
6b1e61f7 |
| 02-Oct-2023 |
Jarkko Nikula <jarkko.nikula@linux.intel.com> |
mfd: intel-lpss: Add Intel Lunar Lake-M PCI IDs
[ Upstream commit e53b22b10c6e0de0cf2a03a92b18fdad70f266c7 ]
Add Intel Lunar Lake-M SoC PCI IDs.
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.i
mfd: intel-lpss: Add Intel Lunar Lake-M PCI IDs
[ Upstream commit e53b22b10c6e0de0cf2a03a92b18fdad70f266c7 ]
Add Intel Lunar Lake-M SoC PCI IDs.
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Link: https://lore.kernel.org/r/20231002083344.75611-1-jarkko.nikula@linux.intel.com
Signed-off-by: Lee Jones <lee@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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|
Revision tags: v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23 |
|
| #
72d4a168 |
| 30-Mar-2023 |
Jarkko Nikula <jarkko.nikula@linux.intel.com> |
mfd: intel-lpss: Add Intel Meteor Lake PCH-S LPSS PCI IDs
Add Intel Meteor Lake PCH-S also called as Meteor Point-S LPSS PCI IDs.
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Acked-
mfd: intel-lpss: Add Intel Meteor Lake PCH-S LPSS PCI IDs
Add Intel Meteor Lake PCH-S also called as Meteor Point-S LPSS PCI IDs.
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20230330132618.4108665-1-jarkko.nikula@linux.intel.com
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|
Revision tags: v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53 |
|
| #
fe55d732 |
| 02-Jul-2022 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
mfd: intel-lpss: Provide an SSP type to the SPI driver
The SPI driver wants to know the exact type of the controller.
Provide this information to it. This is a complementary part to
the previously u
mfd: intel-lpss: Provide an SSP type to the SPI driver
The SPI driver wants to know the exact type of the controller.
Provide this information to it. This is a complementary part to
the previously updated intel-lpss-acpi.c.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20220702211903.9093-1-andriy.shevchenko@linux.intel.com
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|
Revision tags: v5.15.52, v5.15.51 |
|
| #
37e8ba74 |
| 28-Jun-2022 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
mfd: intel-lpss: Add Intel Meteor Lake-P PCI IDs
Add Intel Meteor Lake-P LPSS PCI IDs.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.
mfd: intel-lpss: Add Intel Meteor Lake-P PCI IDs
Add Intel Meteor Lake-P LPSS PCI IDs.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20220628223047.34301-1-andriy.shevchenko@linux.intel.com
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|
Revision tags: v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18 |
|
| #
eeb0a442 |
| 20-May-2022 |
Gaggery Tsai <gaggery.tsai@intel.com> |
mfd: intel-lpss: Add support for ADL-P i2c6 and i2c7
Added 8086:51d8 and 8086:51d9 to the intel_lpss_pci driver. They are
Intel Alder Lake-P i2c controllers.
Signed-off-by: Gaggery Tsai <gaggery.ts
mfd: intel-lpss: Add support for ADL-P i2c6 and i2c7
Added 8086:51d8 and 8086:51d9 to the intel_lpss_pci driver. They are
Intel Alder Lake-P i2c controllers.
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20220520193537.26090-1-gaggery.tsai@intel.com
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|
Revision tags: v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24 |
|
| #
8c70bd58 |
| 11-Feb-2022 |
Jarkko Nikula <jarkko.nikula@linux.intel.com> |
mfd: intel-lpss: Add Intel Raptor Lake PCH-S PCI IDs
Add Intel Raptor Lake PCH-S LPSS PCI IDs.
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shev
mfd: intel-lpss: Add Intel Raptor Lake PCH-S PCI IDs
Add Intel Raptor Lake PCH-S LPSS PCI IDs.
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20220211145055.992179-1-jarkko.nikula@linux.intel.com
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|
Revision tags: v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7 |
|
| #
e6b14206 |
| 03-Dec-2021 |
Hans de Goede <hdegoede@redhat.com> |
mfd: intel-lpss: Fix I2C4 not being available on the Microsoft Surface Go & Go 2
Many DSDTs for Kaby Lake and Kaby Lake Refresh models contain a
_SB.PCI0.GEXP ACPI Device node describing an I2C atta
mfd: intel-lpss: Fix I2C4 not being available on the Microsoft Surface Go & Go 2
Many DSDTs for Kaby Lake and Kaby Lake Refresh models contain a
_SB.PCI0.GEXP ACPI Device node describing an I2C attached PCA953x
GPIO expander.
This seems to be something which is copy and pasted from the DSDT
from some reference design since this ACPI Device is present even on
models where no such GPIO expander is used at all, such as on the
Microsoft Surface Go & Go 2.
This ACPI Device is a problem because it contains a SystemMemory
OperationRegion which covers the MMIO for the I2C4 I2C controller. This
causes the MFD cell for the I2C4 controller to not be instantiated due
to a resource conflict, requiring the use of acpi_enforce_resources=lax
to work around this.
I have done an extensive analysis of all the ACPI tables on the
Microsoft Surface Go and the _SB.PCI0.GEXP ACPI Device's methods are
not used by any code in the ACPI tables, neither are any of them
directly called by any Linux kernel code. This is unsurprising since
running i2cdetect on the I2C4 bus shows that there is no GPIO
expander chip present on these devices at all.
This commit adds a PCI subsystem vendor:device table listing PCI devices
where it is known to be safe to ignore resource conflicts with ACPI
declared SystemMemory regions.
This makes the I2C4 bus work out of the box on the Microsoft Surface
Go & Go 2, which is necessary for the cameras on these devices to work.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20211203115108.89661-1-hdegoede@redhat.com
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|
Revision tags: v5.15.6, v5.15.5 |
|
| #
9651cf2c |
| 24-Nov-2021 |
Orlando Chamberlain <redecorating@protonmail.com> |
mfd: intel-lpss-pci: Fix clock speed for 38a8 UART
This device is found in the MacBookPro16,2, and as the MacBookPro16,1 is
from the same generation of MacBooks and has a UART with bxt_uart_info,
it
mfd: intel-lpss-pci: Fix clock speed for 38a8 UART
This device is found in the MacBookPro16,2, and as the MacBookPro16,1 is
from the same generation of MacBooks and has a UART with bxt_uart_info,
it was incorrectly assumed that the MacBookPro16,2's UART would have the
same info.
This led to the wrong clock speed being used, and the Bluetooth
controller exposed by the UART receiving and sending random data, which
was incorrectly assumed to be an issue with the Bluetooth stuff, not an
error with the UART side of things.
Changing the info to spt_uart_info changes the clock speed and makes it
send and receive data correctly.
Fixes: ddb1ada416fd ("mfd: intel-lpss: Add support for MacBookPro16,2 ICL-N UART")
Signed-off-by: Orlando Chamberlain <redecorating@protonmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20211124091846.11114-1-redecorating@protonmail.com
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|
| #
8b2051a1 |
| 23-Nov-2021 |
Ed Schaller <schallee@darkmist.net> |
mfd: intel-lpss: Add Intel Lakefield PCH PCI IDs
Add new IDs of the Intel Lakefield chip to the list of supported
devices.
Signed-off-by: Ed Schaller <schallee@darkmist.net>
Reviewed-by: Andy Shevc
mfd: intel-lpss: Add Intel Lakefield PCH PCI IDs
Add new IDs of the Intel Lakefield chip to the list of supported
devices.
Signed-off-by: Ed Schaller <schallee@darkmist.net>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20211123180114.GA4747@darkmist.net
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|
Revision tags: v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10 |
|
| #
ddb1ada4 |
| 02-Oct-2021 |
Orlando Chamberlain <redecorating@protonmail.com> |
mfd: intel-lpss: Add support for MacBookPro16,2 ICL-N UART
Added 8086:38a8 to the intel_lpss_pci driver. It is an Intel Ice Lake
PCH-N UART controler present on the MacBookPro16,2.
Signed-off-by: O
mfd: intel-lpss: Add support for MacBookPro16,2 ICL-N UART
Added 8086:38a8 to the intel_lpss_pci driver. It is an Intel Ice Lake
PCH-N UART controler present on the MacBookPro16,2.
Signed-off-by: Orlando Chamberlain <redecorating@protonmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20211002111449.12674-1-redecorating@protonmail.com
show more ...
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|
Revision tags: v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31 |
|
| #
9fb3cad0 |
| 14-Apr-2021 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
mfd: intel-lpss: Add Intel Alder Lake-M PCI IDs
Add Intel Alder Lake-M LPSS PCI IDs.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.or
mfd: intel-lpss: Add Intel Alder Lake-M PCI IDs
Add Intel Alder Lake-M LPSS PCI IDs.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
show more ...
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|
Revision tags: v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20 |
|
| #
03152e35 |
| 01-Mar-2021 |
Heikki Krogerus <heikki.krogerus@linux.intel.com> |
mfd: intel-lpss: Switch to use the software nodes
Software node was always created for the device if it was
supplied with additional device properties, so those nodes
might as well be constant.
Sig
mfd: intel-lpss: Switch to use the software nodes
Software node was always created for the device if it was
supplied with additional device properties, so those nodes
might as well be constant.
Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
show more ...
|
| #
9677e6f7 |
| 01-Mar-2021 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
mfd: intel-lpss: Constify device property structures
There is no point to have non-constant device properties in this driver.
Thus, constify them for good.
Signed-off-by: Andy Shevchenko <andriy.sh
mfd: intel-lpss: Constify device property structures
There is no point to have non-constant device properties in this driver.
Thus, constify them for good.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
show more ...
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|
Revision tags: v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14, v5.10, v5.8.17 |
|
| #
c7b79a75 |
| 27-Oct-2020 |
Jarkko Nikula <jarkko.nikula@linux.intel.com> |
mfd: intel-lpss: Add Intel Alder Lake PCH-S PCI IDs
Add Intel Alder Lake LPSS PCI IDs.
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko
mfd: intel-lpss: Add Intel Alder Lake PCH-S PCI IDs
Add Intel Alder Lake LPSS PCI IDs.
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
show more ...
|
| #
f7b67321 |
| 05-Jan-2021 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
mfd: intel-lpss: Add Intel Alder Lake PCH-P PCI IDs
Add Intel Alder Lake LPSS PCI IDs.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.
mfd: intel-lpss: Add Intel Alder Lake PCH-P PCI IDs
Add Intel Alder Lake LPSS PCI IDs.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
show more ...
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|
Revision tags: v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61 |
|
| #
5f039fa7 |
| 21-Aug-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
mfd: intel-lpss: Add device IDs for UART ports for Lakefield
Add PCI IDs for Lakefield to the list of supported UARTs.
Cc: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Cc: Mika Westerberg <mika.we
mfd: intel-lpss: Add device IDs for UART ports for Lakefield
Add PCI IDs for Lakefield to the list of supported UARTs.
Cc: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: "Ravi V. Shankar" <ravi.v.shankar@intel.com>
Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
show more ...
|
|
Revision tags: v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7 |
|
| #
bb7fcad4 |
| 25-Jun-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
mfd: intel-lpss: Add Intel Tiger Lake PCH-H PCI IDs
Intel Tiger Lake PCH-H has the same LPSS than Intel Broxton.
Add the new IDs to the list of supported devices.
Signed-off-by: Andy Shevchenko <an
mfd: intel-lpss: Add Intel Tiger Lake PCH-H PCI IDs
Intel Tiger Lake PCH-H has the same LPSS than Intel Broxton.
Add the new IDs to the list of supported devices.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
show more ...
|
|
Revision tags: v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47 |
|
| #
3ea2e4ea |
| 15-Jun-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
mfd: intel-lpss: Add Intel Emmitsburg PCH PCI IDs
Intel Emmitsburg PCH has the same LPSS than Intel Ice Lake.
Add the new IDs to the list of supported devices.
Signed-off-by: Andy Shevchenko <andri
mfd: intel-lpss: Add Intel Emmitsburg PCH PCI IDs
Intel Emmitsburg PCH has the same LPSS than Intel Ice Lake.
Add the new IDs to the list of supported devices.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
show more ...
|
|
Revision tags: v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33 |
|
| #
9a875245 |
| 14-Apr-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
mfd: intel-lpss: Update LPSS UART #2 PCI ID for Jasper Lake
It appears that preliminary documentation has a typo in the ID list,
i.e. LPSS UART #2 had been advertised wrongly.
Fix the driver accord
mfd: intel-lpss: Update LPSS UART #2 PCI ID for Jasper Lake
It appears that preliminary documentation has a typo in the ID list,
i.e. LPSS UART #2 had been advertised wrongly.
Fix the driver according to the EDS v0.9.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
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|
|
Revision tags: v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26 |
|
| #
d2923aa4 |
| 16-Mar-2020 |
Jarkko Nikula <jarkko.nikula@linux.intel.com> |
mfd: intel-lpss: Fix Intel Elkhart Lake LPSS I2C input clock
Intel Elkhart Lake LPSS I2C has 100 MHz input clock instead of 133 MHz
that was our preliminary information. This will result slower I2C
mfd: intel-lpss: Fix Intel Elkhart Lake LPSS I2C input clock
Intel Elkhart Lake LPSS I2C has 100 MHz input clock instead of 133 MHz
that was our preliminary information. This will result slower I2C bus
clock when driver calculates its timing parameters in case ACPI tables
don't provide them.
Slower I2C bus clock is allowed but let's fix this to match with
reality.
While at it, keep the same default I2C device properties as Intel
Broxton since it is not known do they need any update.
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
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Revision tags: v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12 |
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4e213b45 |
| 13-Jan-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
mfd: intel-lpss: Add Intel Comet Lake PCH-V PCI IDs
Intel Comet Lake PCH-V has the same LPSS than Intel Kaby Lake.
Add the new IDs to the list of supported devices.
Signed-off-by: Andy Shevchenko <
mfd: intel-lpss: Add Intel Comet Lake PCH-V PCI IDs
Intel Comet Lake PCH-V has the same LPSS than Intel Kaby Lake.
Add the new IDs to the list of supported devices.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
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Revision tags: v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3 |
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57b89dd2 |
| 09-Dec-2019 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
mfd: intel-lpss: Add Intel Jasper Lake PCI IDs
Intel Jasper Lake has the same LPSS than Intel Ice Lake.
Add the new IDs to the list of supported devices.
Signed-off-by: Andy Shevchenko <andriy.shev
mfd: intel-lpss: Add Intel Jasper Lake PCI IDs
Intel Jasper Lake has the same LPSS than Intel Ice Lake.
Add the new IDs to the list of supported devices.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
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Revision tags: v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9 |
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dd047dce |
| 29-Oct-2019 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
mfd: intel-lpss: Add Intel Comet Lake PCH-H PCI IDs
Intel Comet Lake PCH-H has the same LPSS than Intel Cannon Lake.
Add the new IDs to the list of supported devices.
Signed-off-by: Andy Shevchenko
mfd: intel-lpss: Add Intel Comet Lake PCH-H PCI IDs
Intel Comet Lake PCH-H has the same LPSS than Intel Cannon Lake.
Add the new IDs to the list of supported devices.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
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Revision tags: v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12 |
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3f31bc67 |
| 04-Sep-2019 |
Jarkko Nikula <jarkko.nikula@linux.intel.com> |
mfd: intel-lpss: Add default I2C device properties for Gemini Lake
It turned out Intel Gemini Lake doesn't use the same I2C timing
parameters as Broxton.
I got confirmation from the Windows team th
mfd: intel-lpss: Add default I2C device properties for Gemini Lake
It turned out Intel Gemini Lake doesn't use the same I2C timing
parameters as Broxton.
I got confirmation from the Windows team that Gemini Lake systems should
use updated timing parameters that differ from those used in Broxton
based systems.
Fixes: f80e78aa11ad ("mfd: intel-lpss: Add Intel Gemini Lake PCI IDs")
Tested-by: Chris Chiu <chiu@endlessm.com>
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
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Revision tags: v5.2.11, v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6 |
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ec65b560 |
| 01-Aug-2019 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
mfd: intel-lpss: Add Intel Tiger Lake PCI IDs
Intel Tiger Lake has the same LPSS than Intel Broxton.
Add the new IDs to the list of supported devices.
Signed-off-by: Andy Shevchenko <andriy.shevche
mfd: intel-lpss: Add Intel Tiger Lake PCI IDs
Intel Tiger Lake has the same LPSS than Intel Broxton.
Add the new IDs to the list of supported devices.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
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