Revision tags: v3.10, v3.10-rc7, v3.10-rc6, v3.10-rc5, v3.10-rc4, v3.10-rc3, v3.10-rc2, v3.10-rc1, v3.9, v3.9-rc8, v3.9-rc7, v3.9-rc6, v3.9-rc5 |
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#
2abba66e |
| 25-Mar-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: update radeon_atombios_get_default_voltages for mvdd
Add a way to look up the bootup mvdd. Required for DPM on SI.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v3.9-rc4 |
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7178d2a6 |
| 21-Mar-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/dpm: save some display parameters for DPM
Required for SI.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v3.9-rc3, v3.9-rc2, v3.9-rc1, v3.8 |
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#
65171944 |
| 13-Feb-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: update radeon_atom_get_voltage_table() for SI
SI uses a new atom table revision. Required for DPM on SI.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
eaa778af |
| 13-Feb-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/atom: add helper to calcuate mpll params
There's a new table for calculating the memory pll parameters on SI. Required for SI DPM support.
Signed-off-by: Alex Deucher <alexander.deucher
drm/radeon/atom: add helper to calcuate mpll params
There's a new table for calculating the memory pll parameters on SI. Required for SI DPM support.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4a6369e9 |
| 12-Apr-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/kms: add dpm support for rv6xx (v3)
This adds dpm support for rv6xx asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage sc
drm/radeon/kms: add dpm support for rv6xx (v3)
This adds dpm support for rv6xx asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching
Set radeon.dpm=1 to enable.
v2: remove duplicate line v3: fix thermal interrupt check noticed by Jerome
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
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#
ae5b0abb |
| 24-Jun-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/kms: add atom helper functions for dpm (v3)
dpm needs access to atombios data and command tables for setup and calculation of a number of parameters.
v2: endian fix v3: fix mc reg table
drm/radeon/kms: add atom helper functions for dpm (v3)
dpm needs access to atombios data and command tables for setup and calculation of a number of parameters.
v2: endian fix v3: fix mc reg table bug
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9219ed65 |
| 19-Feb-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: update radeon_atom_get_clock_dividers for CIK
CIK uses a slightly different variant of the table structs and params.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v3.8-rc7, v3.8-rc6, v3.8-rc5 |
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9e05fa1d |
| 24-Jan-2013 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/cik: add hw cursor support (v2)
CIK (DCE8) hw cursors are programmed the same as evergreen (DCE4) with the following caveats: - cursors are now 128x128 pixels - new alpha blend enable bit
drm/radeon/cik: add hw cursor support (v2)
CIK (DCE8) hw cursors are programmed the same as evergreen (DCE4) with the following caveats: - cursors are now 128x128 pixels - new alpha blend enable bit
v2: rebase
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6ab76310 |
| 14-May-2013 |
Niels Ole Salscheider <niels_ole@salscheider-online.de> |
drm/radeon: Remove superfluous variable
bool in_mode_set from struct radeon_crtc is not used anymore.
Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de> Signed-off-by: Alex Deuc
drm/radeon: Remove superfluous variable
bool in_mode_set from struct radeon_crtc is not used anymore.
Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7062ab67 |
| 08-Apr-2013 |
Christian König <deathsimple@vodafone.de> |
drm/radeon: add radeon_atom_get_clock_dividers helper
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander
drm/radeon: add radeon_atom_get_clock_dividers helper
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v3.8-rc4, v3.8-rc3 |
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#
0a9069d3 |
| 03-Jan-2013 |
Niels Ole Salscheider <niels_ole@salscheider-online.de> |
drm/radeon: Properly handle DDC probe for DP bridges
DDC information can be accessed using AUX CH
Fixes failure to probe monitors on some systems with DP bridge chips.
agd5f: minor fixes
Signed-o
drm/radeon: Properly handle DDC probe for DP bridges
DDC information can be accessed using AUX CH
Fixes failure to probe monitors on some systems with DP bridge chips.
agd5f: minor fixes
Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Revision tags: v3.8-rc2, v3.8-rc1 |
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#
cafa59b9 |
| 20-Dec-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: add connector table for Mac G4 Silver
Apple cards do not provide data tables in the vbios so we have to hard code the connector parameters in the driver.
Reported-by: Albrecht Dreß <alb
drm/radeon: add connector table for Mac G4 Silver
Apple cards do not provide data tables in the vbios so we have to hard code the connector parameters in the driver.
Reported-by: Albrecht Dreß <albrecht.dress@arcor.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Revision tags: v3.7, v3.7-rc8, v3.7-rc7, v3.7-rc6, v3.7-rc5, v3.7-rc4, v3.7-rc3, v3.7-rc2 |
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#
1a644cd4 |
| 18-Oct-2012 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm: extract dp link train delay functions from radeon
This requires a few changes since that dpcd value is above the range currently cached by radeon. I've check the dp specs, and above 0xf there's
drm: extract dp link train delay functions from radeon
This requires a few changes since that dpcd value is above the range currently cached by radeon. I've check the dp specs, and above 0xf there's a big gap and nothing that looks like we should cache it while a given device is plugged in. It's also the same value that i915.ko uses.
Hence extend the various dpcd arrays in the radeon driver, use proper symbolic constants where applicable (one place overallocated the dpcd array to 25 bytes). Then also drop the rd_interval cache - radeon_dp_link_train_init re-reads the dpcd block, so the values we'll consume in train_cr and train_ce will always be fresh.
To avoid needless diff-churn, #define the old size of dpcd as the new one and keep it around.
v2: Alex Deucher noticed one place where I've forgotten to replace 8 with DP_RECEIVER_CAP_SIZE.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Revision tags: v3.7-rc1 |
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#
760285e7 |
| 02-Oct-2012 |
David Howells <dhowells@redhat.com> |
UAPI: (Scripted) Convert #include "..." to #include <path/...> in drivers/gpu/
Convert #include "..." to #include <path/...> in drivers/gpu/.
Signed-off-by: David Howells <dhowells@redhat.com> Acke
UAPI: (Scripted) Convert #include "..." to #include <path/...> in drivers/gpu/
Convert #include "..." to #include <path/...> in drivers/gpu/.
Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Dave Airlie <airlied@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Acked-by: Dave Jones <davej@redhat.com>
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#
4126d5d6 |
| 02-Oct-2012 |
David Howells <dhowells@redhat.com> |
UAPI: (Scripted) Remove redundant DRM UAPI header #inclusions from drivers/gpu/.
Remove redundant DRM UAPI header #inclusions from drivers/gpu/.
Remove redundant #inclusions of core DRM UAPI header
UAPI: (Scripted) Remove redundant DRM UAPI header #inclusions from drivers/gpu/.
Remove redundant DRM UAPI header #inclusions from drivers/gpu/.
Remove redundant #inclusions of core DRM UAPI headers (drm.h, drm_mode.h and drm_sarea.h). They are now #included via drmP.h and drm_crtc.h via a preceding patch.
Without this patch and the patch to make include the UAPI headers from the core headers, after the UAPI split, the DRM C sources cannot find these UAPI headers because the DRM code relies on specific -I flags to make #include "..." work on headers in include/drm/ - but that does not work after the UAPI split without adding more -I flags.
Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Dave Airlie <airlied@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Acked-by: Dave Jones <davej@redhat.com>
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Revision tags: v3.6, v3.6-rc7, v3.6-rc6 |
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#
bced76f2 |
| 14-Sep-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: restore backlight level on resume
Restore the backlight level on resume. Some systems need to explicitly restore the backlight level on resume.
Fixes panel resume on my Trinity laptop
drm/radeon: restore backlight level on resume
Restore the backlight level on resume. Some systems need to explicitly restore the backlight level on resume.
Fixes panel resume on my Trinity laptop and may fix the following bugs: https://bugs.freedesktop.org/show_bug.cgi?id=43829 https://bugzilla.kernel.org/show_bug.cgi?id=46241
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
57b35e29 |
| 17-Sep-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: work around KMS modeset limitations in PLL allocation (v2)
Since the current KMS API sets the mode independantly on each crtc, we may end up with resource conflicts. The PLL allocation
drm/radeon: work around KMS modeset limitations in PLL allocation (v2)
Since the current KMS API sets the mode independantly on each crtc, we may end up with resource conflicts. The PLL allocation is one of those cases. In the following example we have 3 crtcs in use driving 2 DVI connectors and 1 DP connector. On the initial kernel modeset for fbdev, the display topology ends up as follows:
crtc0 -> DP-0 crtc1 -> DVI-0 crtc2 -> DVI-1
Because this is the first modeset, all of the PLLs are available as none have been assigned. So we end up with the following:
crtc0 uses DCPLL crtc1 uses PPLL2 crtc2 uses PPLL1
When X starts, it assigns a different topology:
crtc0 -> DVI-0 crtc1 -> DP-0 crtc2 -> DVI-1
However, since the KMS API is per crtc, we set the mode on each crtc independantly. When it comes time to set the mode on crtc0, the topology for crtc1 and crtc2 are still intact. crtc1 and crtc2 are already assigned PPLL2 and PPLL1 so when it comes time to set the mode on crtc0, crtc1 and crtc2 have not been torn down yet, so there appears to be no PLLs available. In reality, we are reconfiguring the entire display topology, however, since each crtc is handled independantly, we don't know that in the driver at each crtc mode set time.
This patch checks to see if the same connector is being driven by another crtc, and if so, uses the PLL already associated with it.
v2: store connector in the radeon crtc struct, simplify checking.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5df3196b |
| 13-Sep-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: store the encoder in the radeon_crtc
This saves lots of lookups later.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
19eca43e |
| 13-Sep-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: rework crtc pll setup to better support PPLL sharing
We need the calculate the pixel clock before allocating a PPLL in order to insure the clocks really match.
Signed-off-by: Alex Deuch
drm/radeon: rework crtc pll setup to better support PPLL sharing
We need the calculate the pixel clock before allocating a PPLL in order to insure the clocks really match.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v3.6-rc5, v3.6-rc4, v3.6-rc3, v3.6-rc2 |
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#
37e9b6a6 |
| 03-Aug-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: rework the backlight control to be an asic callback
This cleans up the interface a bit as well.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v3.6-rc1 |
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fda4b25c |
| 30-Jul-2012 |
Luca Tettamanti <kronos.it@gmail.com> |
drm/radeon: implement handler for ACPI event
Set up an handler for ACPI events and respond to brightness change requests from the system BIOS. v2: fix notification when using device-specific command
drm/radeon: implement handler for ACPI event
Set up an handler for ACPI events and respond to brightness change requests from the system BIOS. v2: fix notification when using device-specific command codes (tested by Pali Rohár <pali.rohar@gmail.com>); cache the encoder controlling the backlight during the initialization to avoid searching it every time (suggested by Alex Deucher). v3: whitespace fixes (Alex Deucher).
Signed-off-by: Luca Tettamanti <kronos.it@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
91030880 |
| 26-Jul-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: rework legacy backlight control
To better enable sharing with atom backlight control.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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af7912e5 |
| 26-Jul-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: track whether the GPU controls the backlight (v2)
A table in the vbios tells us whether the GPU backlight controller is used or not. If the bit is set, the GPU backlight controller is u
drm/radeon: track whether the GPU controls the backlight (v2)
A table in the vbios tells us whether the GPU backlight controller is used or not. If the bit is set, the GPU backlight controller is used; if it is not set, an off-chip backlight controller is used.
v2: store all the firmware flags, not just BL control
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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6c0ae2ab |
| 26-Jul-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: properly handle crtc powergating
Need to make sure the crtc is gated on before modesetting. Explicitly gate the crtc on in prepare() and set a flag so that the dpms functions don't gate
drm/radeon: properly handle crtc powergating
Need to make sure the crtc is gated on before modesetting. Explicitly gate the crtc on in prepare() and set a flag so that the dpms functions don't gate it off during mode set.
Noticed by sylware on IRC.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Revision tags: v3.5 |
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#
e811f5ae |
| 17-Jul-2012 |
Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
drm: Make the .mode_fixup() operations mode argument a const pointer
The passed mode must not be modified by the operation, make it const.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonb
drm: Make the .mode_fixup() operations mode argument a const pointer
The passed mode must not be modified by the operation, make it const.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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