1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Original Authors: 25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26 * 27 * Kernel port Author: Dave Airlie 28 */ 29 30 #ifndef RADEON_MODE_H 31 #define RADEON_MODE_H 32 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_edid.h> 35 #include <drm/drm_dp_helper.h> 36 #include <drm/drm_fixed.h> 37 #include <drm/drm_crtc_helper.h> 38 #include <linux/i2c.h> 39 #include <linux/i2c-algo-bit.h> 40 41 struct radeon_bo; 42 struct radeon_device; 43 44 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 45 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 46 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 47 #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 48 49 enum radeon_rmx_type { 50 RMX_OFF, 51 RMX_FULL, 52 RMX_CENTER, 53 RMX_ASPECT 54 }; 55 56 enum radeon_tv_std { 57 TV_STD_NTSC, 58 TV_STD_PAL, 59 TV_STD_PAL_M, 60 TV_STD_PAL_60, 61 TV_STD_NTSC_J, 62 TV_STD_SCART_PAL, 63 TV_STD_SECAM, 64 TV_STD_PAL_CN, 65 TV_STD_PAL_N, 66 }; 67 68 enum radeon_underscan_type { 69 UNDERSCAN_OFF, 70 UNDERSCAN_ON, 71 UNDERSCAN_AUTO, 72 }; 73 74 enum radeon_hpd_id { 75 RADEON_HPD_1 = 0, 76 RADEON_HPD_2, 77 RADEON_HPD_3, 78 RADEON_HPD_4, 79 RADEON_HPD_5, 80 RADEON_HPD_6, 81 RADEON_HPD_NONE = 0xff, 82 }; 83 84 #define RADEON_MAX_I2C_BUS 16 85 86 /* radeon gpio-based i2c 87 * 1. "mask" reg and bits 88 * grabs the gpio pins for software use 89 * 0=not held 1=held 90 * 2. "a" reg and bits 91 * output pin value 92 * 0=low 1=high 93 * 3. "en" reg and bits 94 * sets the pin direction 95 * 0=input 1=output 96 * 4. "y" reg and bits 97 * input pin value 98 * 0=low 1=high 99 */ 100 struct radeon_i2c_bus_rec { 101 bool valid; 102 /* id used by atom */ 103 uint8_t i2c_id; 104 /* id used by atom */ 105 enum radeon_hpd_id hpd; 106 /* can be used with hw i2c engine */ 107 bool hw_capable; 108 /* uses multi-media i2c engine */ 109 bool mm_i2c; 110 /* regs and bits */ 111 uint32_t mask_clk_reg; 112 uint32_t mask_data_reg; 113 uint32_t a_clk_reg; 114 uint32_t a_data_reg; 115 uint32_t en_clk_reg; 116 uint32_t en_data_reg; 117 uint32_t y_clk_reg; 118 uint32_t y_data_reg; 119 uint32_t mask_clk_mask; 120 uint32_t mask_data_mask; 121 uint32_t a_clk_mask; 122 uint32_t a_data_mask; 123 uint32_t en_clk_mask; 124 uint32_t en_data_mask; 125 uint32_t y_clk_mask; 126 uint32_t y_data_mask; 127 }; 128 129 struct radeon_tmds_pll { 130 uint32_t freq; 131 uint32_t value; 132 }; 133 134 #define RADEON_MAX_BIOS_CONNECTOR 16 135 136 /* pll flags */ 137 #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 138 #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 139 #define RADEON_PLL_USE_REF_DIV (1 << 2) 140 #define RADEON_PLL_LEGACY (1 << 3) 141 #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 142 #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 143 #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 144 #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 145 #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 146 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 147 #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 148 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 149 #define RADEON_PLL_USE_POST_DIV (1 << 12) 150 #define RADEON_PLL_IS_LCD (1 << 13) 151 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 152 153 struct radeon_pll { 154 /* reference frequency */ 155 uint32_t reference_freq; 156 157 /* fixed dividers */ 158 uint32_t reference_div; 159 uint32_t post_div; 160 161 /* pll in/out limits */ 162 uint32_t pll_in_min; 163 uint32_t pll_in_max; 164 uint32_t pll_out_min; 165 uint32_t pll_out_max; 166 uint32_t lcd_pll_out_min; 167 uint32_t lcd_pll_out_max; 168 uint32_t best_vco; 169 170 /* divider limits */ 171 uint32_t min_ref_div; 172 uint32_t max_ref_div; 173 uint32_t min_post_div; 174 uint32_t max_post_div; 175 uint32_t min_feedback_div; 176 uint32_t max_feedback_div; 177 uint32_t min_frac_feedback_div; 178 uint32_t max_frac_feedback_div; 179 180 /* flags for the current clock */ 181 uint32_t flags; 182 183 /* pll id */ 184 uint32_t id; 185 }; 186 187 struct radeon_i2c_chan { 188 struct i2c_adapter adapter; 189 struct drm_device *dev; 190 union { 191 struct i2c_algo_bit_data bit; 192 struct i2c_algo_dp_aux_data dp; 193 } algo; 194 struct radeon_i2c_bus_rec rec; 195 }; 196 197 /* mostly for macs, but really any system without connector tables */ 198 enum radeon_connector_table { 199 CT_NONE = 0, 200 CT_GENERIC, 201 CT_IBOOK, 202 CT_POWERBOOK_EXTERNAL, 203 CT_POWERBOOK_INTERNAL, 204 CT_POWERBOOK_VGA, 205 CT_MINI_EXTERNAL, 206 CT_MINI_INTERNAL, 207 CT_IMAC_G5_ISIGHT, 208 CT_EMAC, 209 CT_RN50_POWER, 210 CT_MAC_X800, 211 CT_MAC_G5_9600, 212 CT_SAM440EP, 213 CT_MAC_G4_SILVER 214 }; 215 216 enum radeon_dvo_chip { 217 DVO_SIL164, 218 DVO_SIL1178, 219 }; 220 221 struct radeon_fbdev; 222 223 struct radeon_afmt { 224 bool enabled; 225 int offset; 226 bool last_buffer_filled_status; 227 int id; 228 }; 229 230 struct radeon_mode_info { 231 struct atom_context *atom_context; 232 struct card_info *atom_card_info; 233 enum radeon_connector_table connector_table; 234 bool mode_config_initialized; 235 struct radeon_crtc *crtcs[6]; 236 struct radeon_afmt *afmt[6]; 237 /* DVI-I properties */ 238 struct drm_property *coherent_mode_property; 239 /* DAC enable load detect */ 240 struct drm_property *load_detect_property; 241 /* TV standard */ 242 struct drm_property *tv_std_property; 243 /* legacy TMDS PLL detect */ 244 struct drm_property *tmds_pll_property; 245 /* underscan */ 246 struct drm_property *underscan_property; 247 struct drm_property *underscan_hborder_property; 248 struct drm_property *underscan_vborder_property; 249 /* hardcoded DFP edid from BIOS */ 250 struct edid *bios_hardcoded_edid; 251 int bios_hardcoded_edid_size; 252 253 /* pointer to fbdev info structure */ 254 struct radeon_fbdev *rfbdev; 255 /* firmware flags */ 256 u16 firmware_flags; 257 /* pointer to backlight encoder */ 258 struct radeon_encoder *bl_encoder; 259 }; 260 261 #define RADEON_MAX_BL_LEVEL 0xFF 262 263 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 264 265 struct radeon_backlight_privdata { 266 struct radeon_encoder *encoder; 267 uint8_t negative; 268 }; 269 270 #endif 271 272 #define MAX_H_CODE_TIMING_LEN 32 273 #define MAX_V_CODE_TIMING_LEN 32 274 275 /* need to store these as reading 276 back code tables is excessive */ 277 struct radeon_tv_regs { 278 uint32_t tv_uv_adr; 279 uint32_t timing_cntl; 280 uint32_t hrestart; 281 uint32_t vrestart; 282 uint32_t frestart; 283 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 284 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 285 }; 286 287 struct radeon_atom_ss { 288 uint16_t percentage; 289 uint8_t type; 290 uint16_t step; 291 uint8_t delay; 292 uint8_t range; 293 uint8_t refdiv; 294 /* asic_ss */ 295 uint16_t rate; 296 uint16_t amount; 297 }; 298 299 struct radeon_crtc { 300 struct drm_crtc base; 301 int crtc_id; 302 u16 lut_r[256], lut_g[256], lut_b[256]; 303 bool enabled; 304 bool can_tile; 305 bool in_mode_set; 306 uint32_t crtc_offset; 307 struct drm_gem_object *cursor_bo; 308 uint64_t cursor_addr; 309 int cursor_width; 310 int cursor_height; 311 uint32_t legacy_display_base_addr; 312 uint32_t legacy_cursor_offset; 313 enum radeon_rmx_type rmx_type; 314 u8 h_border; 315 u8 v_border; 316 fixed20_12 vsc; 317 fixed20_12 hsc; 318 struct drm_display_mode native_mode; 319 int pll_id; 320 /* page flipping */ 321 struct radeon_unpin_work *unpin_work; 322 int deferred_flip_completion; 323 /* pll sharing */ 324 struct radeon_atom_ss ss; 325 bool ss_enabled; 326 u32 adjusted_clock; 327 int bpc; 328 u32 pll_reference_div; 329 u32 pll_post_div; 330 u32 pll_flags; 331 struct drm_encoder *encoder; 332 struct drm_connector *connector; 333 }; 334 335 struct radeon_encoder_primary_dac { 336 /* legacy primary dac */ 337 uint32_t ps2_pdac_adj; 338 }; 339 340 struct radeon_encoder_lvds { 341 /* legacy lvds */ 342 uint16_t panel_vcc_delay; 343 uint8_t panel_pwr_delay; 344 uint8_t panel_digon_delay; 345 uint8_t panel_blon_delay; 346 uint16_t panel_ref_divider; 347 uint8_t panel_post_divider; 348 uint16_t panel_fb_divider; 349 bool use_bios_dividers; 350 uint32_t lvds_gen_cntl; 351 /* panel mode */ 352 struct drm_display_mode native_mode; 353 struct backlight_device *bl_dev; 354 int dpms_mode; 355 uint8_t backlight_level; 356 }; 357 358 struct radeon_encoder_tv_dac { 359 /* legacy tv dac */ 360 uint32_t ps2_tvdac_adj; 361 uint32_t ntsc_tvdac_adj; 362 uint32_t pal_tvdac_adj; 363 364 int h_pos; 365 int v_pos; 366 int h_size; 367 int supported_tv_stds; 368 bool tv_on; 369 enum radeon_tv_std tv_std; 370 struct radeon_tv_regs tv; 371 }; 372 373 struct radeon_encoder_int_tmds { 374 /* legacy int tmds */ 375 struct radeon_tmds_pll tmds_pll[4]; 376 }; 377 378 struct radeon_encoder_ext_tmds { 379 /* tmds over dvo */ 380 struct radeon_i2c_chan *i2c_bus; 381 uint8_t slave_addr; 382 enum radeon_dvo_chip dvo_chip; 383 }; 384 385 /* spread spectrum */ 386 struct radeon_encoder_atom_dig { 387 bool linkb; 388 /* atom dig */ 389 bool coherent_mode; 390 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 391 /* atom lvds/edp */ 392 uint32_t lcd_misc; 393 uint16_t panel_pwr_delay; 394 uint32_t lcd_ss_id; 395 /* panel mode */ 396 struct drm_display_mode native_mode; 397 struct backlight_device *bl_dev; 398 int dpms_mode; 399 uint8_t backlight_level; 400 int panel_mode; 401 struct radeon_afmt *afmt; 402 }; 403 404 struct radeon_encoder_atom_dac { 405 enum radeon_tv_std tv_std; 406 }; 407 408 struct radeon_encoder { 409 struct drm_encoder base; 410 uint32_t encoder_enum; 411 uint32_t encoder_id; 412 uint32_t devices; 413 uint32_t active_device; 414 uint32_t flags; 415 uint32_t pixel_clock; 416 enum radeon_rmx_type rmx_type; 417 enum radeon_underscan_type underscan_type; 418 uint32_t underscan_hborder; 419 uint32_t underscan_vborder; 420 struct drm_display_mode native_mode; 421 void *enc_priv; 422 int audio_polling_active; 423 bool is_ext_encoder; 424 u16 caps; 425 }; 426 427 struct radeon_connector_atom_dig { 428 uint32_t igp_lane_info; 429 /* displayport */ 430 struct radeon_i2c_chan *dp_i2c_bus; 431 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 432 u8 dp_sink_type; 433 int dp_clock; 434 int dp_lane_count; 435 bool edp_on; 436 }; 437 438 struct radeon_gpio_rec { 439 bool valid; 440 u8 id; 441 u32 reg; 442 u32 mask; 443 }; 444 445 struct radeon_hpd { 446 enum radeon_hpd_id hpd; 447 u8 plugged_state; 448 struct radeon_gpio_rec gpio; 449 }; 450 451 struct radeon_router { 452 u32 router_id; 453 struct radeon_i2c_bus_rec i2c_info; 454 u8 i2c_addr; 455 /* i2c mux */ 456 bool ddc_valid; 457 u8 ddc_mux_type; 458 u8 ddc_mux_control_pin; 459 u8 ddc_mux_state; 460 /* clock/data mux */ 461 bool cd_valid; 462 u8 cd_mux_type; 463 u8 cd_mux_control_pin; 464 u8 cd_mux_state; 465 }; 466 467 struct radeon_connector { 468 struct drm_connector base; 469 uint32_t connector_id; 470 uint32_t devices; 471 struct radeon_i2c_chan *ddc_bus; 472 /* some systems have an hdmi and vga port with a shared ddc line */ 473 bool shared_ddc; 474 bool use_digital; 475 /* we need to mind the EDID between detect 476 and get modes due to analog/digital/tvencoder */ 477 struct edid *edid; 478 void *con_priv; 479 bool dac_load_detect; 480 bool detected_by_load; /* if the connection status was determined by load */ 481 uint16_t connector_object_id; 482 struct radeon_hpd hpd; 483 struct radeon_router router; 484 struct radeon_i2c_chan *router_bus; 485 }; 486 487 struct radeon_framebuffer { 488 struct drm_framebuffer base; 489 struct drm_gem_object *obj; 490 }; 491 492 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 493 ((em) == ATOM_ENCODER_MODE_DP_MST)) 494 495 extern enum radeon_tv_std 496 radeon_combios_get_tv_info(struct radeon_device *rdev); 497 extern enum radeon_tv_std 498 radeon_atombios_get_tv_info(struct radeon_device *rdev); 499 500 extern struct drm_connector * 501 radeon_get_connector_for_encoder(struct drm_encoder *encoder); 502 extern struct drm_connector * 503 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); 504 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, 505 u32 pixel_clock); 506 507 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 508 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); 509 extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector); 510 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); 511 extern int radeon_get_monitor_bpc(struct drm_connector *connector); 512 513 extern void radeon_connector_hotplug(struct drm_connector *connector); 514 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, 515 struct drm_display_mode *mode); 516 extern void radeon_dp_set_link_config(struct drm_connector *connector, 517 const struct drm_display_mode *mode); 518 extern void radeon_dp_link_train(struct drm_encoder *encoder, 519 struct drm_connector *connector); 520 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 521 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 522 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 523 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 524 struct drm_connector *connector); 525 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 526 extern void radeon_atom_encoder_init(struct radeon_device *rdev); 527 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); 528 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 529 int action, uint8_t lane_num, 530 uint8_t lane_set); 531 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 532 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 533 extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 534 u8 write_byte, u8 *read_byte); 535 536 extern void radeon_i2c_init(struct radeon_device *rdev); 537 extern void radeon_i2c_fini(struct radeon_device *rdev); 538 extern void radeon_combios_i2c_init(struct radeon_device *rdev); 539 extern void radeon_atombios_i2c_init(struct radeon_device *rdev); 540 extern void radeon_i2c_add(struct radeon_device *rdev, 541 struct radeon_i2c_bus_rec *rec, 542 const char *name); 543 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 544 struct radeon_i2c_bus_rec *i2c_bus); 545 extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 546 struct radeon_i2c_bus_rec *rec, 547 const char *name); 548 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 549 struct radeon_i2c_bus_rec *rec, 550 const char *name); 551 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 552 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 553 u8 slave_addr, 554 u8 addr, 555 u8 *val); 556 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 557 u8 slave_addr, 558 u8 addr, 559 u8 val); 560 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 561 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 562 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector); 563 extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); 564 565 extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); 566 567 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 568 struct radeon_atom_ss *ss, 569 int id); 570 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 571 struct radeon_atom_ss *ss, 572 int id, u32 clock); 573 574 extern void radeon_compute_pll_legacy(struct radeon_pll *pll, 575 uint64_t freq, 576 uint32_t *dot_clock_p, 577 uint32_t *fb_div_p, 578 uint32_t *frac_fb_div_p, 579 uint32_t *ref_div_p, 580 uint32_t *post_div_p); 581 582 extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 583 u32 freq, 584 u32 *dot_clock_p, 585 u32 *fb_div_p, 586 u32 *frac_fb_div_p, 587 u32 *ref_div_p, 588 u32 *post_div_p); 589 590 extern void radeon_setup_encoder_clones(struct drm_device *dev); 591 592 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 593 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 594 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 595 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 596 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 597 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 598 extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 599 extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 600 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); 601 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 602 603 extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 604 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 605 struct drm_framebuffer *old_fb); 606 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 607 struct drm_framebuffer *fb, 608 int x, int y, 609 enum mode_set_atomic state); 610 extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 611 struct drm_display_mode *mode, 612 struct drm_display_mode *adjusted_mode, 613 int x, int y, 614 struct drm_framebuffer *old_fb); 615 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 616 617 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 618 struct drm_framebuffer *old_fb); 619 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 620 struct drm_framebuffer *fb, 621 int x, int y, 622 enum mode_set_atomic state); 623 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 624 struct drm_framebuffer *fb, 625 int x, int y, int atomic); 626 extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, 627 struct drm_file *file_priv, 628 uint32_t handle, 629 uint32_t width, 630 uint32_t height); 631 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 632 int x, int y); 633 634 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 635 int *vpos, int *hpos); 636 637 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 638 extern struct edid * 639 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); 640 extern bool radeon_atom_get_clock_info(struct drm_device *dev); 641 extern bool radeon_combios_get_clock_info(struct drm_device *dev); 642 extern struct radeon_encoder_atom_dig * 643 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 644 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 645 struct radeon_encoder_int_tmds *tmds); 646 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 647 struct radeon_encoder_int_tmds *tmds); 648 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 649 struct radeon_encoder_int_tmds *tmds); 650 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 651 struct radeon_encoder_ext_tmds *tmds); 652 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 653 struct radeon_encoder_ext_tmds *tmds); 654 extern struct radeon_encoder_primary_dac * 655 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 656 extern struct radeon_encoder_tv_dac * 657 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 658 extern struct radeon_encoder_lvds * 659 radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 660 extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 661 extern struct radeon_encoder_tv_dac * 662 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 663 extern struct radeon_encoder_primary_dac * 664 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 665 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 666 extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 667 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 668 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 669 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 670 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 671 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 672 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 673 extern void 674 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 675 extern void 676 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 677 extern void 678 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 679 extern void 680 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 681 extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 682 u16 blue, int regno); 683 extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 684 u16 *blue, int regno); 685 int radeon_framebuffer_init(struct drm_device *dev, 686 struct radeon_framebuffer *rfb, 687 struct drm_mode_fb_cmd2 *mode_cmd, 688 struct drm_gem_object *obj); 689 690 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 691 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 692 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 693 void radeon_atombios_init_crtc(struct drm_device *dev, 694 struct radeon_crtc *radeon_crtc); 695 void radeon_legacy_init_crtc(struct drm_device *dev, 696 struct radeon_crtc *radeon_crtc); 697 698 void radeon_get_clock_info(struct drm_device *dev); 699 700 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 701 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 702 703 void radeon_enc_destroy(struct drm_encoder *encoder); 704 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 705 void radeon_combios_asic_init(struct drm_device *dev); 706 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 707 const struct drm_display_mode *mode, 708 struct drm_display_mode *adjusted_mode); 709 void radeon_panel_mode_fixup(struct drm_encoder *encoder, 710 struct drm_display_mode *adjusted_mode); 711 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 712 713 /* legacy tv */ 714 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 715 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 716 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 717 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 718 uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 719 uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 720 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 721 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 722 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 723 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 724 struct drm_display_mode *mode, 725 struct drm_display_mode *adjusted_mode); 726 727 /* fbdev layer */ 728 int radeon_fbdev_init(struct radeon_device *rdev); 729 void radeon_fbdev_fini(struct radeon_device *rdev); 730 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); 731 int radeon_fbdev_total_size(struct radeon_device *rdev); 732 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 733 734 void radeon_fb_output_poll_changed(struct radeon_device *rdev); 735 736 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); 737 738 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); 739 #endif 740