drm/radeon: fill in set_vce_clocks for CIK asics

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/radeon: initial VCE support v4

Only VCE 2.0 support so far.

v2: squashing multiple patches into this one
v3: add IRQ support for CIK, major cleanups,
basic code documentation
v4: remove HAI

drm/radeon: initial VCE support v4

Only VCE 2.0 support so far.

v2: squashing multiple patches into this one
v3: add IRQ support for CIK, major cleanups,
basic code documentation
v4: remove HAINAN from chipset list

Signed-off-by: Christian König <christian.koenig@amd.com>

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drm/radeon/dpm: use the driver state for dpm debugfs

For btc and newer, we may modify the power state depending
on the circumstances. Use the modified state rather than
the base state.

Signed-off-

drm/radeon/dpm: use the driver state for dpm debugfs

For btc and newer, we may modify the power state depending
on the circumstances. Use the modified state rather than
the base state.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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drm/radeon: remove generic rptr/wptr functions (v2)

Fill in asic family specific versions rather than
using the generic version. This lets us handle asic
specific differences more easily. In this

drm/radeon: remove generic rptr/wptr functions (v2)

Fill in asic family specific versions rather than
using the generic version. This lets us handle asic
specific differences more easily. In this case, we
disable sw swapping of the rtpr writeback value on
r6xx+ since the hw does it for us. Fixes bogus
rptr readback on BE systems.

v2: remove missed cpu_to_le32(), add comments

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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drm/radeon: enable gfx cgcg on CIK APUs

Enable coarse grained clockgating. This works properly now
that smc is initialized earlier than the rlc and cp.

Signed-off-by: Alex Deucher <alexander.deuch

drm/radeon: enable gfx cgcg on CIK APUs

Enable coarse grained clockgating. This works properly now
that smc is initialized earlier than the rlc and cp.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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drm/radeon: enable gfx cgcg on CIK dGPUs

Enable coarse grained clockgating on CIK dGPUs. This
works properly now that smc is initialized earlier than
the rlc and cp.

Signed-off-by: Alex Deucher <a

drm/radeon: enable gfx cgcg on CIK dGPUs

Enable coarse grained clockgating on CIK dGPUs. This
works properly now that smc is initialized earlier than
the rlc and cp.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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drm/radeon/dpm: add late_enable for KB/KV

Make sure interrupts are enabled
before we enable thermal interrupts.
Also, don't powergate uvd, etc. until after
the ring tests.

Signed-off-by: Alex Deuch

drm/radeon/dpm: add late_enable for KB/KV

Make sure interrupts are enabled
before we enable thermal interrupts.
Also, don't powergate uvd, etc. until after
the ring tests.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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drm/radeon/dpm: add late_enable for CI

Make sure interrupts are enabled
before we enable thermal interrupts.
Also, don't powergate uvd until after
the ring tests.

Signed-off-by: Alex Deucher <alexa

drm/radeon/dpm: add late_enable for CI

Make sure interrupts are enabled
before we enable thermal interrupts.
Also, don't powergate uvd until after
the ring tests.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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drm/radeon/dpm: add late_enable for SI

Make sure interrupts are enabled
before we enable thermal interrupts.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/radeon/dpm: add late_enable for trinity

Need to wait to enable cg and pg until after
ring tests. Also make sure interrupts are enabled
before we enable thermal interrupts.

Signed-off-by: Alex D

drm/radeon/dpm: add late_enable for trinity

Need to wait to enable cg and pg until after
ring tests. Also make sure interrupts are enabled
before we enable thermal interrupts.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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drm/radeon/dpm: add late_enable for sumo

Need to wait to enable cg and pg until after
ring tests. Also make sure interrupts are enabled
before we enable thermal interrupts.

Signed-off-by: Alex Deuc

drm/radeon/dpm: add late_enable for sumo

Need to wait to enable cg and pg until after
ring tests. Also make sure interrupts are enabled
before we enable thermal interrupts.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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drm/radeon/dpm: add late_enable for rv7xx-NI

Make sure interrupts are enabled
before we enable thermal interrupts.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/radeon/dpm: add late_enable for rs780/rs880/rv6xx

Make sure interrupts are enabled before we enable
thermal interrupts.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/radeon/cik: plug in missing blit callback

I implemented support for this, but forget to hook
up the callback so the driver can actually use it.
On asics with a dedicated DMA engine, we use the D

drm/radeon/cik: plug in missing blit callback

I implemented support for this, but forget to hook
up the callback so the driver can actually use it.
On asics with a dedicated DMA engine, we use the DMA
engine for buffer migration so this is just for testing
purposes.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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drm/radeon: hook up backlight functions for CI and KV family.

Fixes crashes when handling atif events due to the lack of a
callback being registered.

Signed-off-by: Samuel Li <samuel.li@amd.com>
Si

drm/radeon: hook up backlight functions for CI and KV family.

Fixes crashes when handling atif events due to the lack of a
callback being registered.

Signed-off-by: Samuel Li <samuel.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

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drm/radeon: fill in radeon_asic_init for hawaii

Fill in gpu details for hawaii.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/radeon: drop CP page table updates & cleanup v2

The DMA ring seems to be stable now.

v2: remove pt_ring_index as well

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: A

drm/radeon: drop CP page table updates & cleanup v2

The DMA ring seems to be stable now.

v2: remove pt_ring_index as well

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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drm/radeon: plug in blit copy routine for SI

Uses CP DMA packet just like previous asics.
Useful for debugging and benchmarking. Uses
same packet format as prior asics.

Signed-off-by: Alex Deucher

drm/radeon: plug in blit copy routine for SI

Uses CP DMA packet just like previous asics.
Useful for debugging and benchmarking. Uses
same packet format as prior asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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drm/radeon: add missing hdmi callbacks for rv6xx

When dpm was merged, I added a new asic struct for
rv6xx, but it never got properly updated when the
hdmi callbacks were added due to the two patch s

drm/radeon: add missing hdmi callbacks for rv6xx

When dpm was merged, I added a new asic struct for
rv6xx, but it never got properly updated when the
hdmi callbacks were added due to the two patch sets
being developed in parallel.

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=69729

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org

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drm/radeon/dpm: add bapm callback for kb/kv

This adds the enable_bapm callback for kb/kv.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/radeon/dpm: add bapm callback for trinity

This adds the enable_bapm callback for trinity.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/radeon/r6xx: add a stubbed out set_uvd_clocks callback

Certain r6xx boards use the same power state for both UVD
and other things. Since we don't support UVD on r6xx boards
at the moment, there

drm/radeon/r6xx: add a stubbed out set_uvd_clocks callback

Certain r6xx boards use the same power state for both UVD
and other things. Since we don't support UVD on r6xx boards
at the moment, there was no callback installed for setting
the UVD clocks, however, on systems that use the same power
state, this leads to a NULL pointer dereference. Fill
in a stubbed out implementation for now to avoid the crash.

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=66963

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: "3.11" <stable@vger.kernel.org>

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drm/radeon: fix typo in PG flags

s/CG/PG/ in the GFX powergating flag name.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/radeon/dpm: implement force performance levels for rs780 (v2)

Allows you to limit the selected power levels via sysfs.

Force the feedback divider to select a power level.

v2: fix checking in r

drm/radeon/dpm: implement force performance levels for rs780 (v2)

Allows you to limit the selected power levels via sysfs.

Force the feedback divider to select a power level.

v2: fix checking in rs780_force_fbdiv,
drop a duplicate divider structure in rs780_dpm_force_performance_level,
Force the voltage level too.

Signed-off-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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drm/radeon: enable mgcg on CIK

Now that the CP is no longer reset and cg is properly
disabled in when appropriate in the dpm code we can
now enable mgcg (medium grained clockgating).

Signed-off-by:

drm/radeon: enable mgcg on CIK

Now that the CP is no longer reset and cg is properly
disabled in when appropriate in the dpm code we can
now enable mgcg (medium grained clockgating).

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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