1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/console.h> 30 #include <drm/drmP.h> 31 #include <drm/drm_crtc_helper.h> 32 #include <drm/radeon_drm.h> 33 #include <linux/vgaarb.h> 34 #include <linux/vga_switcheroo.h> 35 #include "radeon_reg.h" 36 #include "radeon.h" 37 #include "radeon_asic.h" 38 #include "atom.h" 39 40 /* 41 * Registers accessors functions. 42 */ 43 /** 44 * radeon_invalid_rreg - dummy reg read function 45 * 46 * @rdev: radeon device pointer 47 * @reg: offset of register 48 * 49 * Dummy register read function. Used for register blocks 50 * that certain asics don't have (all asics). 51 * Returns the value in the register. 52 */ 53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) 54 { 55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); 56 BUG_ON(1); 57 return 0; 58 } 59 60 /** 61 * radeon_invalid_wreg - dummy reg write function 62 * 63 * @rdev: radeon device pointer 64 * @reg: offset of register 65 * @v: value to write to the register 66 * 67 * Dummy register read function. Used for register blocks 68 * that certain asics don't have (all asics). 69 */ 70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 71 { 72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", 73 reg, v); 74 BUG_ON(1); 75 } 76 77 /** 78 * radeon_register_accessor_init - sets up the register accessor callbacks 79 * 80 * @rdev: radeon device pointer 81 * 82 * Sets up the register accessor callbacks for various register 83 * apertures. Not all asics have all apertures (all asics). 84 */ 85 static void radeon_register_accessor_init(struct radeon_device *rdev) 86 { 87 rdev->mc_rreg = &radeon_invalid_rreg; 88 rdev->mc_wreg = &radeon_invalid_wreg; 89 rdev->pll_rreg = &radeon_invalid_rreg; 90 rdev->pll_wreg = &radeon_invalid_wreg; 91 rdev->pciep_rreg = &radeon_invalid_rreg; 92 rdev->pciep_wreg = &radeon_invalid_wreg; 93 94 /* Don't change order as we are overridding accessor. */ 95 if (rdev->family < CHIP_RV515) { 96 rdev->pcie_reg_mask = 0xff; 97 } else { 98 rdev->pcie_reg_mask = 0x7ff; 99 } 100 /* FIXME: not sure here */ 101 if (rdev->family <= CHIP_R580) { 102 rdev->pll_rreg = &r100_pll_rreg; 103 rdev->pll_wreg = &r100_pll_wreg; 104 } 105 if (rdev->family >= CHIP_R420) { 106 rdev->mc_rreg = &r420_mc_rreg; 107 rdev->mc_wreg = &r420_mc_wreg; 108 } 109 if (rdev->family >= CHIP_RV515) { 110 rdev->mc_rreg = &rv515_mc_rreg; 111 rdev->mc_wreg = &rv515_mc_wreg; 112 } 113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { 114 rdev->mc_rreg = &rs400_mc_rreg; 115 rdev->mc_wreg = &rs400_mc_wreg; 116 } 117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 118 rdev->mc_rreg = &rs690_mc_rreg; 119 rdev->mc_wreg = &rs690_mc_wreg; 120 } 121 if (rdev->family == CHIP_RS600) { 122 rdev->mc_rreg = &rs600_mc_rreg; 123 rdev->mc_wreg = &rs600_mc_wreg; 124 } 125 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { 126 rdev->mc_rreg = &rs780_mc_rreg; 127 rdev->mc_wreg = &rs780_mc_wreg; 128 } 129 130 if (rdev->family >= CHIP_BONAIRE) { 131 rdev->pciep_rreg = &cik_pciep_rreg; 132 rdev->pciep_wreg = &cik_pciep_wreg; 133 } else if (rdev->family >= CHIP_R600) { 134 rdev->pciep_rreg = &r600_pciep_rreg; 135 rdev->pciep_wreg = &r600_pciep_wreg; 136 } 137 } 138 139 140 /* helper to disable agp */ 141 /** 142 * radeon_agp_disable - AGP disable helper function 143 * 144 * @rdev: radeon device pointer 145 * 146 * Removes AGP flags and changes the gart callbacks on AGP 147 * cards when using the internal gart rather than AGP (all asics). 148 */ 149 void radeon_agp_disable(struct radeon_device *rdev) 150 { 151 rdev->flags &= ~RADEON_IS_AGP; 152 if (rdev->family >= CHIP_R600) { 153 DRM_INFO("Forcing AGP to PCIE mode\n"); 154 rdev->flags |= RADEON_IS_PCIE; 155 } else if (rdev->family >= CHIP_RV515 || 156 rdev->family == CHIP_RV380 || 157 rdev->family == CHIP_RV410 || 158 rdev->family == CHIP_R423) { 159 DRM_INFO("Forcing AGP to PCIE mode\n"); 160 rdev->flags |= RADEON_IS_PCIE; 161 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; 162 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; 163 } else { 164 DRM_INFO("Forcing AGP to PCI mode\n"); 165 rdev->flags |= RADEON_IS_PCI; 166 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 167 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 168 } 169 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 170 } 171 172 /* 173 * ASIC 174 */ 175 176 static struct radeon_asic_ring r100_gfx_ring = { 177 .ib_execute = &r100_ring_ib_execute, 178 .emit_fence = &r100_fence_ring_emit, 179 .emit_semaphore = &r100_semaphore_ring_emit, 180 .cs_parse = &r100_cs_parse, 181 .ring_start = &r100_ring_start, 182 .ring_test = &r100_ring_test, 183 .ib_test = &r100_ib_test, 184 .is_lockup = &r100_gpu_is_lockup, 185 .get_rptr = &radeon_ring_generic_get_rptr, 186 .get_wptr = &radeon_ring_generic_get_wptr, 187 .set_wptr = &radeon_ring_generic_set_wptr, 188 }; 189 190 static struct radeon_asic r100_asic = { 191 .init = &r100_init, 192 .fini = &r100_fini, 193 .suspend = &r100_suspend, 194 .resume = &r100_resume, 195 .vga_set_state = &r100_vga_set_state, 196 .asic_reset = &r100_asic_reset, 197 .ioctl_wait_idle = NULL, 198 .gui_idle = &r100_gui_idle, 199 .mc_wait_for_idle = &r100_mc_wait_for_idle, 200 .gart = { 201 .tlb_flush = &r100_pci_gart_tlb_flush, 202 .set_page = &r100_pci_gart_set_page, 203 }, 204 .ring = { 205 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring 206 }, 207 .irq = { 208 .set = &r100_irq_set, 209 .process = &r100_irq_process, 210 }, 211 .display = { 212 .bandwidth_update = &r100_bandwidth_update, 213 .get_vblank_counter = &r100_get_vblank_counter, 214 .wait_for_vblank = &r100_wait_for_vblank, 215 .set_backlight_level = &radeon_legacy_set_backlight_level, 216 .get_backlight_level = &radeon_legacy_get_backlight_level, 217 }, 218 .copy = { 219 .blit = &r100_copy_blit, 220 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 221 .dma = NULL, 222 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 223 .copy = &r100_copy_blit, 224 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 225 }, 226 .surface = { 227 .set_reg = r100_set_surface_reg, 228 .clear_reg = r100_clear_surface_reg, 229 }, 230 .hpd = { 231 .init = &r100_hpd_init, 232 .fini = &r100_hpd_fini, 233 .sense = &r100_hpd_sense, 234 .set_polarity = &r100_hpd_set_polarity, 235 }, 236 .pm = { 237 .misc = &r100_pm_misc, 238 .prepare = &r100_pm_prepare, 239 .finish = &r100_pm_finish, 240 .init_profile = &r100_pm_init_profile, 241 .get_dynpm_state = &r100_pm_get_dynpm_state, 242 .get_engine_clock = &radeon_legacy_get_engine_clock, 243 .set_engine_clock = &radeon_legacy_set_engine_clock, 244 .get_memory_clock = &radeon_legacy_get_memory_clock, 245 .set_memory_clock = NULL, 246 .get_pcie_lanes = NULL, 247 .set_pcie_lanes = NULL, 248 .set_clock_gating = &radeon_legacy_set_clock_gating, 249 }, 250 .pflip = { 251 .pre_page_flip = &r100_pre_page_flip, 252 .page_flip = &r100_page_flip, 253 .post_page_flip = &r100_post_page_flip, 254 }, 255 }; 256 257 static struct radeon_asic r200_asic = { 258 .init = &r100_init, 259 .fini = &r100_fini, 260 .suspend = &r100_suspend, 261 .resume = &r100_resume, 262 .vga_set_state = &r100_vga_set_state, 263 .asic_reset = &r100_asic_reset, 264 .ioctl_wait_idle = NULL, 265 .gui_idle = &r100_gui_idle, 266 .mc_wait_for_idle = &r100_mc_wait_for_idle, 267 .gart = { 268 .tlb_flush = &r100_pci_gart_tlb_flush, 269 .set_page = &r100_pci_gart_set_page, 270 }, 271 .ring = { 272 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring 273 }, 274 .irq = { 275 .set = &r100_irq_set, 276 .process = &r100_irq_process, 277 }, 278 .display = { 279 .bandwidth_update = &r100_bandwidth_update, 280 .get_vblank_counter = &r100_get_vblank_counter, 281 .wait_for_vblank = &r100_wait_for_vblank, 282 .set_backlight_level = &radeon_legacy_set_backlight_level, 283 .get_backlight_level = &radeon_legacy_get_backlight_level, 284 }, 285 .copy = { 286 .blit = &r100_copy_blit, 287 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 288 .dma = &r200_copy_dma, 289 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 290 .copy = &r100_copy_blit, 291 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 292 }, 293 .surface = { 294 .set_reg = r100_set_surface_reg, 295 .clear_reg = r100_clear_surface_reg, 296 }, 297 .hpd = { 298 .init = &r100_hpd_init, 299 .fini = &r100_hpd_fini, 300 .sense = &r100_hpd_sense, 301 .set_polarity = &r100_hpd_set_polarity, 302 }, 303 .pm = { 304 .misc = &r100_pm_misc, 305 .prepare = &r100_pm_prepare, 306 .finish = &r100_pm_finish, 307 .init_profile = &r100_pm_init_profile, 308 .get_dynpm_state = &r100_pm_get_dynpm_state, 309 .get_engine_clock = &radeon_legacy_get_engine_clock, 310 .set_engine_clock = &radeon_legacy_set_engine_clock, 311 .get_memory_clock = &radeon_legacy_get_memory_clock, 312 .set_memory_clock = NULL, 313 .get_pcie_lanes = NULL, 314 .set_pcie_lanes = NULL, 315 .set_clock_gating = &radeon_legacy_set_clock_gating, 316 }, 317 .pflip = { 318 .pre_page_flip = &r100_pre_page_flip, 319 .page_flip = &r100_page_flip, 320 .post_page_flip = &r100_post_page_flip, 321 }, 322 }; 323 324 static struct radeon_asic_ring r300_gfx_ring = { 325 .ib_execute = &r100_ring_ib_execute, 326 .emit_fence = &r300_fence_ring_emit, 327 .emit_semaphore = &r100_semaphore_ring_emit, 328 .cs_parse = &r300_cs_parse, 329 .ring_start = &r300_ring_start, 330 .ring_test = &r100_ring_test, 331 .ib_test = &r100_ib_test, 332 .is_lockup = &r100_gpu_is_lockup, 333 .get_rptr = &radeon_ring_generic_get_rptr, 334 .get_wptr = &radeon_ring_generic_get_wptr, 335 .set_wptr = &radeon_ring_generic_set_wptr, 336 }; 337 338 static struct radeon_asic r300_asic = { 339 .init = &r300_init, 340 .fini = &r300_fini, 341 .suspend = &r300_suspend, 342 .resume = &r300_resume, 343 .vga_set_state = &r100_vga_set_state, 344 .asic_reset = &r300_asic_reset, 345 .ioctl_wait_idle = NULL, 346 .gui_idle = &r100_gui_idle, 347 .mc_wait_for_idle = &r300_mc_wait_for_idle, 348 .gart = { 349 .tlb_flush = &r100_pci_gart_tlb_flush, 350 .set_page = &r100_pci_gart_set_page, 351 }, 352 .ring = { 353 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 354 }, 355 .irq = { 356 .set = &r100_irq_set, 357 .process = &r100_irq_process, 358 }, 359 .display = { 360 .bandwidth_update = &r100_bandwidth_update, 361 .get_vblank_counter = &r100_get_vblank_counter, 362 .wait_for_vblank = &r100_wait_for_vblank, 363 .set_backlight_level = &radeon_legacy_set_backlight_level, 364 .get_backlight_level = &radeon_legacy_get_backlight_level, 365 }, 366 .copy = { 367 .blit = &r100_copy_blit, 368 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 369 .dma = &r200_copy_dma, 370 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 371 .copy = &r100_copy_blit, 372 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 373 }, 374 .surface = { 375 .set_reg = r100_set_surface_reg, 376 .clear_reg = r100_clear_surface_reg, 377 }, 378 .hpd = { 379 .init = &r100_hpd_init, 380 .fini = &r100_hpd_fini, 381 .sense = &r100_hpd_sense, 382 .set_polarity = &r100_hpd_set_polarity, 383 }, 384 .pm = { 385 .misc = &r100_pm_misc, 386 .prepare = &r100_pm_prepare, 387 .finish = &r100_pm_finish, 388 .init_profile = &r100_pm_init_profile, 389 .get_dynpm_state = &r100_pm_get_dynpm_state, 390 .get_engine_clock = &radeon_legacy_get_engine_clock, 391 .set_engine_clock = &radeon_legacy_set_engine_clock, 392 .get_memory_clock = &radeon_legacy_get_memory_clock, 393 .set_memory_clock = NULL, 394 .get_pcie_lanes = &rv370_get_pcie_lanes, 395 .set_pcie_lanes = &rv370_set_pcie_lanes, 396 .set_clock_gating = &radeon_legacy_set_clock_gating, 397 }, 398 .pflip = { 399 .pre_page_flip = &r100_pre_page_flip, 400 .page_flip = &r100_page_flip, 401 .post_page_flip = &r100_post_page_flip, 402 }, 403 }; 404 405 static struct radeon_asic r300_asic_pcie = { 406 .init = &r300_init, 407 .fini = &r300_fini, 408 .suspend = &r300_suspend, 409 .resume = &r300_resume, 410 .vga_set_state = &r100_vga_set_state, 411 .asic_reset = &r300_asic_reset, 412 .ioctl_wait_idle = NULL, 413 .gui_idle = &r100_gui_idle, 414 .mc_wait_for_idle = &r300_mc_wait_for_idle, 415 .gart = { 416 .tlb_flush = &rv370_pcie_gart_tlb_flush, 417 .set_page = &rv370_pcie_gart_set_page, 418 }, 419 .ring = { 420 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 421 }, 422 .irq = { 423 .set = &r100_irq_set, 424 .process = &r100_irq_process, 425 }, 426 .display = { 427 .bandwidth_update = &r100_bandwidth_update, 428 .get_vblank_counter = &r100_get_vblank_counter, 429 .wait_for_vblank = &r100_wait_for_vblank, 430 .set_backlight_level = &radeon_legacy_set_backlight_level, 431 .get_backlight_level = &radeon_legacy_get_backlight_level, 432 }, 433 .copy = { 434 .blit = &r100_copy_blit, 435 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 436 .dma = &r200_copy_dma, 437 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 438 .copy = &r100_copy_blit, 439 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 440 }, 441 .surface = { 442 .set_reg = r100_set_surface_reg, 443 .clear_reg = r100_clear_surface_reg, 444 }, 445 .hpd = { 446 .init = &r100_hpd_init, 447 .fini = &r100_hpd_fini, 448 .sense = &r100_hpd_sense, 449 .set_polarity = &r100_hpd_set_polarity, 450 }, 451 .pm = { 452 .misc = &r100_pm_misc, 453 .prepare = &r100_pm_prepare, 454 .finish = &r100_pm_finish, 455 .init_profile = &r100_pm_init_profile, 456 .get_dynpm_state = &r100_pm_get_dynpm_state, 457 .get_engine_clock = &radeon_legacy_get_engine_clock, 458 .set_engine_clock = &radeon_legacy_set_engine_clock, 459 .get_memory_clock = &radeon_legacy_get_memory_clock, 460 .set_memory_clock = NULL, 461 .get_pcie_lanes = &rv370_get_pcie_lanes, 462 .set_pcie_lanes = &rv370_set_pcie_lanes, 463 .set_clock_gating = &radeon_legacy_set_clock_gating, 464 }, 465 .pflip = { 466 .pre_page_flip = &r100_pre_page_flip, 467 .page_flip = &r100_page_flip, 468 .post_page_flip = &r100_post_page_flip, 469 }, 470 }; 471 472 static struct radeon_asic r420_asic = { 473 .init = &r420_init, 474 .fini = &r420_fini, 475 .suspend = &r420_suspend, 476 .resume = &r420_resume, 477 .vga_set_state = &r100_vga_set_state, 478 .asic_reset = &r300_asic_reset, 479 .ioctl_wait_idle = NULL, 480 .gui_idle = &r100_gui_idle, 481 .mc_wait_for_idle = &r300_mc_wait_for_idle, 482 .gart = { 483 .tlb_flush = &rv370_pcie_gart_tlb_flush, 484 .set_page = &rv370_pcie_gart_set_page, 485 }, 486 .ring = { 487 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 488 }, 489 .irq = { 490 .set = &r100_irq_set, 491 .process = &r100_irq_process, 492 }, 493 .display = { 494 .bandwidth_update = &r100_bandwidth_update, 495 .get_vblank_counter = &r100_get_vblank_counter, 496 .wait_for_vblank = &r100_wait_for_vblank, 497 .set_backlight_level = &atombios_set_backlight_level, 498 .get_backlight_level = &atombios_get_backlight_level, 499 }, 500 .copy = { 501 .blit = &r100_copy_blit, 502 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 503 .dma = &r200_copy_dma, 504 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 505 .copy = &r100_copy_blit, 506 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 507 }, 508 .surface = { 509 .set_reg = r100_set_surface_reg, 510 .clear_reg = r100_clear_surface_reg, 511 }, 512 .hpd = { 513 .init = &r100_hpd_init, 514 .fini = &r100_hpd_fini, 515 .sense = &r100_hpd_sense, 516 .set_polarity = &r100_hpd_set_polarity, 517 }, 518 .pm = { 519 .misc = &r100_pm_misc, 520 .prepare = &r100_pm_prepare, 521 .finish = &r100_pm_finish, 522 .init_profile = &r420_pm_init_profile, 523 .get_dynpm_state = &r100_pm_get_dynpm_state, 524 .get_engine_clock = &radeon_atom_get_engine_clock, 525 .set_engine_clock = &radeon_atom_set_engine_clock, 526 .get_memory_clock = &radeon_atom_get_memory_clock, 527 .set_memory_clock = &radeon_atom_set_memory_clock, 528 .get_pcie_lanes = &rv370_get_pcie_lanes, 529 .set_pcie_lanes = &rv370_set_pcie_lanes, 530 .set_clock_gating = &radeon_atom_set_clock_gating, 531 }, 532 .pflip = { 533 .pre_page_flip = &r100_pre_page_flip, 534 .page_flip = &r100_page_flip, 535 .post_page_flip = &r100_post_page_flip, 536 }, 537 }; 538 539 static struct radeon_asic rs400_asic = { 540 .init = &rs400_init, 541 .fini = &rs400_fini, 542 .suspend = &rs400_suspend, 543 .resume = &rs400_resume, 544 .vga_set_state = &r100_vga_set_state, 545 .asic_reset = &r300_asic_reset, 546 .ioctl_wait_idle = NULL, 547 .gui_idle = &r100_gui_idle, 548 .mc_wait_for_idle = &rs400_mc_wait_for_idle, 549 .gart = { 550 .tlb_flush = &rs400_gart_tlb_flush, 551 .set_page = &rs400_gart_set_page, 552 }, 553 .ring = { 554 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 555 }, 556 .irq = { 557 .set = &r100_irq_set, 558 .process = &r100_irq_process, 559 }, 560 .display = { 561 .bandwidth_update = &r100_bandwidth_update, 562 .get_vblank_counter = &r100_get_vblank_counter, 563 .wait_for_vblank = &r100_wait_for_vblank, 564 .set_backlight_level = &radeon_legacy_set_backlight_level, 565 .get_backlight_level = &radeon_legacy_get_backlight_level, 566 }, 567 .copy = { 568 .blit = &r100_copy_blit, 569 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 570 .dma = &r200_copy_dma, 571 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 572 .copy = &r100_copy_blit, 573 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 574 }, 575 .surface = { 576 .set_reg = r100_set_surface_reg, 577 .clear_reg = r100_clear_surface_reg, 578 }, 579 .hpd = { 580 .init = &r100_hpd_init, 581 .fini = &r100_hpd_fini, 582 .sense = &r100_hpd_sense, 583 .set_polarity = &r100_hpd_set_polarity, 584 }, 585 .pm = { 586 .misc = &r100_pm_misc, 587 .prepare = &r100_pm_prepare, 588 .finish = &r100_pm_finish, 589 .init_profile = &r100_pm_init_profile, 590 .get_dynpm_state = &r100_pm_get_dynpm_state, 591 .get_engine_clock = &radeon_legacy_get_engine_clock, 592 .set_engine_clock = &radeon_legacy_set_engine_clock, 593 .get_memory_clock = &radeon_legacy_get_memory_clock, 594 .set_memory_clock = NULL, 595 .get_pcie_lanes = NULL, 596 .set_pcie_lanes = NULL, 597 .set_clock_gating = &radeon_legacy_set_clock_gating, 598 }, 599 .pflip = { 600 .pre_page_flip = &r100_pre_page_flip, 601 .page_flip = &r100_page_flip, 602 .post_page_flip = &r100_post_page_flip, 603 }, 604 }; 605 606 static struct radeon_asic rs600_asic = { 607 .init = &rs600_init, 608 .fini = &rs600_fini, 609 .suspend = &rs600_suspend, 610 .resume = &rs600_resume, 611 .vga_set_state = &r100_vga_set_state, 612 .asic_reset = &rs600_asic_reset, 613 .ioctl_wait_idle = NULL, 614 .gui_idle = &r100_gui_idle, 615 .mc_wait_for_idle = &rs600_mc_wait_for_idle, 616 .gart = { 617 .tlb_flush = &rs600_gart_tlb_flush, 618 .set_page = &rs600_gart_set_page, 619 }, 620 .ring = { 621 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 622 }, 623 .irq = { 624 .set = &rs600_irq_set, 625 .process = &rs600_irq_process, 626 }, 627 .display = { 628 .bandwidth_update = &rs600_bandwidth_update, 629 .get_vblank_counter = &rs600_get_vblank_counter, 630 .wait_for_vblank = &avivo_wait_for_vblank, 631 .set_backlight_level = &atombios_set_backlight_level, 632 .get_backlight_level = &atombios_get_backlight_level, 633 .hdmi_enable = &r600_hdmi_enable, 634 .hdmi_setmode = &r600_hdmi_setmode, 635 }, 636 .copy = { 637 .blit = &r100_copy_blit, 638 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 639 .dma = &r200_copy_dma, 640 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 641 .copy = &r100_copy_blit, 642 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 643 }, 644 .surface = { 645 .set_reg = r100_set_surface_reg, 646 .clear_reg = r100_clear_surface_reg, 647 }, 648 .hpd = { 649 .init = &rs600_hpd_init, 650 .fini = &rs600_hpd_fini, 651 .sense = &rs600_hpd_sense, 652 .set_polarity = &rs600_hpd_set_polarity, 653 }, 654 .pm = { 655 .misc = &rs600_pm_misc, 656 .prepare = &rs600_pm_prepare, 657 .finish = &rs600_pm_finish, 658 .init_profile = &r420_pm_init_profile, 659 .get_dynpm_state = &r100_pm_get_dynpm_state, 660 .get_engine_clock = &radeon_atom_get_engine_clock, 661 .set_engine_clock = &radeon_atom_set_engine_clock, 662 .get_memory_clock = &radeon_atom_get_memory_clock, 663 .set_memory_clock = &radeon_atom_set_memory_clock, 664 .get_pcie_lanes = NULL, 665 .set_pcie_lanes = NULL, 666 .set_clock_gating = &radeon_atom_set_clock_gating, 667 }, 668 .pflip = { 669 .pre_page_flip = &rs600_pre_page_flip, 670 .page_flip = &rs600_page_flip, 671 .post_page_flip = &rs600_post_page_flip, 672 }, 673 }; 674 675 static struct radeon_asic rs690_asic = { 676 .init = &rs690_init, 677 .fini = &rs690_fini, 678 .suspend = &rs690_suspend, 679 .resume = &rs690_resume, 680 .vga_set_state = &r100_vga_set_state, 681 .asic_reset = &rs600_asic_reset, 682 .ioctl_wait_idle = NULL, 683 .gui_idle = &r100_gui_idle, 684 .mc_wait_for_idle = &rs690_mc_wait_for_idle, 685 .gart = { 686 .tlb_flush = &rs400_gart_tlb_flush, 687 .set_page = &rs400_gart_set_page, 688 }, 689 .ring = { 690 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 691 }, 692 .irq = { 693 .set = &rs600_irq_set, 694 .process = &rs600_irq_process, 695 }, 696 .display = { 697 .get_vblank_counter = &rs600_get_vblank_counter, 698 .bandwidth_update = &rs690_bandwidth_update, 699 .wait_for_vblank = &avivo_wait_for_vblank, 700 .set_backlight_level = &atombios_set_backlight_level, 701 .get_backlight_level = &atombios_get_backlight_level, 702 .hdmi_enable = &r600_hdmi_enable, 703 .hdmi_setmode = &r600_hdmi_setmode, 704 }, 705 .copy = { 706 .blit = &r100_copy_blit, 707 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 708 .dma = &r200_copy_dma, 709 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 710 .copy = &r200_copy_dma, 711 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 712 }, 713 .surface = { 714 .set_reg = r100_set_surface_reg, 715 .clear_reg = r100_clear_surface_reg, 716 }, 717 .hpd = { 718 .init = &rs600_hpd_init, 719 .fini = &rs600_hpd_fini, 720 .sense = &rs600_hpd_sense, 721 .set_polarity = &rs600_hpd_set_polarity, 722 }, 723 .pm = { 724 .misc = &rs600_pm_misc, 725 .prepare = &rs600_pm_prepare, 726 .finish = &rs600_pm_finish, 727 .init_profile = &r420_pm_init_profile, 728 .get_dynpm_state = &r100_pm_get_dynpm_state, 729 .get_engine_clock = &radeon_atom_get_engine_clock, 730 .set_engine_clock = &radeon_atom_set_engine_clock, 731 .get_memory_clock = &radeon_atom_get_memory_clock, 732 .set_memory_clock = &radeon_atom_set_memory_clock, 733 .get_pcie_lanes = NULL, 734 .set_pcie_lanes = NULL, 735 .set_clock_gating = &radeon_atom_set_clock_gating, 736 }, 737 .pflip = { 738 .pre_page_flip = &rs600_pre_page_flip, 739 .page_flip = &rs600_page_flip, 740 .post_page_flip = &rs600_post_page_flip, 741 }, 742 }; 743 744 static struct radeon_asic rv515_asic = { 745 .init = &rv515_init, 746 .fini = &rv515_fini, 747 .suspend = &rv515_suspend, 748 .resume = &rv515_resume, 749 .vga_set_state = &r100_vga_set_state, 750 .asic_reset = &rs600_asic_reset, 751 .ioctl_wait_idle = NULL, 752 .gui_idle = &r100_gui_idle, 753 .mc_wait_for_idle = &rv515_mc_wait_for_idle, 754 .gart = { 755 .tlb_flush = &rv370_pcie_gart_tlb_flush, 756 .set_page = &rv370_pcie_gart_set_page, 757 }, 758 .ring = { 759 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 760 }, 761 .irq = { 762 .set = &rs600_irq_set, 763 .process = &rs600_irq_process, 764 }, 765 .display = { 766 .get_vblank_counter = &rs600_get_vblank_counter, 767 .bandwidth_update = &rv515_bandwidth_update, 768 .wait_for_vblank = &avivo_wait_for_vblank, 769 .set_backlight_level = &atombios_set_backlight_level, 770 .get_backlight_level = &atombios_get_backlight_level, 771 }, 772 .copy = { 773 .blit = &r100_copy_blit, 774 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 775 .dma = &r200_copy_dma, 776 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 777 .copy = &r100_copy_blit, 778 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 779 }, 780 .surface = { 781 .set_reg = r100_set_surface_reg, 782 .clear_reg = r100_clear_surface_reg, 783 }, 784 .hpd = { 785 .init = &rs600_hpd_init, 786 .fini = &rs600_hpd_fini, 787 .sense = &rs600_hpd_sense, 788 .set_polarity = &rs600_hpd_set_polarity, 789 }, 790 .pm = { 791 .misc = &rs600_pm_misc, 792 .prepare = &rs600_pm_prepare, 793 .finish = &rs600_pm_finish, 794 .init_profile = &r420_pm_init_profile, 795 .get_dynpm_state = &r100_pm_get_dynpm_state, 796 .get_engine_clock = &radeon_atom_get_engine_clock, 797 .set_engine_clock = &radeon_atom_set_engine_clock, 798 .get_memory_clock = &radeon_atom_get_memory_clock, 799 .set_memory_clock = &radeon_atom_set_memory_clock, 800 .get_pcie_lanes = &rv370_get_pcie_lanes, 801 .set_pcie_lanes = &rv370_set_pcie_lanes, 802 .set_clock_gating = &radeon_atom_set_clock_gating, 803 }, 804 .pflip = { 805 .pre_page_flip = &rs600_pre_page_flip, 806 .page_flip = &rs600_page_flip, 807 .post_page_flip = &rs600_post_page_flip, 808 }, 809 }; 810 811 static struct radeon_asic r520_asic = { 812 .init = &r520_init, 813 .fini = &rv515_fini, 814 .suspend = &rv515_suspend, 815 .resume = &r520_resume, 816 .vga_set_state = &r100_vga_set_state, 817 .asic_reset = &rs600_asic_reset, 818 .ioctl_wait_idle = NULL, 819 .gui_idle = &r100_gui_idle, 820 .mc_wait_for_idle = &r520_mc_wait_for_idle, 821 .gart = { 822 .tlb_flush = &rv370_pcie_gart_tlb_flush, 823 .set_page = &rv370_pcie_gart_set_page, 824 }, 825 .ring = { 826 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 827 }, 828 .irq = { 829 .set = &rs600_irq_set, 830 .process = &rs600_irq_process, 831 }, 832 .display = { 833 .bandwidth_update = &rv515_bandwidth_update, 834 .get_vblank_counter = &rs600_get_vblank_counter, 835 .wait_for_vblank = &avivo_wait_for_vblank, 836 .set_backlight_level = &atombios_set_backlight_level, 837 .get_backlight_level = &atombios_get_backlight_level, 838 }, 839 .copy = { 840 .blit = &r100_copy_blit, 841 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 842 .dma = &r200_copy_dma, 843 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 844 .copy = &r100_copy_blit, 845 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 846 }, 847 .surface = { 848 .set_reg = r100_set_surface_reg, 849 .clear_reg = r100_clear_surface_reg, 850 }, 851 .hpd = { 852 .init = &rs600_hpd_init, 853 .fini = &rs600_hpd_fini, 854 .sense = &rs600_hpd_sense, 855 .set_polarity = &rs600_hpd_set_polarity, 856 }, 857 .pm = { 858 .misc = &rs600_pm_misc, 859 .prepare = &rs600_pm_prepare, 860 .finish = &rs600_pm_finish, 861 .init_profile = &r420_pm_init_profile, 862 .get_dynpm_state = &r100_pm_get_dynpm_state, 863 .get_engine_clock = &radeon_atom_get_engine_clock, 864 .set_engine_clock = &radeon_atom_set_engine_clock, 865 .get_memory_clock = &radeon_atom_get_memory_clock, 866 .set_memory_clock = &radeon_atom_set_memory_clock, 867 .get_pcie_lanes = &rv370_get_pcie_lanes, 868 .set_pcie_lanes = &rv370_set_pcie_lanes, 869 .set_clock_gating = &radeon_atom_set_clock_gating, 870 }, 871 .pflip = { 872 .pre_page_flip = &rs600_pre_page_flip, 873 .page_flip = &rs600_page_flip, 874 .post_page_flip = &rs600_post_page_flip, 875 }, 876 }; 877 878 static struct radeon_asic_ring r600_gfx_ring = { 879 .ib_execute = &r600_ring_ib_execute, 880 .emit_fence = &r600_fence_ring_emit, 881 .emit_semaphore = &r600_semaphore_ring_emit, 882 .cs_parse = &r600_cs_parse, 883 .ring_test = &r600_ring_test, 884 .ib_test = &r600_ib_test, 885 .is_lockup = &r600_gfx_is_lockup, 886 .get_rptr = &radeon_ring_generic_get_rptr, 887 .get_wptr = &radeon_ring_generic_get_wptr, 888 .set_wptr = &radeon_ring_generic_set_wptr, 889 }; 890 891 static struct radeon_asic_ring r600_dma_ring = { 892 .ib_execute = &r600_dma_ring_ib_execute, 893 .emit_fence = &r600_dma_fence_ring_emit, 894 .emit_semaphore = &r600_dma_semaphore_ring_emit, 895 .cs_parse = &r600_dma_cs_parse, 896 .ring_test = &r600_dma_ring_test, 897 .ib_test = &r600_dma_ib_test, 898 .is_lockup = &r600_dma_is_lockup, 899 .get_rptr = &r600_dma_get_rptr, 900 .get_wptr = &r600_dma_get_wptr, 901 .set_wptr = &r600_dma_set_wptr, 902 }; 903 904 static struct radeon_asic r600_asic = { 905 .init = &r600_init, 906 .fini = &r600_fini, 907 .suspend = &r600_suspend, 908 .resume = &r600_resume, 909 .vga_set_state = &r600_vga_set_state, 910 .asic_reset = &r600_asic_reset, 911 .ioctl_wait_idle = r600_ioctl_wait_idle, 912 .gui_idle = &r600_gui_idle, 913 .mc_wait_for_idle = &r600_mc_wait_for_idle, 914 .get_xclk = &r600_get_xclk, 915 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 916 .gart = { 917 .tlb_flush = &r600_pcie_gart_tlb_flush, 918 .set_page = &rs600_gart_set_page, 919 }, 920 .ring = { 921 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 922 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 923 }, 924 .irq = { 925 .set = &r600_irq_set, 926 .process = &r600_irq_process, 927 }, 928 .display = { 929 .bandwidth_update = &rv515_bandwidth_update, 930 .get_vblank_counter = &rs600_get_vblank_counter, 931 .wait_for_vblank = &avivo_wait_for_vblank, 932 .set_backlight_level = &atombios_set_backlight_level, 933 .get_backlight_level = &atombios_get_backlight_level, 934 .hdmi_enable = &r600_hdmi_enable, 935 .hdmi_setmode = &r600_hdmi_setmode, 936 }, 937 .copy = { 938 .blit = &r600_copy_cpdma, 939 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 940 .dma = &r600_copy_dma, 941 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 942 .copy = &r600_copy_cpdma, 943 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 944 }, 945 .surface = { 946 .set_reg = r600_set_surface_reg, 947 .clear_reg = r600_clear_surface_reg, 948 }, 949 .hpd = { 950 .init = &r600_hpd_init, 951 .fini = &r600_hpd_fini, 952 .sense = &r600_hpd_sense, 953 .set_polarity = &r600_hpd_set_polarity, 954 }, 955 .pm = { 956 .misc = &r600_pm_misc, 957 .prepare = &rs600_pm_prepare, 958 .finish = &rs600_pm_finish, 959 .init_profile = &r600_pm_init_profile, 960 .get_dynpm_state = &r600_pm_get_dynpm_state, 961 .get_engine_clock = &radeon_atom_get_engine_clock, 962 .set_engine_clock = &radeon_atom_set_engine_clock, 963 .get_memory_clock = &radeon_atom_get_memory_clock, 964 .set_memory_clock = &radeon_atom_set_memory_clock, 965 .get_pcie_lanes = &r600_get_pcie_lanes, 966 .set_pcie_lanes = &r600_set_pcie_lanes, 967 .set_clock_gating = NULL, 968 .get_temperature = &rv6xx_get_temp, 969 }, 970 .pflip = { 971 .pre_page_flip = &rs600_pre_page_flip, 972 .page_flip = &rs600_page_flip, 973 .post_page_flip = &rs600_post_page_flip, 974 }, 975 }; 976 977 static struct radeon_asic rv6xx_asic = { 978 .init = &r600_init, 979 .fini = &r600_fini, 980 .suspend = &r600_suspend, 981 .resume = &r600_resume, 982 .vga_set_state = &r600_vga_set_state, 983 .asic_reset = &r600_asic_reset, 984 .ioctl_wait_idle = r600_ioctl_wait_idle, 985 .gui_idle = &r600_gui_idle, 986 .mc_wait_for_idle = &r600_mc_wait_for_idle, 987 .get_xclk = &r600_get_xclk, 988 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 989 .gart = { 990 .tlb_flush = &r600_pcie_gart_tlb_flush, 991 .set_page = &rs600_gart_set_page, 992 }, 993 .ring = { 994 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 995 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 996 }, 997 .irq = { 998 .set = &r600_irq_set, 999 .process = &r600_irq_process, 1000 }, 1001 .display = { 1002 .bandwidth_update = &rv515_bandwidth_update, 1003 .get_vblank_counter = &rs600_get_vblank_counter, 1004 .wait_for_vblank = &avivo_wait_for_vblank, 1005 .set_backlight_level = &atombios_set_backlight_level, 1006 .get_backlight_level = &atombios_get_backlight_level, 1007 .hdmi_enable = &r600_hdmi_enable, 1008 .hdmi_setmode = &r600_hdmi_setmode, 1009 }, 1010 .copy = { 1011 .blit = &r600_copy_cpdma, 1012 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1013 .dma = &r600_copy_dma, 1014 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1015 .copy = &r600_copy_cpdma, 1016 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1017 }, 1018 .surface = { 1019 .set_reg = r600_set_surface_reg, 1020 .clear_reg = r600_clear_surface_reg, 1021 }, 1022 .hpd = { 1023 .init = &r600_hpd_init, 1024 .fini = &r600_hpd_fini, 1025 .sense = &r600_hpd_sense, 1026 .set_polarity = &r600_hpd_set_polarity, 1027 }, 1028 .pm = { 1029 .misc = &r600_pm_misc, 1030 .prepare = &rs600_pm_prepare, 1031 .finish = &rs600_pm_finish, 1032 .init_profile = &r600_pm_init_profile, 1033 .get_dynpm_state = &r600_pm_get_dynpm_state, 1034 .get_engine_clock = &radeon_atom_get_engine_clock, 1035 .set_engine_clock = &radeon_atom_set_engine_clock, 1036 .get_memory_clock = &radeon_atom_get_memory_clock, 1037 .set_memory_clock = &radeon_atom_set_memory_clock, 1038 .get_pcie_lanes = &r600_get_pcie_lanes, 1039 .set_pcie_lanes = &r600_set_pcie_lanes, 1040 .set_clock_gating = NULL, 1041 .get_temperature = &rv6xx_get_temp, 1042 .set_uvd_clocks = &r600_set_uvd_clocks, 1043 }, 1044 .dpm = { 1045 .init = &rv6xx_dpm_init, 1046 .setup_asic = &rv6xx_setup_asic, 1047 .enable = &rv6xx_dpm_enable, 1048 .late_enable = &r600_dpm_late_enable, 1049 .disable = &rv6xx_dpm_disable, 1050 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1051 .set_power_state = &rv6xx_dpm_set_power_state, 1052 .post_set_power_state = &r600_dpm_post_set_power_state, 1053 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed, 1054 .fini = &rv6xx_dpm_fini, 1055 .get_sclk = &rv6xx_dpm_get_sclk, 1056 .get_mclk = &rv6xx_dpm_get_mclk, 1057 .print_power_state = &rv6xx_dpm_print_power_state, 1058 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level, 1059 .force_performance_level = &rv6xx_dpm_force_performance_level, 1060 }, 1061 .pflip = { 1062 .pre_page_flip = &rs600_pre_page_flip, 1063 .page_flip = &rs600_page_flip, 1064 .post_page_flip = &rs600_post_page_flip, 1065 }, 1066 }; 1067 1068 static struct radeon_asic rs780_asic = { 1069 .init = &r600_init, 1070 .fini = &r600_fini, 1071 .suspend = &r600_suspend, 1072 .resume = &r600_resume, 1073 .vga_set_state = &r600_vga_set_state, 1074 .asic_reset = &r600_asic_reset, 1075 .ioctl_wait_idle = r600_ioctl_wait_idle, 1076 .gui_idle = &r600_gui_idle, 1077 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1078 .get_xclk = &r600_get_xclk, 1079 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1080 .gart = { 1081 .tlb_flush = &r600_pcie_gart_tlb_flush, 1082 .set_page = &rs600_gart_set_page, 1083 }, 1084 .ring = { 1085 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1086 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1087 }, 1088 .irq = { 1089 .set = &r600_irq_set, 1090 .process = &r600_irq_process, 1091 }, 1092 .display = { 1093 .bandwidth_update = &rs690_bandwidth_update, 1094 .get_vblank_counter = &rs600_get_vblank_counter, 1095 .wait_for_vblank = &avivo_wait_for_vblank, 1096 .set_backlight_level = &atombios_set_backlight_level, 1097 .get_backlight_level = &atombios_get_backlight_level, 1098 .hdmi_enable = &r600_hdmi_enable, 1099 .hdmi_setmode = &r600_hdmi_setmode, 1100 }, 1101 .copy = { 1102 .blit = &r600_copy_cpdma, 1103 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1104 .dma = &r600_copy_dma, 1105 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1106 .copy = &r600_copy_cpdma, 1107 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1108 }, 1109 .surface = { 1110 .set_reg = r600_set_surface_reg, 1111 .clear_reg = r600_clear_surface_reg, 1112 }, 1113 .hpd = { 1114 .init = &r600_hpd_init, 1115 .fini = &r600_hpd_fini, 1116 .sense = &r600_hpd_sense, 1117 .set_polarity = &r600_hpd_set_polarity, 1118 }, 1119 .pm = { 1120 .misc = &r600_pm_misc, 1121 .prepare = &rs600_pm_prepare, 1122 .finish = &rs600_pm_finish, 1123 .init_profile = &rs780_pm_init_profile, 1124 .get_dynpm_state = &r600_pm_get_dynpm_state, 1125 .get_engine_clock = &radeon_atom_get_engine_clock, 1126 .set_engine_clock = &radeon_atom_set_engine_clock, 1127 .get_memory_clock = NULL, 1128 .set_memory_clock = NULL, 1129 .get_pcie_lanes = NULL, 1130 .set_pcie_lanes = NULL, 1131 .set_clock_gating = NULL, 1132 .get_temperature = &rv6xx_get_temp, 1133 .set_uvd_clocks = &r600_set_uvd_clocks, 1134 }, 1135 .dpm = { 1136 .init = &rs780_dpm_init, 1137 .setup_asic = &rs780_dpm_setup_asic, 1138 .enable = &rs780_dpm_enable, 1139 .late_enable = &r600_dpm_late_enable, 1140 .disable = &rs780_dpm_disable, 1141 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1142 .set_power_state = &rs780_dpm_set_power_state, 1143 .post_set_power_state = &r600_dpm_post_set_power_state, 1144 .display_configuration_changed = &rs780_dpm_display_configuration_changed, 1145 .fini = &rs780_dpm_fini, 1146 .get_sclk = &rs780_dpm_get_sclk, 1147 .get_mclk = &rs780_dpm_get_mclk, 1148 .print_power_state = &rs780_dpm_print_power_state, 1149 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level, 1150 .force_performance_level = &rs780_dpm_force_performance_level, 1151 }, 1152 .pflip = { 1153 .pre_page_flip = &rs600_pre_page_flip, 1154 .page_flip = &rs600_page_flip, 1155 .post_page_flip = &rs600_post_page_flip, 1156 }, 1157 }; 1158 1159 static struct radeon_asic_ring rv770_uvd_ring = { 1160 .ib_execute = &uvd_v1_0_ib_execute, 1161 .emit_fence = &uvd_v2_2_fence_emit, 1162 .emit_semaphore = &uvd_v1_0_semaphore_emit, 1163 .cs_parse = &radeon_uvd_cs_parse, 1164 .ring_test = &uvd_v1_0_ring_test, 1165 .ib_test = &uvd_v1_0_ib_test, 1166 .is_lockup = &radeon_ring_test_lockup, 1167 .get_rptr = &uvd_v1_0_get_rptr, 1168 .get_wptr = &uvd_v1_0_get_wptr, 1169 .set_wptr = &uvd_v1_0_set_wptr, 1170 }; 1171 1172 static struct radeon_asic rv770_asic = { 1173 .init = &rv770_init, 1174 .fini = &rv770_fini, 1175 .suspend = &rv770_suspend, 1176 .resume = &rv770_resume, 1177 .asic_reset = &r600_asic_reset, 1178 .vga_set_state = &r600_vga_set_state, 1179 .ioctl_wait_idle = r600_ioctl_wait_idle, 1180 .gui_idle = &r600_gui_idle, 1181 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1182 .get_xclk = &rv770_get_xclk, 1183 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1184 .gart = { 1185 .tlb_flush = &r600_pcie_gart_tlb_flush, 1186 .set_page = &rs600_gart_set_page, 1187 }, 1188 .ring = { 1189 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1190 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1191 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1192 }, 1193 .irq = { 1194 .set = &r600_irq_set, 1195 .process = &r600_irq_process, 1196 }, 1197 .display = { 1198 .bandwidth_update = &rv515_bandwidth_update, 1199 .get_vblank_counter = &rs600_get_vblank_counter, 1200 .wait_for_vblank = &avivo_wait_for_vblank, 1201 .set_backlight_level = &atombios_set_backlight_level, 1202 .get_backlight_level = &atombios_get_backlight_level, 1203 .hdmi_enable = &r600_hdmi_enable, 1204 .hdmi_setmode = &r600_hdmi_setmode, 1205 }, 1206 .copy = { 1207 .blit = &r600_copy_cpdma, 1208 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1209 .dma = &rv770_copy_dma, 1210 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1211 .copy = &rv770_copy_dma, 1212 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1213 }, 1214 .surface = { 1215 .set_reg = r600_set_surface_reg, 1216 .clear_reg = r600_clear_surface_reg, 1217 }, 1218 .hpd = { 1219 .init = &r600_hpd_init, 1220 .fini = &r600_hpd_fini, 1221 .sense = &r600_hpd_sense, 1222 .set_polarity = &r600_hpd_set_polarity, 1223 }, 1224 .pm = { 1225 .misc = &rv770_pm_misc, 1226 .prepare = &rs600_pm_prepare, 1227 .finish = &rs600_pm_finish, 1228 .init_profile = &r600_pm_init_profile, 1229 .get_dynpm_state = &r600_pm_get_dynpm_state, 1230 .get_engine_clock = &radeon_atom_get_engine_clock, 1231 .set_engine_clock = &radeon_atom_set_engine_clock, 1232 .get_memory_clock = &radeon_atom_get_memory_clock, 1233 .set_memory_clock = &radeon_atom_set_memory_clock, 1234 .get_pcie_lanes = &r600_get_pcie_lanes, 1235 .set_pcie_lanes = &r600_set_pcie_lanes, 1236 .set_clock_gating = &radeon_atom_set_clock_gating, 1237 .set_uvd_clocks = &rv770_set_uvd_clocks, 1238 .get_temperature = &rv770_get_temp, 1239 }, 1240 .dpm = { 1241 .init = &rv770_dpm_init, 1242 .setup_asic = &rv770_dpm_setup_asic, 1243 .enable = &rv770_dpm_enable, 1244 .disable = &rv770_dpm_disable, 1245 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1246 .set_power_state = &rv770_dpm_set_power_state, 1247 .post_set_power_state = &r600_dpm_post_set_power_state, 1248 .display_configuration_changed = &rv770_dpm_display_configuration_changed, 1249 .fini = &rv770_dpm_fini, 1250 .get_sclk = &rv770_dpm_get_sclk, 1251 .get_mclk = &rv770_dpm_get_mclk, 1252 .print_power_state = &rv770_dpm_print_power_state, 1253 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1254 .force_performance_level = &rv770_dpm_force_performance_level, 1255 .vblank_too_short = &rv770_dpm_vblank_too_short, 1256 }, 1257 .pflip = { 1258 .pre_page_flip = &rs600_pre_page_flip, 1259 .page_flip = &rv770_page_flip, 1260 .post_page_flip = &rs600_post_page_flip, 1261 }, 1262 }; 1263 1264 static struct radeon_asic_ring evergreen_gfx_ring = { 1265 .ib_execute = &evergreen_ring_ib_execute, 1266 .emit_fence = &r600_fence_ring_emit, 1267 .emit_semaphore = &r600_semaphore_ring_emit, 1268 .cs_parse = &evergreen_cs_parse, 1269 .ring_test = &r600_ring_test, 1270 .ib_test = &r600_ib_test, 1271 .is_lockup = &evergreen_gfx_is_lockup, 1272 .get_rptr = &radeon_ring_generic_get_rptr, 1273 .get_wptr = &radeon_ring_generic_get_wptr, 1274 .set_wptr = &radeon_ring_generic_set_wptr, 1275 }; 1276 1277 static struct radeon_asic_ring evergreen_dma_ring = { 1278 .ib_execute = &evergreen_dma_ring_ib_execute, 1279 .emit_fence = &evergreen_dma_fence_ring_emit, 1280 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1281 .cs_parse = &evergreen_dma_cs_parse, 1282 .ring_test = &r600_dma_ring_test, 1283 .ib_test = &r600_dma_ib_test, 1284 .is_lockup = &evergreen_dma_is_lockup, 1285 .get_rptr = &r600_dma_get_rptr, 1286 .get_wptr = &r600_dma_get_wptr, 1287 .set_wptr = &r600_dma_set_wptr, 1288 }; 1289 1290 static struct radeon_asic evergreen_asic = { 1291 .init = &evergreen_init, 1292 .fini = &evergreen_fini, 1293 .suspend = &evergreen_suspend, 1294 .resume = &evergreen_resume, 1295 .asic_reset = &evergreen_asic_reset, 1296 .vga_set_state = &r600_vga_set_state, 1297 .ioctl_wait_idle = r600_ioctl_wait_idle, 1298 .gui_idle = &r600_gui_idle, 1299 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1300 .get_xclk = &rv770_get_xclk, 1301 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1302 .gart = { 1303 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1304 .set_page = &rs600_gart_set_page, 1305 }, 1306 .ring = { 1307 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1308 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1309 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1310 }, 1311 .irq = { 1312 .set = &evergreen_irq_set, 1313 .process = &evergreen_irq_process, 1314 }, 1315 .display = { 1316 .bandwidth_update = &evergreen_bandwidth_update, 1317 .get_vblank_counter = &evergreen_get_vblank_counter, 1318 .wait_for_vblank = &dce4_wait_for_vblank, 1319 .set_backlight_level = &atombios_set_backlight_level, 1320 .get_backlight_level = &atombios_get_backlight_level, 1321 .hdmi_enable = &evergreen_hdmi_enable, 1322 .hdmi_setmode = &evergreen_hdmi_setmode, 1323 }, 1324 .copy = { 1325 .blit = &r600_copy_cpdma, 1326 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1327 .dma = &evergreen_copy_dma, 1328 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1329 .copy = &evergreen_copy_dma, 1330 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1331 }, 1332 .surface = { 1333 .set_reg = r600_set_surface_reg, 1334 .clear_reg = r600_clear_surface_reg, 1335 }, 1336 .hpd = { 1337 .init = &evergreen_hpd_init, 1338 .fini = &evergreen_hpd_fini, 1339 .sense = &evergreen_hpd_sense, 1340 .set_polarity = &evergreen_hpd_set_polarity, 1341 }, 1342 .pm = { 1343 .misc = &evergreen_pm_misc, 1344 .prepare = &evergreen_pm_prepare, 1345 .finish = &evergreen_pm_finish, 1346 .init_profile = &r600_pm_init_profile, 1347 .get_dynpm_state = &r600_pm_get_dynpm_state, 1348 .get_engine_clock = &radeon_atom_get_engine_clock, 1349 .set_engine_clock = &radeon_atom_set_engine_clock, 1350 .get_memory_clock = &radeon_atom_get_memory_clock, 1351 .set_memory_clock = &radeon_atom_set_memory_clock, 1352 .get_pcie_lanes = &r600_get_pcie_lanes, 1353 .set_pcie_lanes = &r600_set_pcie_lanes, 1354 .set_clock_gating = NULL, 1355 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1356 .get_temperature = &evergreen_get_temp, 1357 }, 1358 .dpm = { 1359 .init = &cypress_dpm_init, 1360 .setup_asic = &cypress_dpm_setup_asic, 1361 .enable = &cypress_dpm_enable, 1362 .disable = &cypress_dpm_disable, 1363 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1364 .set_power_state = &cypress_dpm_set_power_state, 1365 .post_set_power_state = &r600_dpm_post_set_power_state, 1366 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1367 .fini = &cypress_dpm_fini, 1368 .get_sclk = &rv770_dpm_get_sclk, 1369 .get_mclk = &rv770_dpm_get_mclk, 1370 .print_power_state = &rv770_dpm_print_power_state, 1371 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1372 .force_performance_level = &rv770_dpm_force_performance_level, 1373 .vblank_too_short = &cypress_dpm_vblank_too_short, 1374 }, 1375 .pflip = { 1376 .pre_page_flip = &evergreen_pre_page_flip, 1377 .page_flip = &evergreen_page_flip, 1378 .post_page_flip = &evergreen_post_page_flip, 1379 }, 1380 }; 1381 1382 static struct radeon_asic sumo_asic = { 1383 .init = &evergreen_init, 1384 .fini = &evergreen_fini, 1385 .suspend = &evergreen_suspend, 1386 .resume = &evergreen_resume, 1387 .asic_reset = &evergreen_asic_reset, 1388 .vga_set_state = &r600_vga_set_state, 1389 .ioctl_wait_idle = r600_ioctl_wait_idle, 1390 .gui_idle = &r600_gui_idle, 1391 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1392 .get_xclk = &r600_get_xclk, 1393 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1394 .gart = { 1395 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1396 .set_page = &rs600_gart_set_page, 1397 }, 1398 .ring = { 1399 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1400 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1401 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1402 }, 1403 .irq = { 1404 .set = &evergreen_irq_set, 1405 .process = &evergreen_irq_process, 1406 }, 1407 .display = { 1408 .bandwidth_update = &evergreen_bandwidth_update, 1409 .get_vblank_counter = &evergreen_get_vblank_counter, 1410 .wait_for_vblank = &dce4_wait_for_vblank, 1411 .set_backlight_level = &atombios_set_backlight_level, 1412 .get_backlight_level = &atombios_get_backlight_level, 1413 .hdmi_enable = &evergreen_hdmi_enable, 1414 .hdmi_setmode = &evergreen_hdmi_setmode, 1415 }, 1416 .copy = { 1417 .blit = &r600_copy_cpdma, 1418 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1419 .dma = &evergreen_copy_dma, 1420 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1421 .copy = &evergreen_copy_dma, 1422 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1423 }, 1424 .surface = { 1425 .set_reg = r600_set_surface_reg, 1426 .clear_reg = r600_clear_surface_reg, 1427 }, 1428 .hpd = { 1429 .init = &evergreen_hpd_init, 1430 .fini = &evergreen_hpd_fini, 1431 .sense = &evergreen_hpd_sense, 1432 .set_polarity = &evergreen_hpd_set_polarity, 1433 }, 1434 .pm = { 1435 .misc = &evergreen_pm_misc, 1436 .prepare = &evergreen_pm_prepare, 1437 .finish = &evergreen_pm_finish, 1438 .init_profile = &sumo_pm_init_profile, 1439 .get_dynpm_state = &r600_pm_get_dynpm_state, 1440 .get_engine_clock = &radeon_atom_get_engine_clock, 1441 .set_engine_clock = &radeon_atom_set_engine_clock, 1442 .get_memory_clock = NULL, 1443 .set_memory_clock = NULL, 1444 .get_pcie_lanes = NULL, 1445 .set_pcie_lanes = NULL, 1446 .set_clock_gating = NULL, 1447 .set_uvd_clocks = &sumo_set_uvd_clocks, 1448 .get_temperature = &sumo_get_temp, 1449 }, 1450 .dpm = { 1451 .init = &sumo_dpm_init, 1452 .setup_asic = &sumo_dpm_setup_asic, 1453 .enable = &sumo_dpm_enable, 1454 .disable = &sumo_dpm_disable, 1455 .pre_set_power_state = &sumo_dpm_pre_set_power_state, 1456 .set_power_state = &sumo_dpm_set_power_state, 1457 .post_set_power_state = &sumo_dpm_post_set_power_state, 1458 .display_configuration_changed = &sumo_dpm_display_configuration_changed, 1459 .fini = &sumo_dpm_fini, 1460 .get_sclk = &sumo_dpm_get_sclk, 1461 .get_mclk = &sumo_dpm_get_mclk, 1462 .print_power_state = &sumo_dpm_print_power_state, 1463 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level, 1464 .force_performance_level = &sumo_dpm_force_performance_level, 1465 }, 1466 .pflip = { 1467 .pre_page_flip = &evergreen_pre_page_flip, 1468 .page_flip = &evergreen_page_flip, 1469 .post_page_flip = &evergreen_post_page_flip, 1470 }, 1471 }; 1472 1473 static struct radeon_asic btc_asic = { 1474 .init = &evergreen_init, 1475 .fini = &evergreen_fini, 1476 .suspend = &evergreen_suspend, 1477 .resume = &evergreen_resume, 1478 .asic_reset = &evergreen_asic_reset, 1479 .vga_set_state = &r600_vga_set_state, 1480 .ioctl_wait_idle = r600_ioctl_wait_idle, 1481 .gui_idle = &r600_gui_idle, 1482 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1483 .get_xclk = &rv770_get_xclk, 1484 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1485 .gart = { 1486 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1487 .set_page = &rs600_gart_set_page, 1488 }, 1489 .ring = { 1490 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1491 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1492 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1493 }, 1494 .irq = { 1495 .set = &evergreen_irq_set, 1496 .process = &evergreen_irq_process, 1497 }, 1498 .display = { 1499 .bandwidth_update = &evergreen_bandwidth_update, 1500 .get_vblank_counter = &evergreen_get_vblank_counter, 1501 .wait_for_vblank = &dce4_wait_for_vblank, 1502 .set_backlight_level = &atombios_set_backlight_level, 1503 .get_backlight_level = &atombios_get_backlight_level, 1504 .hdmi_enable = &evergreen_hdmi_enable, 1505 .hdmi_setmode = &evergreen_hdmi_setmode, 1506 }, 1507 .copy = { 1508 .blit = &r600_copy_cpdma, 1509 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1510 .dma = &evergreen_copy_dma, 1511 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1512 .copy = &evergreen_copy_dma, 1513 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1514 }, 1515 .surface = { 1516 .set_reg = r600_set_surface_reg, 1517 .clear_reg = r600_clear_surface_reg, 1518 }, 1519 .hpd = { 1520 .init = &evergreen_hpd_init, 1521 .fini = &evergreen_hpd_fini, 1522 .sense = &evergreen_hpd_sense, 1523 .set_polarity = &evergreen_hpd_set_polarity, 1524 }, 1525 .pm = { 1526 .misc = &evergreen_pm_misc, 1527 .prepare = &evergreen_pm_prepare, 1528 .finish = &evergreen_pm_finish, 1529 .init_profile = &btc_pm_init_profile, 1530 .get_dynpm_state = &r600_pm_get_dynpm_state, 1531 .get_engine_clock = &radeon_atom_get_engine_clock, 1532 .set_engine_clock = &radeon_atom_set_engine_clock, 1533 .get_memory_clock = &radeon_atom_get_memory_clock, 1534 .set_memory_clock = &radeon_atom_set_memory_clock, 1535 .get_pcie_lanes = &r600_get_pcie_lanes, 1536 .set_pcie_lanes = &r600_set_pcie_lanes, 1537 .set_clock_gating = NULL, 1538 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1539 .get_temperature = &evergreen_get_temp, 1540 }, 1541 .dpm = { 1542 .init = &btc_dpm_init, 1543 .setup_asic = &btc_dpm_setup_asic, 1544 .enable = &btc_dpm_enable, 1545 .disable = &btc_dpm_disable, 1546 .pre_set_power_state = &btc_dpm_pre_set_power_state, 1547 .set_power_state = &btc_dpm_set_power_state, 1548 .post_set_power_state = &btc_dpm_post_set_power_state, 1549 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1550 .fini = &btc_dpm_fini, 1551 .get_sclk = &btc_dpm_get_sclk, 1552 .get_mclk = &btc_dpm_get_mclk, 1553 .print_power_state = &rv770_dpm_print_power_state, 1554 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1555 .force_performance_level = &rv770_dpm_force_performance_level, 1556 .vblank_too_short = &btc_dpm_vblank_too_short, 1557 }, 1558 .pflip = { 1559 .pre_page_flip = &evergreen_pre_page_flip, 1560 .page_flip = &evergreen_page_flip, 1561 .post_page_flip = &evergreen_post_page_flip, 1562 }, 1563 }; 1564 1565 static struct radeon_asic_ring cayman_gfx_ring = { 1566 .ib_execute = &cayman_ring_ib_execute, 1567 .ib_parse = &evergreen_ib_parse, 1568 .emit_fence = &cayman_fence_ring_emit, 1569 .emit_semaphore = &r600_semaphore_ring_emit, 1570 .cs_parse = &evergreen_cs_parse, 1571 .ring_test = &r600_ring_test, 1572 .ib_test = &r600_ib_test, 1573 .is_lockup = &cayman_gfx_is_lockup, 1574 .vm_flush = &cayman_vm_flush, 1575 .get_rptr = &radeon_ring_generic_get_rptr, 1576 .get_wptr = &radeon_ring_generic_get_wptr, 1577 .set_wptr = &radeon_ring_generic_set_wptr, 1578 }; 1579 1580 static struct radeon_asic_ring cayman_dma_ring = { 1581 .ib_execute = &cayman_dma_ring_ib_execute, 1582 .ib_parse = &evergreen_dma_ib_parse, 1583 .emit_fence = &evergreen_dma_fence_ring_emit, 1584 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1585 .cs_parse = &evergreen_dma_cs_parse, 1586 .ring_test = &r600_dma_ring_test, 1587 .ib_test = &r600_dma_ib_test, 1588 .is_lockup = &cayman_dma_is_lockup, 1589 .vm_flush = &cayman_dma_vm_flush, 1590 .get_rptr = &r600_dma_get_rptr, 1591 .get_wptr = &r600_dma_get_wptr, 1592 .set_wptr = &r600_dma_set_wptr 1593 }; 1594 1595 static struct radeon_asic_ring cayman_uvd_ring = { 1596 .ib_execute = &uvd_v1_0_ib_execute, 1597 .emit_fence = &uvd_v2_2_fence_emit, 1598 .emit_semaphore = &uvd_v3_1_semaphore_emit, 1599 .cs_parse = &radeon_uvd_cs_parse, 1600 .ring_test = &uvd_v1_0_ring_test, 1601 .ib_test = &uvd_v1_0_ib_test, 1602 .is_lockup = &radeon_ring_test_lockup, 1603 .get_rptr = &uvd_v1_0_get_rptr, 1604 .get_wptr = &uvd_v1_0_get_wptr, 1605 .set_wptr = &uvd_v1_0_set_wptr, 1606 }; 1607 1608 static struct radeon_asic cayman_asic = { 1609 .init = &cayman_init, 1610 .fini = &cayman_fini, 1611 .suspend = &cayman_suspend, 1612 .resume = &cayman_resume, 1613 .asic_reset = &cayman_asic_reset, 1614 .vga_set_state = &r600_vga_set_state, 1615 .ioctl_wait_idle = r600_ioctl_wait_idle, 1616 .gui_idle = &r600_gui_idle, 1617 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1618 .get_xclk = &rv770_get_xclk, 1619 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1620 .gart = { 1621 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1622 .set_page = &rs600_gart_set_page, 1623 }, 1624 .vm = { 1625 .init = &cayman_vm_init, 1626 .fini = &cayman_vm_fini, 1627 .set_page = &cayman_dma_vm_set_page, 1628 }, 1629 .ring = { 1630 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, 1631 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, 1632 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, 1633 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, 1634 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, 1635 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1636 }, 1637 .irq = { 1638 .set = &evergreen_irq_set, 1639 .process = &evergreen_irq_process, 1640 }, 1641 .display = { 1642 .bandwidth_update = &evergreen_bandwidth_update, 1643 .get_vblank_counter = &evergreen_get_vblank_counter, 1644 .wait_for_vblank = &dce4_wait_for_vblank, 1645 .set_backlight_level = &atombios_set_backlight_level, 1646 .get_backlight_level = &atombios_get_backlight_level, 1647 .hdmi_enable = &evergreen_hdmi_enable, 1648 .hdmi_setmode = &evergreen_hdmi_setmode, 1649 }, 1650 .copy = { 1651 .blit = &r600_copy_cpdma, 1652 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1653 .dma = &evergreen_copy_dma, 1654 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1655 .copy = &evergreen_copy_dma, 1656 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1657 }, 1658 .surface = { 1659 .set_reg = r600_set_surface_reg, 1660 .clear_reg = r600_clear_surface_reg, 1661 }, 1662 .hpd = { 1663 .init = &evergreen_hpd_init, 1664 .fini = &evergreen_hpd_fini, 1665 .sense = &evergreen_hpd_sense, 1666 .set_polarity = &evergreen_hpd_set_polarity, 1667 }, 1668 .pm = { 1669 .misc = &evergreen_pm_misc, 1670 .prepare = &evergreen_pm_prepare, 1671 .finish = &evergreen_pm_finish, 1672 .init_profile = &btc_pm_init_profile, 1673 .get_dynpm_state = &r600_pm_get_dynpm_state, 1674 .get_engine_clock = &radeon_atom_get_engine_clock, 1675 .set_engine_clock = &radeon_atom_set_engine_clock, 1676 .get_memory_clock = &radeon_atom_get_memory_clock, 1677 .set_memory_clock = &radeon_atom_set_memory_clock, 1678 .get_pcie_lanes = &r600_get_pcie_lanes, 1679 .set_pcie_lanes = &r600_set_pcie_lanes, 1680 .set_clock_gating = NULL, 1681 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1682 .get_temperature = &evergreen_get_temp, 1683 }, 1684 .dpm = { 1685 .init = &ni_dpm_init, 1686 .setup_asic = &ni_dpm_setup_asic, 1687 .enable = &ni_dpm_enable, 1688 .disable = &ni_dpm_disable, 1689 .pre_set_power_state = &ni_dpm_pre_set_power_state, 1690 .set_power_state = &ni_dpm_set_power_state, 1691 .post_set_power_state = &ni_dpm_post_set_power_state, 1692 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1693 .fini = &ni_dpm_fini, 1694 .get_sclk = &ni_dpm_get_sclk, 1695 .get_mclk = &ni_dpm_get_mclk, 1696 .print_power_state = &ni_dpm_print_power_state, 1697 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level, 1698 .force_performance_level = &ni_dpm_force_performance_level, 1699 .vblank_too_short = &ni_dpm_vblank_too_short, 1700 }, 1701 .pflip = { 1702 .pre_page_flip = &evergreen_pre_page_flip, 1703 .page_flip = &evergreen_page_flip, 1704 .post_page_flip = &evergreen_post_page_flip, 1705 }, 1706 }; 1707 1708 static struct radeon_asic trinity_asic = { 1709 .init = &cayman_init, 1710 .fini = &cayman_fini, 1711 .suspend = &cayman_suspend, 1712 .resume = &cayman_resume, 1713 .asic_reset = &cayman_asic_reset, 1714 .vga_set_state = &r600_vga_set_state, 1715 .ioctl_wait_idle = r600_ioctl_wait_idle, 1716 .gui_idle = &r600_gui_idle, 1717 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1718 .get_xclk = &r600_get_xclk, 1719 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1720 .gart = { 1721 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1722 .set_page = &rs600_gart_set_page, 1723 }, 1724 .vm = { 1725 .init = &cayman_vm_init, 1726 .fini = &cayman_vm_fini, 1727 .set_page = &cayman_dma_vm_set_page, 1728 }, 1729 .ring = { 1730 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, 1731 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, 1732 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, 1733 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, 1734 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, 1735 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1736 }, 1737 .irq = { 1738 .set = &evergreen_irq_set, 1739 .process = &evergreen_irq_process, 1740 }, 1741 .display = { 1742 .bandwidth_update = &dce6_bandwidth_update, 1743 .get_vblank_counter = &evergreen_get_vblank_counter, 1744 .wait_for_vblank = &dce4_wait_for_vblank, 1745 .set_backlight_level = &atombios_set_backlight_level, 1746 .get_backlight_level = &atombios_get_backlight_level, 1747 .hdmi_enable = &evergreen_hdmi_enable, 1748 .hdmi_setmode = &evergreen_hdmi_setmode, 1749 }, 1750 .copy = { 1751 .blit = &r600_copy_cpdma, 1752 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1753 .dma = &evergreen_copy_dma, 1754 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1755 .copy = &evergreen_copy_dma, 1756 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1757 }, 1758 .surface = { 1759 .set_reg = r600_set_surface_reg, 1760 .clear_reg = r600_clear_surface_reg, 1761 }, 1762 .hpd = { 1763 .init = &evergreen_hpd_init, 1764 .fini = &evergreen_hpd_fini, 1765 .sense = &evergreen_hpd_sense, 1766 .set_polarity = &evergreen_hpd_set_polarity, 1767 }, 1768 .pm = { 1769 .misc = &evergreen_pm_misc, 1770 .prepare = &evergreen_pm_prepare, 1771 .finish = &evergreen_pm_finish, 1772 .init_profile = &sumo_pm_init_profile, 1773 .get_dynpm_state = &r600_pm_get_dynpm_state, 1774 .get_engine_clock = &radeon_atom_get_engine_clock, 1775 .set_engine_clock = &radeon_atom_set_engine_clock, 1776 .get_memory_clock = NULL, 1777 .set_memory_clock = NULL, 1778 .get_pcie_lanes = NULL, 1779 .set_pcie_lanes = NULL, 1780 .set_clock_gating = NULL, 1781 .set_uvd_clocks = &sumo_set_uvd_clocks, 1782 .get_temperature = &tn_get_temp, 1783 }, 1784 .dpm = { 1785 .init = &trinity_dpm_init, 1786 .setup_asic = &trinity_dpm_setup_asic, 1787 .enable = &trinity_dpm_enable, 1788 .disable = &trinity_dpm_disable, 1789 .pre_set_power_state = &trinity_dpm_pre_set_power_state, 1790 .set_power_state = &trinity_dpm_set_power_state, 1791 .post_set_power_state = &trinity_dpm_post_set_power_state, 1792 .display_configuration_changed = &trinity_dpm_display_configuration_changed, 1793 .fini = &trinity_dpm_fini, 1794 .get_sclk = &trinity_dpm_get_sclk, 1795 .get_mclk = &trinity_dpm_get_mclk, 1796 .print_power_state = &trinity_dpm_print_power_state, 1797 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level, 1798 .force_performance_level = &trinity_dpm_force_performance_level, 1799 .enable_bapm = &trinity_dpm_enable_bapm, 1800 }, 1801 .pflip = { 1802 .pre_page_flip = &evergreen_pre_page_flip, 1803 .page_flip = &evergreen_page_flip, 1804 .post_page_flip = &evergreen_post_page_flip, 1805 }, 1806 }; 1807 1808 static struct radeon_asic_ring si_gfx_ring = { 1809 .ib_execute = &si_ring_ib_execute, 1810 .ib_parse = &si_ib_parse, 1811 .emit_fence = &si_fence_ring_emit, 1812 .emit_semaphore = &r600_semaphore_ring_emit, 1813 .cs_parse = NULL, 1814 .ring_test = &r600_ring_test, 1815 .ib_test = &r600_ib_test, 1816 .is_lockup = &si_gfx_is_lockup, 1817 .vm_flush = &si_vm_flush, 1818 .get_rptr = &radeon_ring_generic_get_rptr, 1819 .get_wptr = &radeon_ring_generic_get_wptr, 1820 .set_wptr = &radeon_ring_generic_set_wptr, 1821 }; 1822 1823 static struct radeon_asic_ring si_dma_ring = { 1824 .ib_execute = &cayman_dma_ring_ib_execute, 1825 .ib_parse = &evergreen_dma_ib_parse, 1826 .emit_fence = &evergreen_dma_fence_ring_emit, 1827 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1828 .cs_parse = NULL, 1829 .ring_test = &r600_dma_ring_test, 1830 .ib_test = &r600_dma_ib_test, 1831 .is_lockup = &si_dma_is_lockup, 1832 .vm_flush = &si_dma_vm_flush, 1833 .get_rptr = &r600_dma_get_rptr, 1834 .get_wptr = &r600_dma_get_wptr, 1835 .set_wptr = &r600_dma_set_wptr, 1836 }; 1837 1838 static struct radeon_asic si_asic = { 1839 .init = &si_init, 1840 .fini = &si_fini, 1841 .suspend = &si_suspend, 1842 .resume = &si_resume, 1843 .asic_reset = &si_asic_reset, 1844 .vga_set_state = &r600_vga_set_state, 1845 .ioctl_wait_idle = r600_ioctl_wait_idle, 1846 .gui_idle = &r600_gui_idle, 1847 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1848 .get_xclk = &si_get_xclk, 1849 .get_gpu_clock_counter = &si_get_gpu_clock_counter, 1850 .gart = { 1851 .tlb_flush = &si_pcie_gart_tlb_flush, 1852 .set_page = &rs600_gart_set_page, 1853 }, 1854 .vm = { 1855 .init = &si_vm_init, 1856 .fini = &si_vm_fini, 1857 .set_page = &si_dma_vm_set_page, 1858 }, 1859 .ring = { 1860 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring, 1861 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring, 1862 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring, 1863 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring, 1864 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring, 1865 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1866 }, 1867 .irq = { 1868 .set = &si_irq_set, 1869 .process = &si_irq_process, 1870 }, 1871 .display = { 1872 .bandwidth_update = &dce6_bandwidth_update, 1873 .get_vblank_counter = &evergreen_get_vblank_counter, 1874 .wait_for_vblank = &dce4_wait_for_vblank, 1875 .set_backlight_level = &atombios_set_backlight_level, 1876 .get_backlight_level = &atombios_get_backlight_level, 1877 .hdmi_enable = &evergreen_hdmi_enable, 1878 .hdmi_setmode = &evergreen_hdmi_setmode, 1879 }, 1880 .copy = { 1881 .blit = &r600_copy_cpdma, 1882 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1883 .dma = &si_copy_dma, 1884 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1885 .copy = &si_copy_dma, 1886 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1887 }, 1888 .surface = { 1889 .set_reg = r600_set_surface_reg, 1890 .clear_reg = r600_clear_surface_reg, 1891 }, 1892 .hpd = { 1893 .init = &evergreen_hpd_init, 1894 .fini = &evergreen_hpd_fini, 1895 .sense = &evergreen_hpd_sense, 1896 .set_polarity = &evergreen_hpd_set_polarity, 1897 }, 1898 .pm = { 1899 .misc = &evergreen_pm_misc, 1900 .prepare = &evergreen_pm_prepare, 1901 .finish = &evergreen_pm_finish, 1902 .init_profile = &sumo_pm_init_profile, 1903 .get_dynpm_state = &r600_pm_get_dynpm_state, 1904 .get_engine_clock = &radeon_atom_get_engine_clock, 1905 .set_engine_clock = &radeon_atom_set_engine_clock, 1906 .get_memory_clock = &radeon_atom_get_memory_clock, 1907 .set_memory_clock = &radeon_atom_set_memory_clock, 1908 .get_pcie_lanes = &r600_get_pcie_lanes, 1909 .set_pcie_lanes = &r600_set_pcie_lanes, 1910 .set_clock_gating = NULL, 1911 .set_uvd_clocks = &si_set_uvd_clocks, 1912 .get_temperature = &si_get_temp, 1913 }, 1914 .dpm = { 1915 .init = &si_dpm_init, 1916 .setup_asic = &si_dpm_setup_asic, 1917 .enable = &si_dpm_enable, 1918 .disable = &si_dpm_disable, 1919 .pre_set_power_state = &si_dpm_pre_set_power_state, 1920 .set_power_state = &si_dpm_set_power_state, 1921 .post_set_power_state = &si_dpm_post_set_power_state, 1922 .display_configuration_changed = &si_dpm_display_configuration_changed, 1923 .fini = &si_dpm_fini, 1924 .get_sclk = &ni_dpm_get_sclk, 1925 .get_mclk = &ni_dpm_get_mclk, 1926 .print_power_state = &ni_dpm_print_power_state, 1927 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level, 1928 .force_performance_level = &si_dpm_force_performance_level, 1929 .vblank_too_short = &ni_dpm_vblank_too_short, 1930 }, 1931 .pflip = { 1932 .pre_page_flip = &evergreen_pre_page_flip, 1933 .page_flip = &evergreen_page_flip, 1934 .post_page_flip = &evergreen_post_page_flip, 1935 }, 1936 }; 1937 1938 static struct radeon_asic_ring ci_gfx_ring = { 1939 .ib_execute = &cik_ring_ib_execute, 1940 .ib_parse = &cik_ib_parse, 1941 .emit_fence = &cik_fence_gfx_ring_emit, 1942 .emit_semaphore = &cik_semaphore_ring_emit, 1943 .cs_parse = NULL, 1944 .ring_test = &cik_ring_test, 1945 .ib_test = &cik_ib_test, 1946 .is_lockup = &cik_gfx_is_lockup, 1947 .vm_flush = &cik_vm_flush, 1948 .get_rptr = &radeon_ring_generic_get_rptr, 1949 .get_wptr = &radeon_ring_generic_get_wptr, 1950 .set_wptr = &radeon_ring_generic_set_wptr, 1951 }; 1952 1953 static struct radeon_asic_ring ci_cp_ring = { 1954 .ib_execute = &cik_ring_ib_execute, 1955 .ib_parse = &cik_ib_parse, 1956 .emit_fence = &cik_fence_compute_ring_emit, 1957 .emit_semaphore = &cik_semaphore_ring_emit, 1958 .cs_parse = NULL, 1959 .ring_test = &cik_ring_test, 1960 .ib_test = &cik_ib_test, 1961 .is_lockup = &cik_gfx_is_lockup, 1962 .vm_flush = &cik_vm_flush, 1963 .get_rptr = &cik_compute_ring_get_rptr, 1964 .get_wptr = &cik_compute_ring_get_wptr, 1965 .set_wptr = &cik_compute_ring_set_wptr, 1966 }; 1967 1968 static struct radeon_asic_ring ci_dma_ring = { 1969 .ib_execute = &cik_sdma_ring_ib_execute, 1970 .ib_parse = &cik_ib_parse, 1971 .emit_fence = &cik_sdma_fence_ring_emit, 1972 .emit_semaphore = &cik_sdma_semaphore_ring_emit, 1973 .cs_parse = NULL, 1974 .ring_test = &cik_sdma_ring_test, 1975 .ib_test = &cik_sdma_ib_test, 1976 .is_lockup = &cik_sdma_is_lockup, 1977 .vm_flush = &cik_dma_vm_flush, 1978 .get_rptr = &r600_dma_get_rptr, 1979 .get_wptr = &r600_dma_get_wptr, 1980 .set_wptr = &r600_dma_set_wptr, 1981 }; 1982 1983 static struct radeon_asic ci_asic = { 1984 .init = &cik_init, 1985 .fini = &cik_fini, 1986 .suspend = &cik_suspend, 1987 .resume = &cik_resume, 1988 .asic_reset = &cik_asic_reset, 1989 .vga_set_state = &r600_vga_set_state, 1990 .ioctl_wait_idle = NULL, 1991 .gui_idle = &r600_gui_idle, 1992 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1993 .get_xclk = &cik_get_xclk, 1994 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 1995 .gart = { 1996 .tlb_flush = &cik_pcie_gart_tlb_flush, 1997 .set_page = &rs600_gart_set_page, 1998 }, 1999 .vm = { 2000 .init = &cik_vm_init, 2001 .fini = &cik_vm_fini, 2002 .set_page = &cik_sdma_vm_set_page, 2003 }, 2004 .ring = { 2005 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, 2006 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, 2007 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, 2008 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, 2009 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, 2010 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 2011 }, 2012 .irq = { 2013 .set = &cik_irq_set, 2014 .process = &cik_irq_process, 2015 }, 2016 .display = { 2017 .bandwidth_update = &dce8_bandwidth_update, 2018 .get_vblank_counter = &evergreen_get_vblank_counter, 2019 .wait_for_vblank = &dce4_wait_for_vblank, 2020 .set_backlight_level = &atombios_set_backlight_level, 2021 .get_backlight_level = &atombios_get_backlight_level, 2022 .hdmi_enable = &evergreen_hdmi_enable, 2023 .hdmi_setmode = &evergreen_hdmi_setmode, 2024 }, 2025 .copy = { 2026 .blit = NULL, 2027 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2028 .dma = &cik_copy_dma, 2029 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2030 .copy = &cik_copy_dma, 2031 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2032 }, 2033 .surface = { 2034 .set_reg = r600_set_surface_reg, 2035 .clear_reg = r600_clear_surface_reg, 2036 }, 2037 .hpd = { 2038 .init = &evergreen_hpd_init, 2039 .fini = &evergreen_hpd_fini, 2040 .sense = &evergreen_hpd_sense, 2041 .set_polarity = &evergreen_hpd_set_polarity, 2042 }, 2043 .pm = { 2044 .misc = &evergreen_pm_misc, 2045 .prepare = &evergreen_pm_prepare, 2046 .finish = &evergreen_pm_finish, 2047 .init_profile = &sumo_pm_init_profile, 2048 .get_dynpm_state = &r600_pm_get_dynpm_state, 2049 .get_engine_clock = &radeon_atom_get_engine_clock, 2050 .set_engine_clock = &radeon_atom_set_engine_clock, 2051 .get_memory_clock = &radeon_atom_get_memory_clock, 2052 .set_memory_clock = &radeon_atom_set_memory_clock, 2053 .get_pcie_lanes = NULL, 2054 .set_pcie_lanes = NULL, 2055 .set_clock_gating = NULL, 2056 .set_uvd_clocks = &cik_set_uvd_clocks, 2057 .get_temperature = &ci_get_temp, 2058 }, 2059 .dpm = { 2060 .init = &ci_dpm_init, 2061 .setup_asic = &ci_dpm_setup_asic, 2062 .enable = &ci_dpm_enable, 2063 .disable = &ci_dpm_disable, 2064 .pre_set_power_state = &ci_dpm_pre_set_power_state, 2065 .set_power_state = &ci_dpm_set_power_state, 2066 .post_set_power_state = &ci_dpm_post_set_power_state, 2067 .display_configuration_changed = &ci_dpm_display_configuration_changed, 2068 .fini = &ci_dpm_fini, 2069 .get_sclk = &ci_dpm_get_sclk, 2070 .get_mclk = &ci_dpm_get_mclk, 2071 .print_power_state = &ci_dpm_print_power_state, 2072 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level, 2073 .force_performance_level = &ci_dpm_force_performance_level, 2074 .vblank_too_short = &ci_dpm_vblank_too_short, 2075 .powergate_uvd = &ci_dpm_powergate_uvd, 2076 }, 2077 .pflip = { 2078 .pre_page_flip = &evergreen_pre_page_flip, 2079 .page_flip = &evergreen_page_flip, 2080 .post_page_flip = &evergreen_post_page_flip, 2081 }, 2082 }; 2083 2084 static struct radeon_asic kv_asic = { 2085 .init = &cik_init, 2086 .fini = &cik_fini, 2087 .suspend = &cik_suspend, 2088 .resume = &cik_resume, 2089 .asic_reset = &cik_asic_reset, 2090 .vga_set_state = &r600_vga_set_state, 2091 .ioctl_wait_idle = NULL, 2092 .gui_idle = &r600_gui_idle, 2093 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2094 .get_xclk = &cik_get_xclk, 2095 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2096 .gart = { 2097 .tlb_flush = &cik_pcie_gart_tlb_flush, 2098 .set_page = &rs600_gart_set_page, 2099 }, 2100 .vm = { 2101 .init = &cik_vm_init, 2102 .fini = &cik_vm_fini, 2103 .set_page = &cik_sdma_vm_set_page, 2104 }, 2105 .ring = { 2106 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, 2107 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, 2108 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, 2109 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, 2110 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, 2111 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 2112 }, 2113 .irq = { 2114 .set = &cik_irq_set, 2115 .process = &cik_irq_process, 2116 }, 2117 .display = { 2118 .bandwidth_update = &dce8_bandwidth_update, 2119 .get_vblank_counter = &evergreen_get_vblank_counter, 2120 .wait_for_vblank = &dce4_wait_for_vblank, 2121 .set_backlight_level = &atombios_set_backlight_level, 2122 .get_backlight_level = &atombios_get_backlight_level, 2123 .hdmi_enable = &evergreen_hdmi_enable, 2124 .hdmi_setmode = &evergreen_hdmi_setmode, 2125 }, 2126 .copy = { 2127 .blit = NULL, 2128 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2129 .dma = &cik_copy_dma, 2130 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2131 .copy = &cik_copy_dma, 2132 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2133 }, 2134 .surface = { 2135 .set_reg = r600_set_surface_reg, 2136 .clear_reg = r600_clear_surface_reg, 2137 }, 2138 .hpd = { 2139 .init = &evergreen_hpd_init, 2140 .fini = &evergreen_hpd_fini, 2141 .sense = &evergreen_hpd_sense, 2142 .set_polarity = &evergreen_hpd_set_polarity, 2143 }, 2144 .pm = { 2145 .misc = &evergreen_pm_misc, 2146 .prepare = &evergreen_pm_prepare, 2147 .finish = &evergreen_pm_finish, 2148 .init_profile = &sumo_pm_init_profile, 2149 .get_dynpm_state = &r600_pm_get_dynpm_state, 2150 .get_engine_clock = &radeon_atom_get_engine_clock, 2151 .set_engine_clock = &radeon_atom_set_engine_clock, 2152 .get_memory_clock = &radeon_atom_get_memory_clock, 2153 .set_memory_clock = &radeon_atom_set_memory_clock, 2154 .get_pcie_lanes = NULL, 2155 .set_pcie_lanes = NULL, 2156 .set_clock_gating = NULL, 2157 .set_uvd_clocks = &cik_set_uvd_clocks, 2158 .get_temperature = &kv_get_temp, 2159 }, 2160 .dpm = { 2161 .init = &kv_dpm_init, 2162 .setup_asic = &kv_dpm_setup_asic, 2163 .enable = &kv_dpm_enable, 2164 .disable = &kv_dpm_disable, 2165 .pre_set_power_state = &kv_dpm_pre_set_power_state, 2166 .set_power_state = &kv_dpm_set_power_state, 2167 .post_set_power_state = &kv_dpm_post_set_power_state, 2168 .display_configuration_changed = &kv_dpm_display_configuration_changed, 2169 .fini = &kv_dpm_fini, 2170 .get_sclk = &kv_dpm_get_sclk, 2171 .get_mclk = &kv_dpm_get_mclk, 2172 .print_power_state = &kv_dpm_print_power_state, 2173 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level, 2174 .force_performance_level = &kv_dpm_force_performance_level, 2175 .powergate_uvd = &kv_dpm_powergate_uvd, 2176 .enable_bapm = &kv_dpm_enable_bapm, 2177 }, 2178 .pflip = { 2179 .pre_page_flip = &evergreen_pre_page_flip, 2180 .page_flip = &evergreen_page_flip, 2181 .post_page_flip = &evergreen_post_page_flip, 2182 }, 2183 }; 2184 2185 /** 2186 * radeon_asic_init - register asic specific callbacks 2187 * 2188 * @rdev: radeon device pointer 2189 * 2190 * Registers the appropriate asic specific callbacks for each 2191 * chip family. Also sets other asics specific info like the number 2192 * of crtcs and the register aperture accessors (all asics). 2193 * Returns 0 for success. 2194 */ 2195 int radeon_asic_init(struct radeon_device *rdev) 2196 { 2197 radeon_register_accessor_init(rdev); 2198 2199 /* set the number of crtcs */ 2200 if (rdev->flags & RADEON_SINGLE_CRTC) 2201 rdev->num_crtc = 1; 2202 else 2203 rdev->num_crtc = 2; 2204 2205 rdev->has_uvd = false; 2206 2207 switch (rdev->family) { 2208 case CHIP_R100: 2209 case CHIP_RV100: 2210 case CHIP_RS100: 2211 case CHIP_RV200: 2212 case CHIP_RS200: 2213 rdev->asic = &r100_asic; 2214 break; 2215 case CHIP_R200: 2216 case CHIP_RV250: 2217 case CHIP_RS300: 2218 case CHIP_RV280: 2219 rdev->asic = &r200_asic; 2220 break; 2221 case CHIP_R300: 2222 case CHIP_R350: 2223 case CHIP_RV350: 2224 case CHIP_RV380: 2225 if (rdev->flags & RADEON_IS_PCIE) 2226 rdev->asic = &r300_asic_pcie; 2227 else 2228 rdev->asic = &r300_asic; 2229 break; 2230 case CHIP_R420: 2231 case CHIP_R423: 2232 case CHIP_RV410: 2233 rdev->asic = &r420_asic; 2234 /* handle macs */ 2235 if (rdev->bios == NULL) { 2236 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; 2237 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; 2238 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; 2239 rdev->asic->pm.set_memory_clock = NULL; 2240 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level; 2241 } 2242 break; 2243 case CHIP_RS400: 2244 case CHIP_RS480: 2245 rdev->asic = &rs400_asic; 2246 break; 2247 case CHIP_RS600: 2248 rdev->asic = &rs600_asic; 2249 break; 2250 case CHIP_RS690: 2251 case CHIP_RS740: 2252 rdev->asic = &rs690_asic; 2253 break; 2254 case CHIP_RV515: 2255 rdev->asic = &rv515_asic; 2256 break; 2257 case CHIP_R520: 2258 case CHIP_RV530: 2259 case CHIP_RV560: 2260 case CHIP_RV570: 2261 case CHIP_R580: 2262 rdev->asic = &r520_asic; 2263 break; 2264 case CHIP_R600: 2265 rdev->asic = &r600_asic; 2266 break; 2267 case CHIP_RV610: 2268 case CHIP_RV630: 2269 case CHIP_RV620: 2270 case CHIP_RV635: 2271 case CHIP_RV670: 2272 rdev->asic = &rv6xx_asic; 2273 rdev->has_uvd = true; 2274 break; 2275 case CHIP_RS780: 2276 case CHIP_RS880: 2277 rdev->asic = &rs780_asic; 2278 rdev->has_uvd = true; 2279 break; 2280 case CHIP_RV770: 2281 case CHIP_RV730: 2282 case CHIP_RV710: 2283 case CHIP_RV740: 2284 rdev->asic = &rv770_asic; 2285 rdev->has_uvd = true; 2286 break; 2287 case CHIP_CEDAR: 2288 case CHIP_REDWOOD: 2289 case CHIP_JUNIPER: 2290 case CHIP_CYPRESS: 2291 case CHIP_HEMLOCK: 2292 /* set num crtcs */ 2293 if (rdev->family == CHIP_CEDAR) 2294 rdev->num_crtc = 4; 2295 else 2296 rdev->num_crtc = 6; 2297 rdev->asic = &evergreen_asic; 2298 rdev->has_uvd = true; 2299 break; 2300 case CHIP_PALM: 2301 case CHIP_SUMO: 2302 case CHIP_SUMO2: 2303 rdev->asic = &sumo_asic; 2304 rdev->has_uvd = true; 2305 break; 2306 case CHIP_BARTS: 2307 case CHIP_TURKS: 2308 case CHIP_CAICOS: 2309 /* set num crtcs */ 2310 if (rdev->family == CHIP_CAICOS) 2311 rdev->num_crtc = 4; 2312 else 2313 rdev->num_crtc = 6; 2314 rdev->asic = &btc_asic; 2315 rdev->has_uvd = true; 2316 break; 2317 case CHIP_CAYMAN: 2318 rdev->asic = &cayman_asic; 2319 /* set num crtcs */ 2320 rdev->num_crtc = 6; 2321 rdev->has_uvd = true; 2322 break; 2323 case CHIP_ARUBA: 2324 rdev->asic = &trinity_asic; 2325 /* set num crtcs */ 2326 rdev->num_crtc = 4; 2327 rdev->has_uvd = true; 2328 break; 2329 case CHIP_TAHITI: 2330 case CHIP_PITCAIRN: 2331 case CHIP_VERDE: 2332 case CHIP_OLAND: 2333 case CHIP_HAINAN: 2334 rdev->asic = &si_asic; 2335 /* set num crtcs */ 2336 if (rdev->family == CHIP_HAINAN) 2337 rdev->num_crtc = 0; 2338 else if (rdev->family == CHIP_OLAND) 2339 rdev->num_crtc = 2; 2340 else 2341 rdev->num_crtc = 6; 2342 if (rdev->family == CHIP_HAINAN) 2343 rdev->has_uvd = false; 2344 else 2345 rdev->has_uvd = true; 2346 switch (rdev->family) { 2347 case CHIP_TAHITI: 2348 rdev->cg_flags = 2349 RADEON_CG_SUPPORT_GFX_MGCG | 2350 RADEON_CG_SUPPORT_GFX_MGLS | 2351 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2352 RADEON_CG_SUPPORT_GFX_CGLS | 2353 RADEON_CG_SUPPORT_GFX_CGTS | 2354 RADEON_CG_SUPPORT_GFX_CP_LS | 2355 RADEON_CG_SUPPORT_MC_MGCG | 2356 RADEON_CG_SUPPORT_SDMA_MGCG | 2357 RADEON_CG_SUPPORT_BIF_LS | 2358 RADEON_CG_SUPPORT_VCE_MGCG | 2359 RADEON_CG_SUPPORT_UVD_MGCG | 2360 RADEON_CG_SUPPORT_HDP_LS | 2361 RADEON_CG_SUPPORT_HDP_MGCG; 2362 rdev->pg_flags = 0; 2363 break; 2364 case CHIP_PITCAIRN: 2365 rdev->cg_flags = 2366 RADEON_CG_SUPPORT_GFX_MGCG | 2367 RADEON_CG_SUPPORT_GFX_MGLS | 2368 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2369 RADEON_CG_SUPPORT_GFX_CGLS | 2370 RADEON_CG_SUPPORT_GFX_CGTS | 2371 RADEON_CG_SUPPORT_GFX_CP_LS | 2372 RADEON_CG_SUPPORT_GFX_RLC_LS | 2373 RADEON_CG_SUPPORT_MC_LS | 2374 RADEON_CG_SUPPORT_MC_MGCG | 2375 RADEON_CG_SUPPORT_SDMA_MGCG | 2376 RADEON_CG_SUPPORT_BIF_LS | 2377 RADEON_CG_SUPPORT_VCE_MGCG | 2378 RADEON_CG_SUPPORT_UVD_MGCG | 2379 RADEON_CG_SUPPORT_HDP_LS | 2380 RADEON_CG_SUPPORT_HDP_MGCG; 2381 rdev->pg_flags = 0; 2382 break; 2383 case CHIP_VERDE: 2384 rdev->cg_flags = 2385 RADEON_CG_SUPPORT_GFX_MGCG | 2386 RADEON_CG_SUPPORT_GFX_MGLS | 2387 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2388 RADEON_CG_SUPPORT_GFX_CGLS | 2389 RADEON_CG_SUPPORT_GFX_CGTS | 2390 RADEON_CG_SUPPORT_GFX_CP_LS | 2391 RADEON_CG_SUPPORT_GFX_RLC_LS | 2392 RADEON_CG_SUPPORT_MC_LS | 2393 RADEON_CG_SUPPORT_MC_MGCG | 2394 RADEON_CG_SUPPORT_SDMA_MGCG | 2395 RADEON_CG_SUPPORT_BIF_LS | 2396 RADEON_CG_SUPPORT_VCE_MGCG | 2397 RADEON_CG_SUPPORT_UVD_MGCG | 2398 RADEON_CG_SUPPORT_HDP_LS | 2399 RADEON_CG_SUPPORT_HDP_MGCG; 2400 rdev->pg_flags = 0 | 2401 /*RADEON_PG_SUPPORT_GFX_PG | */ 2402 RADEON_PG_SUPPORT_SDMA; 2403 break; 2404 case CHIP_OLAND: 2405 rdev->cg_flags = 2406 RADEON_CG_SUPPORT_GFX_MGCG | 2407 RADEON_CG_SUPPORT_GFX_MGLS | 2408 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2409 RADEON_CG_SUPPORT_GFX_CGLS | 2410 RADEON_CG_SUPPORT_GFX_CGTS | 2411 RADEON_CG_SUPPORT_GFX_CP_LS | 2412 RADEON_CG_SUPPORT_GFX_RLC_LS | 2413 RADEON_CG_SUPPORT_MC_LS | 2414 RADEON_CG_SUPPORT_MC_MGCG | 2415 RADEON_CG_SUPPORT_SDMA_MGCG | 2416 RADEON_CG_SUPPORT_BIF_LS | 2417 RADEON_CG_SUPPORT_UVD_MGCG | 2418 RADEON_CG_SUPPORT_HDP_LS | 2419 RADEON_CG_SUPPORT_HDP_MGCG; 2420 rdev->pg_flags = 0; 2421 break; 2422 case CHIP_HAINAN: 2423 rdev->cg_flags = 2424 RADEON_CG_SUPPORT_GFX_MGCG | 2425 RADEON_CG_SUPPORT_GFX_MGLS | 2426 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2427 RADEON_CG_SUPPORT_GFX_CGLS | 2428 RADEON_CG_SUPPORT_GFX_CGTS | 2429 RADEON_CG_SUPPORT_GFX_CP_LS | 2430 RADEON_CG_SUPPORT_GFX_RLC_LS | 2431 RADEON_CG_SUPPORT_MC_LS | 2432 RADEON_CG_SUPPORT_MC_MGCG | 2433 RADEON_CG_SUPPORT_SDMA_MGCG | 2434 RADEON_CG_SUPPORT_BIF_LS | 2435 RADEON_CG_SUPPORT_HDP_LS | 2436 RADEON_CG_SUPPORT_HDP_MGCG; 2437 rdev->pg_flags = 0; 2438 break; 2439 default: 2440 rdev->cg_flags = 0; 2441 rdev->pg_flags = 0; 2442 break; 2443 } 2444 break; 2445 case CHIP_BONAIRE: 2446 case CHIP_HAWAII: 2447 rdev->asic = &ci_asic; 2448 rdev->num_crtc = 6; 2449 rdev->has_uvd = true; 2450 if (rdev->family == CHIP_BONAIRE) { 2451 rdev->cg_flags = 2452 RADEON_CG_SUPPORT_GFX_MGCG | 2453 RADEON_CG_SUPPORT_GFX_MGLS | 2454 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2455 RADEON_CG_SUPPORT_GFX_CGLS | 2456 RADEON_CG_SUPPORT_GFX_CGTS | 2457 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2458 RADEON_CG_SUPPORT_GFX_CP_LS | 2459 RADEON_CG_SUPPORT_MC_LS | 2460 RADEON_CG_SUPPORT_MC_MGCG | 2461 RADEON_CG_SUPPORT_SDMA_MGCG | 2462 RADEON_CG_SUPPORT_SDMA_LS | 2463 RADEON_CG_SUPPORT_BIF_LS | 2464 RADEON_CG_SUPPORT_VCE_MGCG | 2465 RADEON_CG_SUPPORT_UVD_MGCG | 2466 RADEON_CG_SUPPORT_HDP_LS | 2467 RADEON_CG_SUPPORT_HDP_MGCG; 2468 rdev->pg_flags = 0; 2469 } else { 2470 rdev->cg_flags = 2471 RADEON_CG_SUPPORT_GFX_MGCG | 2472 RADEON_CG_SUPPORT_GFX_MGLS | 2473 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2474 RADEON_CG_SUPPORT_GFX_CGLS | 2475 RADEON_CG_SUPPORT_GFX_CGTS | 2476 RADEON_CG_SUPPORT_GFX_CP_LS | 2477 RADEON_CG_SUPPORT_MC_LS | 2478 RADEON_CG_SUPPORT_MC_MGCG | 2479 RADEON_CG_SUPPORT_SDMA_MGCG | 2480 RADEON_CG_SUPPORT_SDMA_LS | 2481 RADEON_CG_SUPPORT_BIF_LS | 2482 RADEON_CG_SUPPORT_VCE_MGCG | 2483 RADEON_CG_SUPPORT_UVD_MGCG | 2484 RADEON_CG_SUPPORT_HDP_LS | 2485 RADEON_CG_SUPPORT_HDP_MGCG; 2486 rdev->pg_flags = 0; 2487 } 2488 break; 2489 case CHIP_KAVERI: 2490 case CHIP_KABINI: 2491 rdev->asic = &kv_asic; 2492 /* set num crtcs */ 2493 if (rdev->family == CHIP_KAVERI) { 2494 rdev->num_crtc = 4; 2495 rdev->cg_flags = 2496 RADEON_CG_SUPPORT_GFX_MGCG | 2497 RADEON_CG_SUPPORT_GFX_MGLS | 2498 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2499 RADEON_CG_SUPPORT_GFX_CGLS | 2500 RADEON_CG_SUPPORT_GFX_CGTS | 2501 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2502 RADEON_CG_SUPPORT_GFX_CP_LS | 2503 RADEON_CG_SUPPORT_SDMA_MGCG | 2504 RADEON_CG_SUPPORT_SDMA_LS | 2505 RADEON_CG_SUPPORT_BIF_LS | 2506 RADEON_CG_SUPPORT_VCE_MGCG | 2507 RADEON_CG_SUPPORT_UVD_MGCG | 2508 RADEON_CG_SUPPORT_HDP_LS | 2509 RADEON_CG_SUPPORT_HDP_MGCG; 2510 rdev->pg_flags = 0; 2511 /*RADEON_PG_SUPPORT_GFX_PG | 2512 RADEON_PG_SUPPORT_GFX_SMG | 2513 RADEON_PG_SUPPORT_GFX_DMG | 2514 RADEON_PG_SUPPORT_UVD | 2515 RADEON_PG_SUPPORT_VCE | 2516 RADEON_PG_SUPPORT_CP | 2517 RADEON_PG_SUPPORT_GDS | 2518 RADEON_PG_SUPPORT_RLC_SMU_HS | 2519 RADEON_PG_SUPPORT_ACP | 2520 RADEON_PG_SUPPORT_SAMU;*/ 2521 } else { 2522 rdev->num_crtc = 2; 2523 rdev->cg_flags = 2524 RADEON_CG_SUPPORT_GFX_MGCG | 2525 RADEON_CG_SUPPORT_GFX_MGLS | 2526 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2527 RADEON_CG_SUPPORT_GFX_CGLS | 2528 RADEON_CG_SUPPORT_GFX_CGTS | 2529 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2530 RADEON_CG_SUPPORT_GFX_CP_LS | 2531 RADEON_CG_SUPPORT_SDMA_MGCG | 2532 RADEON_CG_SUPPORT_SDMA_LS | 2533 RADEON_CG_SUPPORT_BIF_LS | 2534 RADEON_CG_SUPPORT_VCE_MGCG | 2535 RADEON_CG_SUPPORT_UVD_MGCG | 2536 RADEON_CG_SUPPORT_HDP_LS | 2537 RADEON_CG_SUPPORT_HDP_MGCG; 2538 rdev->pg_flags = 0; 2539 /*RADEON_PG_SUPPORT_GFX_PG | 2540 RADEON_PG_SUPPORT_GFX_SMG | 2541 RADEON_PG_SUPPORT_UVD | 2542 RADEON_PG_SUPPORT_VCE | 2543 RADEON_PG_SUPPORT_CP | 2544 RADEON_PG_SUPPORT_GDS | 2545 RADEON_PG_SUPPORT_RLC_SMU_HS | 2546 RADEON_PG_SUPPORT_SAMU;*/ 2547 } 2548 rdev->has_uvd = true; 2549 break; 2550 default: 2551 /* FIXME: not supported yet */ 2552 return -EINVAL; 2553 } 2554 2555 if (rdev->flags & RADEON_IS_IGP) { 2556 rdev->asic->pm.get_memory_clock = NULL; 2557 rdev->asic->pm.set_memory_clock = NULL; 2558 } 2559 2560 return 0; 2561 } 2562 2563