Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29 |
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6b9bd7c3 |
| 12-May-2023 |
Jani Nikula <jani.nikula@intel.com> |
drm/i915/display: add i915 parameter to I915_STATE_WARN()
Add i915 parameter to I915_STATE_WARN() and use device based logging.
Done using cocci + hand edited where there was no i915 local variable
drm/i915/display: add i915 parameter to I915_STATE_WARN()
Add i915 parameter to I915_STATE_WARN() and use device based logging.
Done using cocci + hand edited where there was no i915 local variable ready.
v2: avoid null deref in verify_connector_state()
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230512181658.1735594-1-jani.nikula@intel.com
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Revision tags: v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25 |
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51390cc0 |
| 13-Apr-2023 |
Radhakrishna Sripada <radhakrishna.sripada@intel.com> |
drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy has a dedicated PIPE 5.2 Message bus for configuration. Th
drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy has a dedicated PIPE 5.2 Message bus for configuration. This message bus is used to configure the phy internal registers.
XELPDP has C10 phys to drive output to the EDP and the native output from the display engine. Add structures, programming hardware state readout logic. Port clock calculations are similar to DG2. Use the DG2 formulae to calculate the port clock but use the relevant pll signals. Note: PHY lane 0 is always used for PLL programming.
Add sequences for C10 phy enable/disable phy lane reset, powerdown change sequence and phy lane programming.
Bspec: 64539, 64568, 64599, 65100, 65101, 65450, 65451, 67610, 67636
v2: Squash patches related to C10 phy message bus and pll programming support (Jani) Move register definitions to a new file i.e. intel_cx0_reg_defs.h (Jani) Move macro definitions (Jani) DP rates as separate patch (Jani) Spin out xelpdp register definitions into a separate file (Jani) Replace macro to select registers based on phy lane with function calls (Jani) Fix styling issues (Jani) Call XELPDP_PORT_P2M_MSGBUS_STATUS() with port instead of phy (Lucas) v3: Move clear request flag into try-loop v4: On PHY idle change drm_err_once() as drm_dbg_kms() (Jani) use __intel_de_wait_for_register() instead of __intel_wait_for_register and uncomment intel_uncore.h (Jani) Add DP-alt support for PHY lane programming (Khaled) v4: Add tx and cmn on c10mpllb_state (Imre) Add missing waits for pending transactions between two message bus writes (Imre) General cleanups and simplifications (Imre) v5: Few nit cleanups from rev4 (imre) s/dev_priv/i915/ , s/c10mpllb/c10pll/ (RK) Rebase v6: Move the mtl code from intel_c10pll_calc_port_clock to mtl function Fix typo in comment for REG_FIELD_PREP8 definition(Imre)
Cc: Mika Kahola <mika.kahola@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Cc: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> (v4) Link: https://patchwork.freedesktop.org/patch/msgid/20230413212443.1504245-4-radhakrishna.sripada@intel.com
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Revision tags: v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4 |
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52a90349 |
| 21-Oct-2022 |
Ville Syrjälä <ville.syrjala@linux.intel.com> |
drm/i915: Introduce intel_crtc_needs_fastset()
Replace the somewhat obscure crtc_state.update_pipe checks with a more descriptive thing. Also nicely matches the intel_crtc_needs_modeset() counterpar
drm/i915: Introduce intel_crtc_needs_fastset()
Replace the somewhat obscure crtc_state.update_pipe checks with a more descriptive thing. Also nicely matches the intel_crtc_needs_modeset() counterpart for full modesets.
v2: Handle one more case in the fbc code
Reviewed-by: Jani Nikula <jani.nikula@intel.com> #v1 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221021162442.27283-2-ville.syrjala@linux.intel.com
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Revision tags: v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68 |
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42a0d256 |
| 08-Sep-2022 |
Ville Syrjälä <ville.syrjala@linux.intel.com> |
drm/i915: Extract skl_watermark.c
Pull all the skl+ watermark code (and the dbuf/sagv/ipc code since it's all sort of intertwined and I'm too lazy to think of a finer grained split right now) into i
drm/i915: Extract skl_watermark.c
Pull all the skl+ watermark code (and the dbuf/sagv/ipc code since it's all sort of intertwined and I'm too lazy to think of a finer grained split right now) into its own file from the catch-all intel_pm.c.
Also sneak in the s/dev_priv/i915/ rename while at it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220908191646.20239-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
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Revision tags: v5.15.67, v5.15.66 |
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27d06077 |
| 07-Sep-2022 |
Ville Syrjälä <ville.syrjala@linux.intel.com> |
drm/i915: Make M/N checks non-fuzzy
Now that we no longer fuzz M/N during fastset these should match exctly.
In order to get a match with what the BIOS does we need to round M/N down. And we do the
drm/i915: Make M/N checks non-fuzzy
Now that we no longer fuzz M/N during fastset these should match exctly.
In order to get a match with what the BIOS does we need to round M/N down. And we do the opposite rounding when doing the readback. That gets us pretty much the same thing back.
There can still be slight rounding differences between FDI M/N vs. the DPLL output so we allow for tiny deviation in intel_pipe_config_sanity_check().
v2: Tweak rounding/sanity check stuff a bit
Reviewed-by: Jani Nikula <jani.nikula@intel.com> #v1 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220907091057.11572-10-ville.syrjala@linux.intel.com
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Revision tags: v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48 |
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ac1b49be |
| 16-Jun-2022 |
Jani Nikula <jani.nikula@intel.com> |
drm/i915/display: change who adds [] around crtc state dump context string
Add the brackets [] around crtc state dump context string in intel_crtc_state_dump() so the callers don't have to.
Signed-
drm/i915/display: change who adds [] around crtc state dump context string
Add the brackets [] around crtc state dump context string in intel_crtc_state_dump() so the callers don't have to.
Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/c7d671279fb7d99eaf882bcb88c5c1d653755fb1.1655372759.git.jani.nikula@intel.com
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3e29d3b3 |
| 16-Jun-2022 |
Jani Nikula <jani.nikula@intel.com> |
drm/i915/display: split out crtc state dump to a separate file
Declutter intel_display.c by splitting out crtc state dumping to a separate file.
v2: intel_pipe_config_dump -> intel_crtc_state_dump
drm/i915/display: split out crtc state dump to a separate file
Declutter intel_display.c by splitting out crtc state dumping to a separate file.
v2: intel_pipe_config_dump -> intel_crtc_state_dump
Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/f72a5626473692910263671af91e02251ed87eea.1655372759.git.jani.nikula@intel.com
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df17ff62 |
| 16-Jun-2022 |
Jani Nikula <jani.nikula@intel.com> |
drm/i915/display: split out modeset verification code
Add new file intel_modeset_verify.c for high level modeset verification code to declutter intel_display.h. The new file is supposed to be about
drm/i915/display: split out modeset verification code
Add new file intel_modeset_verify.c for high level modeset verification code to declutter intel_display.h. The new file is supposed to be about crtc/encoder/connector verification; the state verification for very specific functionality such as plls or wm should be placed next to the code it verifies.
Fix some minor checkpatch issues while at it.
v2: Rebase
Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/b9b47c14316a9edb772a8b8f934eabe7e928dd76.1655372759.git.jani.nikula@intel.com
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