drm/amdgpu: Add mmhub v1_8_0 ras err status registersadd new ras error status registers introduced inmmhub v1_8_0 to log mmea and mm_cane ras err, includingMMEAx_UE|CE_ERR_STATUS_LO|HIMM_CANE_UE
drm/amdgpu: Add mmhub v1_8_0 ras err status registersadd new ras error status registers introduced inmmhub v1_8_0 to log mmea and mm_cane ras err, includingMMEAx_UE|CE_ERR_STATUS_LO|HIMM_CANE_UE|CE_ERR_STATUS_LO|HISigned-off-by: Hawking Zhang <Hawking.Zhang@amd.com>Reviewed-by: Tao Zhou <tao.zhou1@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
drm/amdgpu: add mmhub v1_8_0 ip headersAdd mmhub v1_8_0 register offset and shift masksheader filesv2: update headers (Alex)Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>Reviewed-by: Le
drm/amdgpu: add mmhub v1_8_0 ip headersAdd mmhub v1_8_0 register offset and shift masksheader filesv2: update headers (Alex)Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>Reviewed-by: Le Ma <Le.Ma@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Add missing XGMI hive registers for mmhub 9.4.1These are used by umr to sort the hive nodes since the kernelinitializes the nodes in order of bus enumeration not XGMI hiveenumerat
drm/amd/amdgpu: Add missing XGMI hive registers for mmhub 9.4.1These are used by umr to sort the hive nodes since the kernelinitializes the nodes in order of bus enumeration not XGMI hiveenumeration.Signed-off-by: Tom St Denis <tom.stdenis@amd.com>Reviewed-by: Alex Deucher <alexander.deucher@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add mmhub v3_0_1 headersAdd mmhub v3_0_1 headers, because there are many differeces with v3_0_0.v2: squash in updates (Alex)Signed-off-by: Huang Rui <ray.huang@amd.com>Reviewed-by:
drm/amdgpu: add mmhub v3_0_1 headersAdd mmhub v3_0_1 headers, because there are many differeces with v3_0_0.v2: squash in updates (Alex)Signed-off-by: Huang Rui <ray.huang@amd.com>Reviewed-by: Tim Huang <Tim.Huang@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add mmhub v3_0_2 ip headersAdd mmhub v3_0_2 register offset and shift masksv2: update to latest headersSigned-off-by: Hawking Zhang <Hawking.Zhang@amd.com>Reviewed-by: Likun Gao <L
drm/amdgpu: add mmhub v3_0_2 ip headersAdd mmhub v3_0_2 register offset and shift masksv2: update to latest headersSigned-off-by: Hawking Zhang <Hawking.Zhang@amd.com>Reviewed-by: Likun Gao <Likun.Gao@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add mmhub v3_0_0 ip headers v6Add mmhub v3_0_0 register offset and shift masksheader files (Hawking)Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>Signed-off-by: Likun Gao <Lik
drm/amdgpu: add mmhub v3_0_0 ip headers v6Add mmhub v3_0_0 register offset and shift masksheader files (Hawking)Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>Signed-off-by: Likun Gao <Likun.Gao@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>Reviewed-by: Likun Gao <Likun.Gao@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add mmhub v1_7 ip headers (v3)v1: Add mmhub v1_7 register offset andshift masks in header files (Hawking)v2: Clean up mmhub v1_7 registers (Alex)v3: Update registers (Alex)Signed-o
drm/amdgpu: add mmhub v1_7 ip headers (v3)v1: Add mmhub v1_7 register offset andshift masks in header files (Hawking)v2: Clean up mmhub v1_7 registers (Alex)v3: Update registers (Alex)Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>Reviewed-by: Kevin Wang <kevin1.wang@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add vangogh asic header files (v2)This patch is to add vangogh asic header files.v2: squash in updatesSigned-off-by: Huang Rui <ray.huang@amd.com>Reviewed-by: Alex Deucher <alexand
drm/amdgpu: add vangogh asic header files (v2)This patch is to add vangogh asic header files.v2: squash in updatesSigned-off-by: Huang Rui <ray.huang@amd.com>Reviewed-by: Alex Deucher <alexander.deucher@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: update mmhub 9.4.1 header files for AcrturusAdd mask & shift definition of MAM_D(0~3)MEM for all mmhubranges.Signed-off-by: Dennis Li <Dennis.Li@amd.com>Acked-by: Alex Deucher <alex
drm/amdgpu: update mmhub 9.4.1 header files for AcrturusAdd mask & shift definition of MAM_D(0~3)MEM for all mmhubranges.Signed-off-by: Dennis Li <Dennis.Li@amd.com>Acked-by: Alex Deucher <alexander.deucher@amd.com>Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: refine query function of mmhub EDC counter in vg20Add codes to print the detail EDC info for the subblock of mmhubv2: Move the EDC_CNT registers' defintion from mmhub_9_4 headerfiles
drm/amdgpu: refine query function of mmhub EDC counter in vg20Add codes to print the detail EDC info for the subblock of mmhubv2: Move the EDC_CNT registers' defintion from mmhub_9_4 headerfiles to mmhub_1_0 ones. Add mmhub_v1_0_ prefix for the localstatic variable and function.v3: squash in DC fixSigned-off-by: Dennis Li <dennis.li@amd.com>Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>Reviewed-by: Tao Zhou <tao.zhou1@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: implement querying ras error count for mmhubget mmhub ea ras error count by accessing EDC_CNT registerSigned-off-by: Tao Zhou <tao.zhou1@amd.com>Reviewed-by: Guchun Chen <guchun.chen
drm/amdgpu: implement querying ras error count for mmhubget mmhub ea ras error count by accessing EDC_CNT registerSigned-off-by: Tao Zhou <tao.zhou1@amd.com>Reviewed-by: Guchun Chen <guchun.chen@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add mmhub 9.4.1 header files for Acrturusmmhub is the GPU memory hub used by SDMA and VCN.Signed-off-by: Le Ma <le.ma@amd.com>Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>Signe
drm/amdgpu: add mmhub 9.4.1 header files for Acrturusmmhub is the GPU memory hub used by SDMA and VCN.Signed-off-by: Le Ma <le.ma@amd.com>Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add MMHUB 2.0 register headersSigned-off-by: Hawking Zhang <Hawking.Zhang@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/include: Add mmhub 9.4 reg offsets and shift-maskIn particular, we need the mmMC_VM_XGMI_LFB_CNTL register, fordetermining if xGMI is enabled on VG20. This will be used by DC todetermine
drm/amd/include: Add mmhub 9.4 reg offsets and shift-maskIn particular, we need the mmMC_VM_XGMI_LFB_CNTL register, fordetermining if xGMI is enabled on VG20. This will be used by DC todetermine the correct spread spectrum adjustment for display and audioclocks.Reviewed-by: Alex Deucher <alexander.deucher@amd.com>Signed-off-by: Leo Li <sunpeng.li@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/include: Add ip header files for vega12.Add ip header files for IPs with a delta for vg12:GC, MMHUB, OSSAcked-by: Christian König <christian.koenig@amd.com>Signed-off-by: Feifei Xu <Fei
drm/amd/include: Add ip header files for vega12.Add ip header files for IPs with a delta for vg12:GC, MMHUB, OSSAcked-by: Christian König <christian.koenig@amd.com>Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>Reviewed-By: Ken Wang <ken.wang@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/include:cleanup raven1 mmhub header files.Cleanup asic_reg/raven1/MMHUB folder.Remove unused mmhub_9_1_default.hSigned-off-by: Feifei Xu <Feifei.Xu@amd.com>Acked-by: Christian König <chr
drm/amd/include:cleanup raven1 mmhub header files.Cleanup asic_reg/raven1/MMHUB folder.Remove unused mmhub_9_1_default.hSigned-off-by: Feifei Xu <Feifei.Xu@amd.com>Acked-by: Christian König <christian.koenig@amd.com>Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/include:cleanup vega10 mmhub header files.Cleanup asic_reg/vega10/MMHUB folder.Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>