drm/amdgpu: Add df v4_3 headersAdd df v4_3 header files.Signed-off-by: Candice Li <candice.li@amd.com>Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>Signed-off-by: Alex Deucher <alexander.de
drm/amdgpu: Add df v4_3 headersAdd df v4_3 header files.Signed-off-by: Candice Li <candice.li@amd.com>Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
drm/amdgpu: add poison mode query for DF (v2)Add ras poison mode query interface for DF.v2: replace RREG32_PCIE with RREG32_SOC15.Signed-off-by: Tao Zhou <tao.zhou1@amd.com>Reviewed-by: Hawkin
drm/amdgpu: add poison mode query for DF (v2)Add ras poison mode query interface for DF.v2: replace RREG32_PCIE with RREG32_SOC15.Signed-off-by: Tao Zhou <tao.zhou1@amd.com>Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Query correct register for DF hashing on AldebaranFor Aldebaran, driver needs to query DramMegaBaseAddress tocheck if DF hashing is enabled.Signed-off-by: Mukul Joshi <mukul.joshi@am
drm/amdgpu: Query correct register for DF hashing on AldebaranFor Aldebaran, driver needs to query DramMegaBaseAddress tocheck if DF hashing is enabled.Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>Acked-by: Alex Deucher <alexander.deucher@amd.com>Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Enable TCP channel hashing for AldebaranEnable TCP channel hashing to match DF hash settings for Aldebaran.Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>Signed-off-by: Oak Zeng <Oa
drm/amdgpu: Enable TCP channel hashing for AldebaranEnable TCP channel hashing to match DF hash settings for Aldebaran.Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>Reviewed-by: Joseph Greathouse <Joseph.Greathouse@amd.com>Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: added support to get mGPU DRAM baseresolves issue with RAS error injection in mGPU configurationReviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>Signed-off-by: John Clements <john.c
drm/amdgpu: added support to get mGPU DRAM baseresolves issue with RAS error injection in mGPU configurationReviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>Signed-off-by: John Clements <john.clements@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add defines for DF and TCP HashingOn Arcturus, we need TC channel hashing, which is set by thedriver, to match DF hashing, which is set by VBIOS. To matchthese, we plan to query the D
drm/amdgpu: add defines for DF and TCP HashingOn Arcturus, we need TC channel hashing, which is set by thedriver, to match DF hashing, which is set by VBIOS. To matchthese, we plan to query the DF information and then properlyset the TC configuration bits to match them.This patch adds the required fields to register definitionsin preparation for a future patch which will use them.Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com>Reviewed-by: Alex Deucher <alexander.deucher@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add perfmons accessible during df c-statesDuring DF C-State, Perfmon counters outside of range 1D700-1D7FF willencounter SLVERR affecting xGMI performance monitoring. PerfmonCtr[7:4]
drm/amdgpu: add perfmons accessible during df c-statesDuring DF C-State, Perfmon counters outside of range 1D700-1D7FF willencounter SLVERR affecting xGMI performance monitoring. PerfmonCtr[7:4]is being added to avoid SLVERR during read since it falls within thisrange. PerfmonCtl[7:4] is being added in order to arm PerfmonCtr[7:4].Since PerfmonCtl[7:4] exists outside of range 1D700-1D7FF, DF routineswill be enabled to opportunistically re-arm PerfmonCtl[7:4] on retryafter SLVERR.Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com>Acked-by: Alex Deucher <Alexander.Deucher@amd.com>Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: exposing fica registers to df offsetsexposing fica registers to poll df pie data for xgmi error counters forvega20.Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com>Reviewed-by: Al
drm/amdgpu: exposing fica registers to df offsetsexposing fica registers to poll df pie data for xgmi error counters forvega20.Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com>Reviewed-by: Alexander Deucher <Alexander.Deucher@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add df perfmon regs and funcs for xgmiv6: Squash in warning fix (Colin Ian King)v5: Fix warnings (Alex)v4: fixed mixed delaration and code warnings and minor errorsv3: exposing df fu
drm/amdgpu: add df perfmon regs and funcs for xgmiv6: Squash in warning fix (Colin Ian King)v5: Fix warnings (Alex)v4: fixed mixed delaration and code warnings and minor errorsv3: exposing df funcs in amdgpu_df_funcs in amdgpu.hv2: moving permonctl/perfmonctr from default to offset- adding df perfmonctl and perfmonctr registers for df counters- adding df funcs to set perfmonctl and get perfmonctr fordf and xgmi counters- exposing df funcs in amdgpu_df_funcsSigned-off-by: Jonathan Kim <jonathan.kim@amd.com>Reviewed-by: Evan Quan <evan.quan@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/include: Update df 3.6 mask and shift definitionThe register field hsas been changed in df 3.6, update to correct settingSigned-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>Acked-by: Alex De
drm/amd/include: Update df 3.6 mask and shift definitionThe register field hsas been changed in df 3.6, update to correct settingSigned-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>Acked-by: Alex Deucher <alexander.deucher@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add new DF 1.7 register defsReviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add df 3.6 headersNeeded for vega20.Acked-by: Christian König <christian.koenig@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add df v1_7 header filesSigned-off-by: Hawking Zhang <Hawking.Zhang@amd.com>Reviewed-by: Alex Deucher <alexander.deucher@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>