|
Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45 |
|
| #
a9366b94 |
| 10-Aug-2023 |
SungHuai Wang <danny.wang@amd.com> |
drm/amd/display: fix static screen detection setting
[WHY]
OTG_STATIC_SCREEN_EVENT_MASK is changed in DCN3,
but we still follow DCN2 to apply setting for
OTG_STATIC_SCREEN_EVENT_MASK.
[How]
Add new
drm/amd/display: fix static screen detection setting
[WHY]
OTG_STATIC_SCREEN_EVENT_MASK is changed in DCN3,
but we still follow DCN2 to apply setting for
OTG_STATIC_SCREEN_EVENT_MASK.
[How]
Add new function to apply correct settings for DCN3 series.
Reviewed-by: Anthony Koo <anthony.koo@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: SungHuai Wang <danny.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
|
Revision tags: v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20 |
|
| #
25879d7b |
| 16-Mar-2023 |
Qingqing Zhuo <qingqing.zhuo@amd.com> |
drm/amd/display: Clean FPGA code in dc
[Why]
Drop dead code for Linux.
[How]
Remove all IS_FPGA_MAXIMUS_DC and IS_DIAG_DC
Reviewed-by: Ariel Bernstein <eric.bernstein@amd.com>
Acked-by: Tom Chung
drm/amd/display: Clean FPGA code in dc
[Why]
Drop dead code for Linux.
[How]
Remove all IS_FPGA_MAXIMUS_DC and IS_DIAG_DC
Reviewed-by: Ariel Bernstein <eric.bernstein@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
d205a800 |
| 12-Apr-2023 |
Leo (Hanghong) Ma <hanghong.ma@amd.com> |
drm/amd/display: Add visual confirm color support for MCLK switch
[Why && How]
We would like to have visual confirm color support for MCLK switch.
1. Set visual confirm color to yellow: Vblank MCLK
drm/amd/display: Add visual confirm color support for MCLK switch
[Why && How]
We would like to have visual confirm color support for MCLK switch.
1. Set visual confirm color to yellow: Vblank MCLK switch.
2. Set visual confirm color to cyan: FPO + Vblank MCLK
switch.
3. Set visual confirm color to pink: Vactive MCLK switch.
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
7052a801 |
| 30-Mar-2023 |
Michael Mityushkin <michael.mityushkin@amd.com> |
drm/amd/display: Correct output color space during HW reinitialize
[Why]
Doing core_link_disable_stream or set_dpms_off when reinitializing
hardware causes issue to repro with external display conne
drm/amd/display: Correct output color space during HW reinitialize
[Why]
Doing core_link_disable_stream or set_dpms_off when reinitializing
hardware causes issue to repro with external display connected. This is
unnecessary, blanking pixel data should be sufficient.
[How]
Call disable_pixel_data while reinitializing hardware instead of
core_link_disable_stream or set_dpms_off.
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Michael Mityushkin <michael.mityushkin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
|
Revision tags: v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11 |
|
| #
9dc5b360 |
| 29-Nov-2022 |
Charlene Liu <Charlene.Liu@amd.com> |
Revert "drm/amd/display: correct static_screen_event_mask"
This reverts commit c800d9ff8cdec57778ab21f4d933a25f41f44738.
[why]
revert for now because this change exposed other issue.
Signed-off-by
Revert "drm/amd/display: correct static_screen_event_mask"
This reverts commit c800d9ff8cdec57778ab21f4d933a25f41f44738.
[why]
revert for now because this change exposed other issue.
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
|
Revision tags: v6.0.10, v5.15.80 |
|
| #
c800d9ff |
| 24-Nov-2022 |
Charlene Liu <Charlene.Liu@amd.com> |
drm/amd/display: correct static_screen_event_mask
[why]
HW register bit define changed.
Reviewed-by: Zhan Liu <Zhan.Liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-b
drm/amd/display: correct static_screen_event_mask
[why]
HW register bit define changed.
Reviewed-by: Zhan Liu <Zhan.Liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
|
Revision tags: v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65 |
|
| #
9c75891f |
| 31-Aug-2022 |
Wenjing Liu <wenjing.liu@amd.com> |
drm/amd/display: rework recent update PHY state commit
[why]
Original change 594b237b9a07 ("drm/amd/display: Add
interface to track PHY state") was implemented by assuming stream's
dpms off is equiv
drm/amd/display: rework recent update PHY state commit
[why]
Original change 594b237b9a07 ("drm/amd/display: Add
interface to track PHY state") was implemented by assuming stream's
dpms off is equivalent to PHY power off.
This assumption doesn't hold in following situations:
1. MST multiple stream scenario, where multiple streams are sharing the
same PHY output. Toggle dpms off for one of the stream doesn't power
off the PHY due to the presence of other streams.
2. enable stream failure scenario, where enable stream fails due to
failure of link training. This will cause DPMS off is set to false, while
the actual PHY power state is off in certain cases.
Due to the problematic assumption, the logic will skip disabling
other streams for MST multiple stream scenario, therefore PHY is
not actually powered off.
[how]
1. Rework this refactor by moving PHY state update down to hardware
level, where we update PHY state in place when hardware sequencer
is actually changing the power state of the PHY hardware.
2. Reimplement symclk on TX off workaround in place when we are actually
calling transmitter control to power off PHY in dcn32. Note the workaround is
added due to the lack of proper software interface to set TX while keeping
symclk on. We plan to address this interface problem so we can set TX off
only without affecting symclk in future dcn versions.
Fixes: 594b237b9a07 ("drm/amd/display: Add interface to track PHY state")
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
|
Revision tags: v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17 |
|
| #
9b9bd3f6 |
| 19-Mar-2022 |
Eric Yang <Eric.Yang2@amd.com> |
drm/amd/display: undo clearing of z10 related function pointers
[Why]
Z10 and S0i3 have some shared path. Previous code clean up ,
incorrectly removed these pointers, which breaks s0i3 restore
[How
drm/amd/display: undo clearing of z10 related function pointers
[Why]
Z10 and S0i3 have some shared path. Previous code clean up ,
incorrectly removed these pointers, which breaks s0i3 restore
[How]
Do not clear the function pointers based on Z10 disable.
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
a0bd69e1 |
| 19-Mar-2022 |
Eric Yang <Eric.Yang2@amd.com> |
drm/amd/display: undo clearing of z10 related function pointers
[Why]
Z10 and S0i3 have some shared path. Previous code clean up ,
incorrectly removed these pointers, which breaks s0i3 restore
[How
drm/amd/display: undo clearing of z10 related function pointers
[Why]
Z10 and S0i3 have some shared path. Previous code clean up ,
incorrectly removed these pointers, which breaks s0i3 restore
[How]
Do not clear the function pointers based on Z10 disable.
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
|
Revision tags: v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8 |
|
| #
c856f16c |
| 09-Dec-2021 |
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> |
drm/amd/display: Set optimize_pwr_state for DCN31
[Why]
We'll exit optimized power state to do link detection but we won't enter
back into the optimized power state.
This could potentially block s2
drm/amd/display: Set optimize_pwr_state for DCN31
[Why]
We'll exit optimized power state to do link detection but we won't enter
back into the optimized power state.
This could potentially block s2idle entry depending on the sequencing,
but it also means we're losing some power during the transition period.
[How]
Hook up the handler like DCN21. It was also missed like the
exit_optimized_pwr_state callback.
Fixes: 64b1d0e8d500 ("drm/amd/display: Add DCN3.1 HWSEQ")
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Eric Yang <Eric.Yang2@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
33735c1c |
| 09-Dec-2021 |
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> |
drm/amd/display: Set optimize_pwr_state for DCN31
[Why]
We'll exit optimized power state to do link detection but we won't enter
back into the optimized power state.
This could potentially block s2
drm/amd/display: Set optimize_pwr_state for DCN31
[Why]
We'll exit optimized power state to do link detection but we won't enter
back into the optimized power state.
This could potentially block s2idle entry depending on the sequencing,
but it also means we're losing some power during the transition period.
[How]
Hook up the handler like DCN21. It was also missed like the
exit_optimized_pwr_state callback.
Fixes: 64b1d0e8d500 ("drm/amd/display: Add DCN3.1 HWSEQ")
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Eric Yang <Eric.Yang2@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
7e4d2f30 |
| 10-Dec-2021 |
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> |
drm/amd/display: Set exit_optimized_pwr_state for DCN31
[Why]
SMU now respects the PHY refclk disable request from driver.
This causes a hang during hotplug when PHY refclk was disabled
because it'
drm/amd/display: Set exit_optimized_pwr_state for DCN31
[Why]
SMU now respects the PHY refclk disable request from driver.
This causes a hang during hotplug when PHY refclk was disabled
because it's not being re-enabled and the transmitter control
starts on dc_link_detect.
[How]
We normally would re-enable the clk with exit_optimized_pwr_state
but this is only set on DCN21 and DCN301. Set it for dcn31 as well.
This fixes DMCUB timeouts in the PHY.
Fixes: 64b1d0e8d500 ("drm/amd/display: Add DCN3.1 HWSEQ")
Reviewed-by: Eric Yang <Eric.Yang2@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
0215466a |
| 10-Dec-2021 |
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> |
drm/amd/display: Set exit_optimized_pwr_state for DCN31
[Why]
SMU now respects the PHY refclk disable request from driver.
This causes a hang during hotplug when PHY refclk was disabled
because it'
drm/amd/display: Set exit_optimized_pwr_state for DCN31
[Why]
SMU now respects the PHY refclk disable request from driver.
This causes a hang during hotplug when PHY refclk was disabled
because it's not being re-enabled and the transmitter control
starts on dc_link_detect.
[How]
We normally would re-enable the clk with exit_optimized_pwr_state
but this is only set on DCN21 and DCN301. Set it for dcn31 as well.
This fixes DMCUB timeouts in the PHY.
Fixes: 64b1d0e8d500 ("drm/amd/display: Add DCN3.1 HWSEQ")
Reviewed-by: Eric Yang <Eric.Yang2@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
|
Revision tags: v5.15.7 |
|
| #
64cf26f0 |
| 07-Dec-2021 |
Isabella Basso <isabbasso@riseup.net> |
drm/amd: append missing includes
This fixes warnings caused by global functions lacking prototypes:, such as:
warning: no previous prototype for 'dcn303_hw_sequencer_construct'
[-Wmissing-prototy
drm/amd: append missing includes
This fixes warnings caused by global functions lacking prototypes:, such as:
warning: no previous prototype for 'dcn303_hw_sequencer_construct'
[-Wmissing-prototypes]
12 | void dcn303_hw_sequencer_construct(struct dc *dc)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
...
warning: no previous prototype for ‘amdgpu_has_atpx’
[-Wmissing-prototypes]
76 | bool amdgpu_has_atpx(void) {
| ^~~~~~~~~~~~~~~
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Isabella Basso <isabbasso@riseup.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
|
Revision tags: v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2 |
|
| #
f8fb5cd4 |
| 08-Nov-2021 |
Charlene Liu <Charlene.Liu@amd.com> |
drm/amd/display: based on flag reset z10 function pointer
[Why & How]
Per hardware requirements, add a flag to control
z10 enable/disable.
Reviewed-by: Sung joon Kim <Sungjoon.Kim@amd.com>
Acked-by
drm/amd/display: based on flag reset z10 function pointer
[Why & How]
Per hardware requirements, add a flag to control
z10 enable/disable.
Reviewed-by: Sung joon Kim <Sungjoon.Kim@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
|
Revision tags: v5.15.1, v5.15 |
|
| #
0a068b68 |
| 21-Oct-2021 |
Jake Wang <haonan.wang2@amd.com> |
drm/amd/display: Added HPO HW control shutdown support
[Why]
HPO is only used for DP2.0. HPO HW control should be
disable when not being used to save power.
[How]
Shutdown HPO HW control during ini
drm/amd/display: Added HPO HW control shutdown support
[Why]
HPO is only used for DP2.0. HPO HW control should be
disable when not being used to save power.
[How]
Shutdown HPO HW control during init hw.
Shutdown HPO HW control during stream disable.
Enable HPO HW control during stream enable if DP2.0.
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
|
Revision tags: v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62 |
|
| #
f777bb9a |
| 02-Sep-2021 |
Lai, Derek <Derek.Lai@amd.com> |
drm/amd/display: Added power down on boot for DCN3
[Why]
The change of setting a timer callback on boot for 10 seconds is still
working, just lost power down on boot and power down for DCN3.
[How]
drm/amd/display: Added power down on boot for DCN3
[Why]
The change of setting a timer callback on boot for 10 seconds is still
working, just lost power down on boot and power down for DCN3.
[How]
Added power down on boot and power down for DCN3.
Reviewed-by: Anthony Koo <anthony.koo@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Derek Lai <Derek.Lai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
|
Revision tags: v5.14, v5.10.61 |
|
| #
6077911b |
| 19-Aug-2021 |
Josip Pavic <Josip.Pavic@amd.com> |
drm/amd/display: unblock abm when odm is enabled only on configs that support it
[Why]
When ODM is enabled, ABM is blocked on dcn31 but unblocked on dcn30.
Since the dcn31 firmware is now able to h
drm/amd/display: unblock abm when odm is enabled only on configs that support it
[Why]
When ODM is enabled, ABM is blocked on dcn31 but unblocked on dcn30.
Since the dcn31 firmware is now able to handle ABM interop with ODM, it
is no longer necessary to block ABM when ODM is enabled.
Since the dcn30 firmware does not handle ABM interop with ODM, leaving
that combination unblocked can lead to one side of the screen appearing
brighter than the other.
[How]
When ODM is enabled, unblock abm on dcn31 and block it on dcn30
Reviewed-by: Anthony Koo <anthony.koo@amd.com>
Acked-by: Mikita Lipski <mikita.lipski@amd.com>
Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
a3dffd1d |
| 09-Dec-2021 |
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> |
drm/amd/display: Set optimize_pwr_state for DCN31
[ Upstream commit 33735c1c8d0223170d79dbe166976d9cd7339c7a ]
[Why]
We'll exit optimized power state to do link detection but we won't enter
back in
drm/amd/display: Set optimize_pwr_state for DCN31
[ Upstream commit 33735c1c8d0223170d79dbe166976d9cd7339c7a ]
[Why]
We'll exit optimized power state to do link detection but we won't enter
back into the optimized power state.
This could potentially block s2idle entry depending on the sequencing,
but it also means we're losing some power during the transition period.
[How]
Hook up the handler like DCN21. It was also missed like the
exit_optimized_pwr_state callback.
Fixes: 64b1d0e8d500 ("drm/amd/display: Add DCN3.1 HWSEQ")
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Eric Yang <Eric.Yang2@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
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| #
cc98ef78 |
| 10-Dec-2021 |
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> |
drm/amd/display: Set exit_optimized_pwr_state for DCN31
[ Upstream commit 7e4d2f30df3fb48f75ce9e96867d42bdddab83ac ]
[Why]
SMU now respects the PHY refclk disable request from driver.
This causes
drm/amd/display: Set exit_optimized_pwr_state for DCN31
[ Upstream commit 7e4d2f30df3fb48f75ce9e96867d42bdddab83ac ]
[Why]
SMU now respects the PHY refclk disable request from driver.
This causes a hang during hotplug when PHY refclk was disabled
because it's not being re-enabled and the transmitter control
starts on dc_link_detect.
[How]
We normally would re-enable the clk with exit_optimized_pwr_state
but this is only set on DCN21 and DCN301. Set it for dcn31 as well.
This fixes DMCUB timeouts in the PHY.
Fixes: 64b1d0e8d500 ("drm/amd/display: Add DCN3.1 HWSEQ")
Reviewed-by: Eric Yang <Eric.Yang2@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
|
|
Revision tags: v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49 |
|
| #
234b4fd9 |
| 09-Jul-2021 |
Eric Yang <Eric.Yang2@amd.com> |
drm/amd/display: refactor riommu invalidation wa
[Why]
A cleaner solution, only done once on boot.
[How]
Remove previous workaround and configure an extra
vmid one time on boot
Reviewed-by: Kazlau
drm/amd/display: refactor riommu invalidation wa
[Why]
A cleaner solution, only done once on boot.
[How]
Remove previous workaround and configure an extra
vmid one time on boot
Reviewed-by: Kazlauskas Nicholas <Nicholas.Kazlauskas@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
f586fea8 |
| 05-Aug-2021 |
Jake Wang <haonan.wang2@amd.com> |
drm/amd/display: Ensure DCN save after VM setup
[Why]
DM initializes VM context after DMCUB initialization.
This results in loss of DCN_VM_CONTEXT registers after z10.
[How]
Notify DMCUB when VM se
drm/amd/display: Ensure DCN save after VM setup
[Why]
DM initializes VM context after DMCUB initialization.
This results in loss of DCN_VM_CONTEXT registers after z10.
[How]
Notify DMCUB when VM setup is complete, and have DMCUB
save init registers.
v2: squash in CONFIG_DRM_AMD_DC_DCN3_1 fix
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
71ae580f |
| 05-Aug-2021 |
Jake Wang <haonan.wang2@amd.com> |
drm/amd/display: Ensure DCN save after VM setup
[Why]
DM initializes VM context after DMCUB initialization.
This results in loss of DCN_VM_CONTEXT registers after z10.
[How]
Notify DMCUB when VM se
drm/amd/display: Ensure DCN save after VM setup
[Why]
DM initializes VM context after DMCUB initialization.
This results in loss of DCN_VM_CONTEXT registers after z10.
[How]
Notify DMCUB when VM setup is complete, and have DMCUB
save init registers.
v2: squash in CONFIG_DRM_AMD_DC_DCN3_1 fix
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
bbf87050 |
| 09-Jul-2021 |
Eric Yang <Eric.Yang2@amd.com> |
drm/amd/display: refactor riommu invalidation wa
[Why]
A cleaner solution, only done once on boot.
[How]
Remove previous workaround and configure an extra
vmid one time on boot
Reviewed-by: Kazlau
drm/amd/display: refactor riommu invalidation wa
[Why]
A cleaner solution, only done once on boot.
[How]
Remove previous workaround and configure an extra
vmid one time on boot
Reviewed-by: Kazlauskas Nicholas <Nicholas.Kazlauskas@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
|
Revision tags: v5.13, v5.10.46 |
|
| #
e0f65a85 |
| 14-Jun-2021 |
Mikita Lipski <mikita.lipski@amd.com> |
drm/amd/display: Remove MALL function from DCN3.1
[why]
DCN31 doesn't have MALL in DMUB so to avoid sending unknown commands to
DMUB just remove the function pointer.
[how]
Remove apply_idle_power_
drm/amd/display: Remove MALL function from DCN3.1
[why]
DCN31 doesn't have MALL in DMUB so to avoid sending unknown commands to
DMUB just remove the function pointer.
[how]
Remove apply_idle_power_optimizations from function pointers structure
for DCN31
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|