drm/amd/display: register edp_backlight_control() for DCN301

As made mention of in commit 099303e9a9bd ("drm/amd/display: eDP
intermittent black screen during PnP"), we need to turn off the
display'

drm/amd/display: register edp_backlight_control() for DCN301

As made mention of in commit 099303e9a9bd ("drm/amd/display: eDP
intermittent black screen during PnP"), we need to turn off the
display's backlight before powering off an eDP display. Not doing so
will result in undefined behaviour according to the eDP spec. So, set
DCN301's edp_backlight_control() function pointer to
dce110_edp_backlight_control().

Cc: stable@vger.kernel.org
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2765
Fixes: 9c75891feef0 ("drm/amd/display: rework recent update PHY state commit")
Suggested-by: Swapnil Patel <swapnil.patel@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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drm/amd/display: Add visual confirm color support for MCLK switch

[Why && How]
We would like to have visual confirm color support for MCLK switch.
1. Set visual confirm color to yellow: Vblank MCLK

drm/amd/display: Add visual confirm color support for MCLK switch

[Why && How]
We would like to have visual confirm color support for MCLK switch.
1. Set visual confirm color to yellow: Vblank MCLK switch.
2. Set visual confirm color to cyan: FPO + Vblank MCLK
switch.
3. Set visual confirm color to pink: Vactive MCLK switch.

Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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drm/amd/display: rework recent update PHY state commit

[why]
Original change 594b237b9a07 ("drm/amd/display: Add
interface to track PHY state") was implemented by assuming stream's
dpms off is equiv

drm/amd/display: rework recent update PHY state commit

[why]
Original change 594b237b9a07 ("drm/amd/display: Add
interface to track PHY state") was implemented by assuming stream's
dpms off is equivalent to PHY power off.
This assumption doesn't hold in following situations:
1. MST multiple stream scenario, where multiple streams are sharing the
same PHY output. Toggle dpms off for one of the stream doesn't power
off the PHY due to the presence of other streams.
2. enable stream failure scenario, where enable stream fails due to
failure of link training. This will cause DPMS off is set to false, while
the actual PHY power state is off in certain cases.
Due to the problematic assumption, the logic will skip disabling
other streams for MST multiple stream scenario, therefore PHY is
not actually powered off.

[how]
1. Rework this refactor by moving PHY state update down to hardware
level, where we update PHY state in place when hardware sequencer
is actually changing the power state of the PHY hardware.
2. Reimplement symclk on TX off workaround in place when we are actually
calling transmitter control to power off PHY in dcn32. Note the workaround is
added due to the lack of proper software interface to set TX while keeping
symclk on. We plan to address this interface problem so we can set TX off
only without affecting symclk in future dcn versions.

Fixes: 594b237b9a07 ("drm/amd/display: Add interface to track PHY state")
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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drm/amd: append missing includes

This fixes warnings caused by global functions lacking prototypes:, such as:

warning: no previous prototype for 'dcn303_hw_sequencer_construct'
[-Wmissing-prototy

drm/amd: append missing includes

This fixes warnings caused by global functions lacking prototypes:, such as:

warning: no previous prototype for 'dcn303_hw_sequencer_construct'
[-Wmissing-prototypes]
12 | void dcn303_hw_sequencer_construct(struct dc *dc)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
...
warning: no previous prototype for ‘amdgpu_has_atpx’
[-Wmissing-prototypes]
76 | bool amdgpu_has_atpx(void) {
| ^~~~~~~~~~~~~~~

Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Isabella Basso <isabbasso@riseup.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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drm/amd/display: Refactor visual confirm

[Why + How]
Visual confirm has no asic-specific logic,
so we can refactor and unify these functions
that are currently spread out across multiple
dcn files.

drm/amd/display: Refactor visual confirm

[Why + How]
Visual confirm has no asic-specific logic,
so we can refactor and unify these functions
that are currently spread out across multiple
dcn files.
Add a new hw sequencer interface update_visual_confirm_color,
and a new mpc function pointer set_bg_color.
This will allow visual confirm to updated independently
of MPCC blending updates.

v2: squash in DCN3.1 fixes

Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Revert "drm/amd/display: Refactor and add visual confirm for HW Flip Queue"

This reverts commit 3ca402375a2197579d1029e7fa9d856847fe0e7b.

Recent visual confirm changes are regressing the driver, ca

Revert "drm/amd/display: Refactor and add visual confirm for HW Flip Queue"

This reverts commit 3ca402375a2197579d1029e7fa9d856847fe0e7b.

Recent visual confirm changes are regressing the driver, causing a
black screen on boot in some green sardine configs, or visual confirm
is not updated at all.

Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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drm/amd/display: Refactor and add visual confirm for HW Flip Queue

[Why]
Visual confirm will indicate if driver is programming
the surface address.
Refactor is required because much of the visual co

drm/amd/display: Refactor and add visual confirm for HW Flip Queue

[Why]
Visual confirm will indicate if driver is programming
the surface address.
Refactor is required because much of the visual confirm
logic is buried deep in the mpcc files.
In addition, visual confirm is not updated during fast updates.

[How]
In order to have visual confirm for driver flips, visual confirm
needs to be updated on every frame, including fast updates.
Add a new hw sequencer interface update_visual_confirm_color,
and a new mpc function pointer set_bg_color.

v2: drop unused variable (Alex)

Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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drm/amd/display: Connect clock optimization function to dcn301

[why/how]
Connecting clock optimization functions to dcn301 HWSS
to enable power state enter/exit optimization

Signed-off-by: Mikita L

drm/amd/display: Connect clock optimization function to dcn301

[why/how]
Connecting clock optimization functions to dcn301 HWSS
to enable power state enter/exit optimization

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Acked-by: Bindu Ramamurthy <bindur12@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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drm/amd/display: Add function and debugfs to dump DCC_EN bit

[why]
Currently to view the DCC_EN bit the entire DTN log
must be dumped. A compact method to view the DCC_EN
bit is desirable.

[how]
In

drm/amd/display: Add function and debugfs to dump DCC_EN bit

[why]
Currently to view the DCC_EN bit the entire DTN log
must be dumped. A compact method to view the DCC_EN
bit is desirable.

[how]
Introduce new debugfs interface that only dumps the
DCC_EN bit.

Example usage:
cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en

Signed-off-by: Victor Lu <victorchengchi.lu@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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drm/amd/display: Old sequence for HUBP blank

New proposed sequence for HUBP blanking causes regressions where the
hardware would fail to enter blank which triggers an assert in the new
sequence. Thi

drm/amd/display: Old sequence for HUBP blank

New proposed sequence for HUBP blanking causes regressions where the
hardware would fail to enter blank which triggers an assert in the new
sequence. This change brings back the old sequence.

Fixes: 985faf2c4ecb60 ("drm/amd/display: New sequence for HUBP blank")
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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drm/amd/display: New sequence for HUBP blank

[WHY]
DCN30 has a bug where blanking HUBP blocks pstate allow unless
HUBP_DISABLE is toggled afterwards.

[HOW]
Create a HW sequence for blanking HUBP.
1

drm/amd/display: New sequence for HUBP blank

[WHY]
DCN30 has a bug where blanking HUBP blocks pstate allow unless
HUBP_DISABLE is toggled afterwards.

[HOW]
Create a HW sequence for blanking HUBP.
1. Wait for enter VBLANK
2. Set HUBP_BLANK
3. Make sure HUBP_IN_BLANK = 1
4. Toggle HUBP_DISABLE on and off to perform soft reset

All existing calls to hubp->funcs->set_blank should be replaced with
this new sequence.
In wait_for_mpcc_disconnect, only blank the pipe being disconnected, and
leave all other pipes unmodified.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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drm/amd/display: fix the NULL pointer that missed set_disp_pattern_generator callback

This patch is to fix the NULL pointer that missed set_disp_pattern_generator callback on DCN301

[ 505.054167]

drm/amd/display: fix the NULL pointer that missed set_disp_pattern_generator callback

This patch is to fix the NULL pointer that missed set_disp_pattern_generator callback on DCN301

[ 505.054167] BUG: kernel NULL pointer dereference, address: 0000000000000000
[ 505.054176] #PF: supervisor instruction fetch in kernel mode
[ 505.054181] #PF: error_code(0x0010) - not-present page
[ 505.054185] PGD 0 P4D 0
[ 505.054199] Oops: 0010 [#1] SMP NOPTI
[ 505.054211] CPU: 6 PID: 1306 Comm: modprobe Tainted: G W OE 5.9.0-rc5-custom #1
[ 505.054216] Hardware name: AMD Chachani-VN/Chachani-VN, BIOS WCH0A29N_RAPV16.FD 10/29/2020
[ 505.054225] RIP: 0010:0x0
[ 505.054234] Code: Bad RIP value.
[ 505.054239] RSP: 0018:ffffb88541c66f60 EFLAGS: 00010206
[ 505.054245] RAX: 0000000000000000 RBX: ffff912836070000 RCX: 0000000000000003
[ 505.054248] RDX: 000000000000000c RSI: ffff9128365001e8 RDI: ffff912836070000
[ 505.054252] RBP: ffffb88541c66fd8 R08: 0000000000000002 R09: ffffb88541c66fa2
[ 505.054265] R10: 0000000000009580 R11: 0000000000000008 R12: ffff9128365001e8
[ 505.054272] R13: 000000000000000c R14: 0000000000000438 R15: ffff9128a48bd000
[ 505.054279] FS: 00007f09f999f540(0000) GS:ffff9128b3f80000(0000) knlGS:0000000000000000
[ 505.054284] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 505.054288] CR2: ffffffffffffffd6 CR3: 00000002db98c000 CR4: 0000000000350ee0
[ 505.054291] Call Trace:
[ 505.055024] dcn20_blank_pixel_data+0x148/0x260 [amdgpu]
[ 505.055730] dcn20_enable_stream_timing+0x381/0x47c [amdgpu]
[ 505.056641] dce110_apply_ctx_to_hw+0x337/0x577 [amdgpu]
[ 505.056667] ? put_object+0x2f/0x40
[ 505.057329] dc_commit_state+0x4b3/0x9d0 [amdgpu]
[ 505.058030] amdgpu_dm_atomic_commit_tail+0x405/0x1ec6 [amdgpu]
[ 505.058053] ? update_stack_state+0x103/0x170
[ 505.058071] ? __module_text_address+0x12/0x60

Signed-off-by: Huang Rui <ray.huang@amd.com>
Tested-by: Changfeng <Changfeng.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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drm/amd/display: Update GSL state if leaving immediate flip

[Why]
We should leave GSL if we're not doing immediate flip no matter if
we're doing pipe split or not

[How]
Check for updating GSL state

drm/amd/display: Update GSL state if leaving immediate flip

[Why]
We should leave GSL if we're not doing immediate flip no matter if
we're doing pipe split or not

[How]
Check for updating GSL state whenever we're not doing
immediate flip

v2: Squash in build fix (Alex)

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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drm/amd/display: Add dcn3.01 support to DC (v2)

Update dc for vangogh support.

v2: fix compilation without DCN 301 set.

Signed-off-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alex

drm/amd/display: Add dcn3.01 support to DC (v2)

Update dc for vangogh support.

v2: fix compilation without DCN 301 set.

Signed-off-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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