Revision tags: v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14 |
|
#
88d5cb25 |
| 04-Jan-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/display: drop DCN support for aarch64
From Ard:
"Simply disabling -mgeneral-regs-only left and right is risky, given that the standard AArch64 ABI permits the use of FP/SIMD registers an
drm/amdgpu/display: drop DCN support for aarch64
From Ard:
"Simply disabling -mgeneral-regs-only left and right is risky, given that the standard AArch64 ABI permits the use of FP/SIMD registers anywhere, and GCC is known to use SIMD registers for spilling, and may invent other uses of the FP/SIMD register file that have nothing to do with the floating point code in question. Note that putting kernel_neon_begin() and kernel_neon_end() around the code that does use FP is not sufficient here, the problem is in all the other code that may be emitted with references to SIMD registers in it.
So the only way to do this properly is to put all floating point code in a separate compilation unit, and only compile that unit with -mgeneral-regs-only."
Disable support until the code can be properly refactored to support this properly on aarch64.
Acked-by: Will Deacon <will@kernel.org> Reported-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c241ed2f |
| 04-Jan-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/display: drop DCN support for aarch64
From Ard:
"Simply disabling -mgeneral-regs-only left and right is risky, given that the standard AArch64 ABI permits the use of FP/SIMD registers an
drm/amdgpu/display: drop DCN support for aarch64
From Ard:
"Simply disabling -mgeneral-regs-only left and right is risky, given that the standard AArch64 ABI permits the use of FP/SIMD registers anywhere, and GCC is known to use SIMD registers for spilling, and may invent other uses of the FP/SIMD register file that have nothing to do with the floating point code in question. Note that putting kernel_neon_begin() and kernel_neon_end() around the code that does use FP is not sufficient here, the problem is in all the other code that may be emitted with references to SIMD registers in it.
So the only way to do this properly is to put all floating point code in a separate compilation unit, and only compile that unit with -mgeneral-regs-only."
Disable support until the code can be properly refactored to support this properly on aarch64.
Acked-by: Will Deacon <will@kernel.org> Reported-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
99ea1203 |
| 04-Jan-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/display: drop DCN support for aarch64
commit c241ed2f0ea549c18cff62a3708b43846b84dae3 upstream.
From Ard:
"Simply disabling -mgeneral-regs-only left and right is risky, given that the s
drm/amdgpu/display: drop DCN support for aarch64
commit c241ed2f0ea549c18cff62a3708b43846b84dae3 upstream.
From Ard:
"Simply disabling -mgeneral-regs-only left and right is risky, given that the standard AArch64 ABI permits the use of FP/SIMD registers anywhere, and GCC is known to use SIMD registers for spilling, and may invent other uses of the FP/SIMD register file that have nothing to do with the floating point code in question. Note that putting kernel_neon_begin() and kernel_neon_end() around the code that does use FP is not sufficient here, the problem is in all the other code that may be emitted with references to SIMD registers in it.
So the only way to do this properly is to put all floating point code in a separate compilation unit, and only compile that unit with -mgeneral-regs-only."
Disable support until the code can be properly refactored to support this properly on aarch64.
Acked-by: Will Deacon <will@kernel.org> Reported-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> [ardb: backport to v5.10 by reverting c38d444e44badc55 instead] Acked-by: Alex Deucher <alexander.deucher@amd.com> # v5.10 backport Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Revision tags: v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58 |
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#
c38d444e |
| 08-Aug-2020 |
Daniel Kolesa <daniel@octaforge.org> |
drm/amd/display: add DCN support for aarch64
This adds ARM64 support into the DCN. This mainly enables support for Navi graphics cards. The dcn10 changes haven't been tested, since I don't have the
drm/amd/display: add DCN support for aarch64
This adds ARM64 support into the DCN. This mainly enables support for Navi graphics cards. The dcn10 changes haven't been tested, since I don't have the relevant hardware available, but there is no way to conditionally disable them, so I've done them anyway.
Signed-off-by: Daniel Kolesa <daniel@octaforge.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9 |
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#
78c77382 |
| 29-Oct-2019 |
Anthony Koo <Anthony.Koo@amd.com> |
drm/amd/display: cleanup of function pointer tables
[Why] It is becoming increasingly hard to figure out which function is called on the different DCN versions
[How] 1. Make function pointer table
drm/amd/display: cleanup of function pointer tables
[Why] It is becoming increasingly hard to figure out which function is called on the different DCN versions
[How] 1. Make function pointer table init in its own init.c file 2. Remove other scenarios in hwseq.c file that need to include headers of other DCN versions. (If needed, it should have been done via the function pointers)
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11, v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5, v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16, v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11, v5.1.10, v5.1.9, v5.1.8, v5.1.7, v5.1.6, v5.1.5, v5.1.4, v5.1.3, v5.1.2, v5.1.1, v5.0.14 |
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#
9b93eb47 |
| 07-May-2019 |
Eric Yang <Eric.Yang2@amd.com> |
drm/amd/display: move clk_mgr files to right place
[Why] Better organization
[How] Move clk_mgr files under dc/clk_mgr
Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Yongqiang Sun <yon
drm/amd/display: move clk_mgr files to right place
[Why] Better organization
[How] Move clk_mgr files under dc/clk_mgr
Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.1, v5.0.13, v5.0.12, v5.0.11, v5.0.10 |
|
#
dc88b4a6 |
| 22-Apr-2019 |
Eric Yang <Eric.Yang2@amd.com> |
drm/amd/display: make clk mgr soc specific
[Why] First step of refactoring clk mgr to better handle different ways of handling clock operations. Clock operation policies are soc specific and not jus
drm/amd/display: make clk mgr soc specific
[Why] First step of refactoring clk mgr to better handle different ways of handling clock operations. Clock operation policies are soc specific and not just DCN vesion specific. It is not a hw resource, should not be in the resource pool.
[How] Change clock manager creation to be based on HW internal ID, rename clock manager members to be more clear. Move clock manager out of resource.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.0.9, v5.0.8, v5.0.7, v5.0.6, v5.0.5, v5.0.4, v5.0.3, v4.19.29, v5.0.2, v4.19.28, v5.0.1, v4.19.27, v5.0, v4.19.26, v4.19.25, v4.19.24, v4.19.23, v4.19.22, v4.19.21, v4.19.20, v4.19.19, v4.19.18, v4.19.17, v4.19.16, v4.19.15, v4.19.14, v4.19.13, v4.19.12, v4.19.11, v4.19.10, v4.19.9, v4.19.8, v4.19.7, v4.19.6, v4.19.5, v4.19.4, v4.18.20, v4.19.3, v4.18.19, v4.19.2, v4.18.18, v4.18.17, v4.19.1, v4.19, v4.18.16, v4.18.15, v4.18.14, v4.18.13, v4.18.12, v4.18.11 |
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#
84e7fc05 |
| 28-Sep-2018 |
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> |
drm/amd/display: rename dccg to clk_mgr
In preparation for adding the actual dccg block since the current implementation of dccg is mor eof a clock manager than a hw block
Signed-off-by: Dmytro Lak
drm/amd/display: rename dccg to clk_mgr
In preparation for adding the actual dccg block since the current implementation of dccg is mor eof a clock manager than a hw block
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v4.18.10 |
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#
4c5e8b54 |
| 24-Sep-2018 |
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> |
drm/amd/display: split dccg clock manager into asic folders
Currently dccg contains code related to every dcn revision in a single file.
This change splits out the dcn parts of code into correct fo
drm/amd/display: split dccg clock manager into asic folders
Currently dccg contains code related to every dcn revision in a single file.
This change splits out the dcn parts of code into correct folders
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v4.18.9, v4.18.7, v4.18.6, v4.18.5, v4.17.18, v4.18.4, v4.18.3, v4.17.17, v4.18.2, v4.17.16, v4.17.15, v4.18.1, v4.18, v4.17.14 |
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#
dd730435 |
| 08-Aug-2018 |
Jun Lei <Jun.Lei@amd.com> |
drm/amd/display: implement DPMS DTN test v2
[why] Existing DTN infrastructure in driver is hacky. It uses implicit log names, and also incorrect escape ID.
[how] - Implement using generic DTN esca
drm/amd/display: implement DPMS DTN test v2
[why] Existing DTN infrastructure in driver is hacky. It uses implicit log names, and also incorrect escape ID.
[how] - Implement using generic DTN escape ID. - Move file logging functionality from driver to to script; driver now outputs to string/buffer - Move HWSS debug functionality to separate c file - Add debug functionalty for per-block logging as CSV - Add pretty print in python
Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v4.17.13, v4.17.12, v4.17.11, v4.17.10, v4.17.9, v4.17.8, v4.17.7, v4.17.6, v4.17.5, v4.17.4, v4.17.3, v4.17.2, v4.17.1, v4.17 |
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#
f0cd0a34 |
| 26-Apr-2018 |
Eric Bernstein <eric.bernstein@amd.com> |
drm/amd/display: DCN1 link encoder
Create DCN1 link encoder files and update AUX and HPD register access.
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@
drm/amd/display: DCN1 link encoder
Create DCN1 link encoder files and update AUX and HPD register access.
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v4.16 |
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#
0c41891c |
| 19-Mar-2018 |
Eric Bernstein <eric.bernstein@amd.com> |
drm/amd/display: Refactor stream encoder for HW review
Move DCN1 implementation of stream encoder to new file (instead of common dce_stream_encoder.c). Cleanup code related to different implementati
drm/amd/display: Refactor stream encoder for HW review
Move DCN1 implementation of stream encoder to new file (instead of common dce_stream_encoder.c). Cleanup code related to different implementation due to register definition differences.
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v4.15 |
|
#
b51adc77 |
| 04-Dec-2017 |
Yue Hin Lau <Yuehin.Lau@amd.com> |
drm/amd/display: Only blank DCN when we have set_blank implementation
Also rename timing_generator to optc
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstei
drm/amd/display: Only blank DCN when we have set_blank implementation
Also rename timing_generator to optc
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1a09120f |
| 30-Nov-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add license to Makefiles
Was missing license text.
Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christi
drm/amdgpu: add license to Makefiles
Was missing license text.
Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v4.13.16, v4.14 |
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#
62d591a8 |
| 18-Oct-2017 |
Yue Hin Lau <Yuehin.Lau@amd.com> |
drm/amd/display: create new files for hubbub functions
moving hubbub functions to new file
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Har
drm/amd/display: create new files for hubbub functions
moving hubbub functions to new file
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e2874a3c |
| 30-Nov-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add license to Makefiles
Was missing license text.
Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christi
drm/amdgpu: add license to Makefiles
Was missing license text.
Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
86be9a04 |
| 05-Oct-2017 |
Yue Hin Lau <Yuehin.Lau@amd.com> |
drm/amd/display: renaming filename for hubp
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-
drm/amd/display: renaming filename for hubp
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v4.13.5 |
|
#
024f0607 |
| 11-Sep-2017 |
Yue Hin Lau <Yuehin.Lau@amd.com> |
drm/amd/display: Refactor dcn10_dpp_cm_helper to dcn10_cm_common
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland
drm/amd/display: Refactor dcn10_dpp_cm_helper to dcn10_cm_common
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a2e74cb6 |
| 28-Sep-2017 |
Harry Wentland <harry.wentland@amd.com> |
drm/amd/display: Remove DWB
It's not in a good shape and currently completely unused.
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signe
drm/amd/display: Remove DWB
It's not in a good shape and currently completely unused.
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v4.13 |
|
#
83524646 |
| 29-Aug-2017 |
Yue Hin Lau <Yuehin.Lau@amd.com> |
drm/amd/display: seperate dpp_cm_helper functions into new file
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@
drm/amd/display: seperate dpp_cm_helper functions into new file
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
dff2721b |
| 17-Aug-2017 |
Yue Hin Lau <Yuehin.Lau@amd.com> |
drm/amd/display: separate cm functions out from dcn10_dpp
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.co
drm/amd/display: separate cm functions out from dcn10_dpp
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5e9a81b2 |
| 15-Aug-2017 |
Yue Hin Lau <Yuehin.Lau@amd.com> |
drm/amd/display: separate scl functions out from dcn10_dpp
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.c
drm/amd/display: separate scl functions out from dcn10_dpp
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
391e20d8 |
| 03-Aug-2017 |
Duke Du <Duke.Du@amd.com> |
drm/amd/display: add display write back(DWB)
Signed-off-by: Duke Du <Duke.Du@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Al
drm/amd/display: add display write back(DWB)
Signed-off-by: Duke Du <Duke.Du@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
587cdfe9 |
| 05-Jul-2017 |
Vitaly Prosyak <vitaly.prosyak@amd.com> |
drm/amd/display: Rename trasnform to dpp for dcn's
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.co
drm/amd/display: Rename trasnform to dpp for dcn's
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v4.12, v4.10.17, v4.10.16 |
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#
70ccab60 |
| 08-May-2017 |
Harry Wentland <harry.wentland@amd.com> |
drm/amdgpu/display: Add core dc support for DCN
Core display support for DCN.
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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