#
00737c59 |
| 29-Oct-2018 |
Eric Bernstein <eric.bernstein@amd.com> |
drm/amd/display: get tail pipe before aquire free pipe
[Why] For some complicated blending transition cases, the head pipe of the second stream may end up being a higher pipe index than the free pip
drm/amd/display: get tail pipe before aquire free pipe
[Why] For some complicated blending transition cases, the head pipe of the second stream may end up being a higher pipe index than the free pipe. In those cases dc_add_plane_to_context will incorrectly set the tail_pipe to the free pipe, which will cause the top_pipe and bottom_pipe to be the same
[How] Move the call to resource_get_tail_pipe_for_stream() to be before call to acquire_free_pipe_for_stream().
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9b6067c0 |
| 19-Oct-2018 |
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> |
drm/amd/display: redesign scaling rotation math
Change the math to work in viewport rotation when calculating viewport and viewport adjustment. This simplifies the math for viewport calculation and
drm/amd/display: redesign scaling rotation math
Change the math to work in viewport rotation when calculating viewport and viewport adjustment. This simplifies the math for viewport calculation and makes viewport adjustment easier to understand.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
08e1c28d |
| 19-Oct-2018 |
Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com> |
drm/amd/display: calculate stream->phy_pix_clk before clock mapping
[why] phy_pix_clk is one of the variable used to check if one PLL can be shared with displays having common mode set configuration
drm/amd/display: calculate stream->phy_pix_clk before clock mapping
[why] phy_pix_clk is one of the variable used to check if one PLL can be shared with displays having common mode set configuration. As of now phy_pix_clock varialbe is calculated in function dc_validate_stream(). dc_validate_stream() function is called after clocks are assigned for the new display. Due to this during hotplug, when PLL sharing conditions are checked for new display phy_pix_clk variable will be 0 and for displays that are already enabled phy_pix_clk will have some value. Hence PLL will not be shared and if the display hardware doesn't have any more PLL to assign, mode set will fail due to resource unavailability.
[how] Instead of only calculating the phy_pix_clk variable after the PLL is assigned for new display, this patch calculates phy_pix_clk also during the before assigning the PLL for new display.
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
eb9714a2 |
| 22-Oct-2018 |
Wenjing Liu <Wenjing.Liu@amd.com> |
drm/amd/display: resolve minor log problems
[Why] dc_add_stream_to_context is used to check bw requirement. It is not an error if it fails.
[How] Replace DC_ERROR with DC_LOG_WARNING.
Signed-off-b
drm/amd/display: resolve minor log problems
[Why] dc_add_stream_to_context is used to check bw requirement. It is not an error if it fails.
[How] Replace DC_ERROR with DC_LOG_WARNING.
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
83d40659 |
| 16-Oct-2018 |
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> |
drm/amd/display: fix mirror rotation scaling math
Curretly dc will incorrectly calculate viewport when there is rotation or mirror being applied
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushki
drm/amd/display: fix mirror rotation scaling math
Curretly dc will incorrectly calculate viewport when there is rotation or mirror being applied
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Su Chung <Su.Chung@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ddc07a38 |
| 12-Oct-2018 |
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> |
drm/amd/display: remove interlace scaling adjustment
We do not need to adjust surface scaling when p2i is enabled and we do not support interlaced timing otherwise
Signed-off-by: Dmytro Laktyushkin
drm/amd/display: remove interlace scaling adjustment
We do not need to adjust surface scaling when p2i is enabled and we do not support interlaced timing otherwise
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
84e7fc05 |
| 28-Sep-2018 |
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> |
drm/amd/display: rename dccg to clk_mgr
In preparation for adding the actual dccg block since the current implementation of dccg is mor eof a clock manager than a hw block
Signed-off-by: Dmytro Lak
drm/amd/display: rename dccg to clk_mgr
In preparation for adding the actual dccg block since the current implementation of dccg is mor eof a clock manager than a hw block
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
24f7dd7e |
| 13-Sep-2018 |
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> |
drm/amd/display: move pplib/smu notification to dccg block
This is done to clear up the clock programming sequence since the only time we need to notify pplib is after clock update.
This also renam
drm/amd/display: move pplib/smu notification to dccg block
This is done to clear up the clock programming sequence since the only time we need to notify pplib is after clock update.
This also renames the clk block to dccg, at the moment this block contains both clock management and dccg functionality.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
74eac5f3 |
| 13-Sep-2018 |
Su Sung Chung <Su.Chung@amd.com> |
drm/amd/display: Calculate swizzle mode using bpp during validation
[Why] Previously bandwidth validation was failing because swizzle mode was not initialized during plane_state allocation. The swiz
drm/amd/display: Calculate swizzle mode using bpp during validation
[Why] Previously bandwidth validation was failing because swizzle mode was not initialized during plane_state allocation. The swizzle mode was calculated using pixed format which is how swizzle mode is initially calculated in addrlib.
[How] * Set default swizzle mode for validation to DC_SW_UNKNOWN * Created new function in dcn10_assign_swizzle_mode which sets the plane swizzle mode based on selected pixed format * Added the call of assign_swizzle_mode into dc_validate_global_state * Set failsafe swizzle mode back to DC_SW_LINEAR
Signed-off-by: Su Sung Chung <Su.Chung@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
39c03e00 |
| 12-Sep-2018 |
Charlene Liu <charlene.liu@amd.com> |
drm/amd/display: fix 4K stereo screen flash issue
[Why] HDMI_scramber is not enabled for pixel rate >340Mhz. [How] Calculate the phy clock to include the Hw frame packing factor.
Signed-off-by: Cha
drm/amd/display: fix 4K stereo screen flash issue
[Why] HDMI_scramber is not enabled for pixel rate >340Mhz. [How] Calculate the phy clock to include the Hw frame packing factor.
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d77f778e |
| 27-Aug-2018 |
Charlene Liu <charlene.liu@amd.com> |
drm/amd/display: Fix 3D stereo issues.
We were not providing the correct pixel clocks to DML for marks calculation.
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushki
drm/amd/display: Fix 3D stereo issues.
We were not providing the correct pixel clocks to DML for marks calculation.
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v4.17.11, v4.17.10, v4.17.9, v4.17.8, v4.17.7, v4.17.6, v4.17.5, v4.17.4, v4.17.3, v4.17.2, v4.17.1, v4.17, v4.16, v4.15 |
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#
0e3d73f1 |
| 22-Jan-2018 |
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> |
drm/amd/display: Add Raven2 definitions in dc
Add Raven2 definitions in the dc code
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com>
drm/amd/display: Add Raven2 definitions in dc
Add Raven2 definitions in the dc code
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
cae50a43 |
| 24-Aug-2018 |
Eric Yang <Eric.Yang2@amd.com> |
drm/amd/display: use link type to decide stream enc acquisition
[Why] Virtual sink is used when set mode happens on a disconnected display to allow the mode set to proceed. This did not work with MS
drm/amd/display: use link type to decide stream enc acquisition
[Why] Virtual sink is used when set mode happens on a disconnected display to allow the mode set to proceed. This did not work with MST because the logic for acquiring stream encoder uses stream signal to determine the special handling is required, and stream signal is virtual instead of DP in this case.
[How] Use link type to decide instead.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
43fbbe89 |
| 14-Aug-2018 |
Dan Carpenter <dan.carpenter@oracle.com> |
drm/amd/display: indent an if statement
The if statement isn't indented and it makes static checkers complain.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Harry Wentland <h
drm/amd/display: indent an if statement
The if statement isn't indented and it makes static checkers complain.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1336926f |
| 04-Jun-2018 |
Alvin lee <alvin.lee3@amd.com> |
drm/amd/display: Enable Stereo in Dal3
- program infoframe for Stereo - program stereo flip control registers properly
v2: Add missing license headers
Signed-off-by: Alvin lee <alvin.lee3@amd.com>
drm/amd/display: Enable Stereo in Dal3
- program infoframe for Stereo - program stereo flip control registers properly
v2: Add missing license headers
Signed-off-by: Alvin lee <alvin.lee3@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1e7e86c4 |
| 01-May-2018 |
Samson Tam <Samson.Tam@amd.com> |
drm/amd/display: decouple front and backend pgm using dpms_off as backend enable flag
Signed-off-by: Samson Tam <Samson.Tam@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry We
drm/amd/display: decouple front and backend pgm using dpms_off as backend enable flag
Signed-off-by: Samson Tam <Samson.Tam@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
98e6436d |
| 21-Aug-2018 |
Anthony Koo <Anthony.Koo@amd.com> |
drm/amd/display: Refactor FreeSync module
Remove dependency on internal sink map and instead use existing stream and plane state
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Signed-off-by: Harr
drm/amd/display: Refactor FreeSync module
Remove dependency on internal sink map and instead use existing stream and plane state
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
94a4ffd1 |
| 26-Jul-2018 |
Gloria Li <geling.li@amd.com> |
drm/amd/display: fix PIP bugs on Dal3
[Why] There are outstanding bugs for PIP in Dal3: -Crash when toggling PIP visibility -Global Alpha is not working, Adjusting global alpha doesn’t have an effe
drm/amd/display: fix PIP bugs on Dal3
[Why] There are outstanding bugs for PIP in Dal3: -Crash when toggling PIP visibility -Global Alpha is not working, Adjusting global alpha doesn’t have an effect -Cursor is not working with pip plane and pipe splits -One flash occurs when cursor enters PIP plane from top/bottom -Crash when moving PIP plane off the screen
[How] Resolve divide by 0 error Implement global alpha Program cursor on all pipes Add dst rects' x and y offests into cursor position Disable cursor when it is beyond bottom/top edge
Signed-off-by: Gloria Li <geling.li@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9b5349f7 |
| 27-Jul-2018 |
Martin Tsai <Martin.Tsai@amd.com> |
drm/amd/display: correct image viewport calculation
[why] We didn't transfer the camera/video viewport coordinate when doing rotation and mirror.
[how] To correct the viewport coordinate in calcula
drm/amd/display: correct image viewport calculation
[why] We didn't transfer the camera/video viewport coordinate when doing rotation and mirror.
[how] To correct the viewport coordinate in calculate_viewport().
Signed-off-by: Martin Tsai <Martin.Tsai@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
dc37a9a0 |
| 16-Aug-2018 |
Leo (Sunpeng) Li <sunpeng.li@amd.com> |
Revert "drm/amdgpu/display: Replace CONFIG_DRM_AMD_DC_DCN1_0 with CONFIG_X86"
This reverts commit 8624c3c4dbfe24fc6740687236a2e196f5f4bfb0.
We need CONFIG_DRM_AMD_DC_DCN1_0 to guard code that is us
Revert "drm/amdgpu/display: Replace CONFIG_DRM_AMD_DC_DCN1_0 with CONFIG_X86"
This reverts commit 8624c3c4dbfe24fc6740687236a2e196f5f4bfb0.
We need CONFIG_DRM_AMD_DC_DCN1_0 to guard code that is using fp math.
Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ad8960a6 |
| 02-Aug-2018 |
Mikita Lipski <mikita.lipski@amd.com> |
drm/amd/display: Check if clock source in use before disabling
[why] We are disabling clock source while other pipes are still using it, because we don't verify the number of pipes that share it.
[
drm/amd/display: Check if clock source in use before disabling
[why] We are disabling clock source while other pipes are still using it, because we don't verify the number of pipes that share it.
[how] - Adding a function in resources to return the number of pipes sharing the clock source. - Checking that no one is sharing the clock source before disabling
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
fc69009e |
| 16-Jul-2018 |
Mikita Lipski <mikita.lipski@amd.com> |
drm/amd/display: Allow clock sharing b/w HDMI and DVI
[why] HDMI and DVI share the same PHY clock and single link DVI and HDMI both use 4 lanes, so they should be allowed to be sharing the same cloc
drm/amd/display: Allow clock sharing b/w HDMI and DVI
[why] HDMI and DVI share the same PHY clock and single link DVI and HDMI both use 4 lanes, so they should be allowed to be sharing the same clock source if all other parameters are satisfied.
[how] Change a check for general DVI to Dual DVI.
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3e27e10e |
| 12-Jul-2018 |
Mikita Lipski <mikita.lipski@amd.com> |
drm/amd/display: Don't share clk source between DP and HDMI
[why] Prevent clock source sharing between HDMI and DP connectors. DP shouldn't be sharing its ref clock with phy clock, which caused an i
drm/amd/display: Don't share clk source between DP and HDMI
[why] Prevent clock source sharing between HDMI and DP connectors. DP shouldn't be sharing its ref clock with phy clock, which caused an issue of older ASICS booting up with multiple diplays plugged in.
[how] Add an extra check that would prevent HDMI and DP sharing clk.
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
48412031 |
| 17-Jul-2018 |
Michel Dänzer <michel.daenzer@amd.com> |
drm/amdgpu/display: Replace CONFIG_DRM_AMD_DC_DCN1_0 with CONFIG_X86
Allowing CONFIG_DRM_AMD_DC_DCN1_0 to be disabled on X86 was an opportunity for display with Raven Ridge accidentally not working.
drm/amdgpu/display: Replace CONFIG_DRM_AMD_DC_DCN1_0 with CONFIG_X86
Allowing CONFIG_DRM_AMD_DC_DCN1_0 to be disabled on X86 was an opportunity for display with Raven Ridge accidentally not working.
Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ece4147f |
| 27-Jun-2018 |
Ken Chalmers <ken.chalmers@amd.com> |
drm/amd/display: Fix new stream count check in dc_add_stream_to_ctx
[Why] The previous code could allow through attempts to enable more streams than there are timing generators, in designs where the
drm/amd/display: Fix new stream count check in dc_add_stream_to_ctx
[Why] The previous code could allow through attempts to enable more streams than there are timing generators, in designs where the number of pipes is greater than the number of timing generators.
[How] Compare the new stream count to the resource pool's timing generator count, instead of its pipe count. Also correct a typo in the error message.
Signed-off-by: Ken Chalmers <ken.chalmers@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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