| #
5ea6f9c2 |
| 14-Jul-2020 |
Chengming Gui <Jack.Gui@amd.com> |
drm/amdgpu: add timeout flush mechanism to update wptr for self interrupt (v2)
outstanding log reaches threshold will trigger IH ring1/2's wptr
reported, that will avoid generating inter
drm/amdgpu: add timeout flush mechanism to update wptr for self interrupt (v2)
outstanding log reaches threshold will trigger IH ring1/2's wptr
reported, that will avoid generating interrupts to ring0 too frequent.
But if ring1/2's wptr hasn't been increased for a long time, the outstanding log
can't reach threshold so that driver can't get latest wptr info and
miss some interrupts.
v2: squash in warning fix
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
|
Revision tags: v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20 |
|
| #
026c396b |
| 12-Feb-2020 |
Jiansong Chen <Jiansong.Chen@amd.com> |
drm/amdgpu: add ih ip block for navy_flounder
navy_flounder has the same osssys IP verison with
sienna_cichlid, follow its setting.
Signed-off-by: Jiansong Chen <Jiansong.Chen@a
drm/amdgpu: add ih ip block for navy_flounder
navy_flounder has the same osssys IP verison with
sienna_cichlid, follow its setting.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
|
Revision tags: v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11, v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5, v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16, v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11 |
|
| #
757b3af8 |
| 16-Jun-2019 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: add ih ip block for sienna_cichlid
Update IH handling for sienna_cichlid
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.c
drm/amdgpu: add ih ip block for sienna_cichlid
Update IH handling for sienna_cichlid
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
193cce34 |
| 01-Apr-2020 |
Alex Sierra <alex.sierra@amd.com> |
amdgpu/drm: remove psp access on navi10 for sriov
Navi ASICs don't require to access through PSP to osssys registers.
This on SR-IOV configuration.
Signed-off-by: Alex Sierra <a
amdgpu/drm: remove psp access on navi10 for sriov
Navi ASICs don't require to access through PSP to osssys registers.
This on SR-IOV configuration.
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
9e94ff33 |
| 23-Mar-2020 |
Alex Sierra <alex.sierra@amd.com> |
drm/amdgpu: reroute VMC and UMD to IH ring 1 for oss v5
[Why]
Due Page faults can easily overwhelm the interrupt handler.
So to make sure that we never lose valuable interrupts on th
drm/amdgpu: reroute VMC and UMD to IH ring 1 for oss v5
[Why]
Due Page faults can easily overwhelm the interrupt handler.
So to make sure that we never lose valuable interrupts on the primary ring
we re-route page faults to IH ring 1.
It also facilitates the recovery page process, since it's already
running from a process context.
This is valid for Arcturus and future Navi generation GPUs.
[How]
Setting IH_CLIENT_CFG_DATA for VMC and UMD IH clients.
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
0ab176e6 |
| 23-Mar-2020 |
Alex Sierra <alex.sierra@amd.com> |
drm/amdgpu: call psp to program ih cntl in SR-IOV for Navi
call psp to program ih cntl in SR-IOV if supported on Navi and Arcturus.
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
drm/amdgpu: call psp to program ih cntl in SR-IOV for Navi
call psp to program ih cntl in SR-IOV if supported on Navi and Arcturus.
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
ab518012 |
| 23-Mar-2020 |
Alex Sierra <alex.sierra@amd.com> |
drm/amdgpu: enable IH ring 1 and ring 2 for navi
Support added into IH to enable ring1 and ring2 for navi10_ih.
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Reviewed-by: Fel
drm/amdgpu: enable IH ring 1 and ring 2 for navi
Support added into IH to enable ring1 and ring2 for navi10_ih.
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
022b6518 |
| 06-Feb-2020 |
Samir Dhume <samir.dhume@amd.com> |
drm/amdgpu: Rearm IRQ in Navi10 SR-IOV if IRQ lost
Ported from Vega10. SDMA stress tests sometimes see IRQ lost.
Signed-off-by: Samir Dhume <samir.dhume@amd.com>
Reviewed-by: Mo
drm/amdgpu: Rearm IRQ in Navi10 SR-IOV if IRQ lost
Ported from Vega10. SDMA stress tests sometimes see IRQ lost.
Signed-off-by: Samir Dhume <samir.dhume@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
a9d4fe2f |
| 20-Jan-2020 |
Nirmoy Das <nirmoy.das@amd.com> |
drm/amdgpu: remove unnecessary conversion to bool
Better clean that up before some automation starts to complain about it
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
Acked-b
drm/amdgpu: remove unnecessary conversion to bool
Better clean that up before some automation starts to complain about it
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
7eca4006 |
| 20-Dec-2019 |
Ma Feng <mafeng.ma@huawei.com> |
drm/amdgpu: Remove unneeded variable 'ret' in navi10_ih.c
Fixes coccicheck warning:
drivers/gpu/drm/amd/amdgpu/navi10_ih.c:113:5-8: Unneeded variable: "ret". Return "0" on line 182
drm/amdgpu: Remove unneeded variable 'ret' in navi10_ih.c
Fixes coccicheck warning:
drivers/gpu/drm/amd/amdgpu/navi10_ih.c:113:5-8: Unneeded variable: "ret". Return "0" on line 182
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Ma Feng <mafeng.ma@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
bebc0762 |
| 23-Aug-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to new amdgpu_nbio structure
no functional change, just switch to new structures
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deuche
drm/amdgpu: switch to new amdgpu_nbio structure
no functional change, just switch to new structures
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
b23b2e9e |
| 31-Jul-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: drop drmP.h from navi10_ih.c
And fix the fallout.
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
Revision tags: v5.1.10, v5.1.9, v5.1.8, v5.1.7, v5.1.6, v5.1.5, v5.1.4, v5.1.3, v5.1.2, v5.1.1, v5.0.14, v5.1, v5.0.13, v5.0.12, v5.0.11, v5.0.10, v5.0.9, v5.0.8, v5.0.7, v5.0.6, v5.0.5, v5.0.4, v5.0.3, v4.19.29, v5.0.2, v4.19.28, v5.0.1, v4.19.27, v5.0 |
|
| #
edc61147 |
| 02-Mar-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add navi10 ih ip block (v3)
IH is the interrupt handler block.
v1: add initial ih support (Ray)
v2: add dummy prescreen iv function for navi10 (Hawking)
v3: squa
drm/amdgpu: add navi10 ih ip block (v3)
IH is the interrupt handler block.
v1: add initial ih support (Ray)
v2: add dummy prescreen iv function for navi10 (Hawking)
v3: squash in additional updates (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|