1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 29 #include "oss/osssys_5_0_0_offset.h" 30 #include "oss/osssys_5_0_0_sh_mask.h" 31 32 #include "soc15_common.h" 33 #include "navi10_ih.h" 34 35 #define MAX_REARM_RETRY 10 36 37 #define mmIH_CHICKEN_Sienna_Cichlid 0x018d 38 #define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0 39 40 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 41 42 /** 43 * navi10_ih_enable_interrupts - Enable the interrupt ring buffer 44 * 45 * @adev: amdgpu_device pointer 46 * 47 * Enable the interrupt ring buffer (NAVI10). 48 */ 49 static void navi10_ih_enable_interrupts(struct amdgpu_device *adev) 50 { 51 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 52 53 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 54 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 55 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 56 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 57 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 58 return; 59 } 60 } else { 61 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 62 } 63 64 adev->irq.ih.enabled = true; 65 66 if (adev->irq.ih1.ring_size) { 67 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 68 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 69 RB_ENABLE, 1); 70 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 71 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 72 ih_rb_cntl)) { 73 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 74 return; 75 } 76 } else { 77 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 78 } 79 adev->irq.ih1.enabled = true; 80 } 81 82 if (adev->irq.ih2.ring_size) { 83 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 84 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 85 RB_ENABLE, 1); 86 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 87 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 88 ih_rb_cntl)) { 89 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 90 return; 91 } 92 } else { 93 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 94 } 95 adev->irq.ih2.enabled = true; 96 } 97 } 98 99 /** 100 * navi10_ih_disable_interrupts - Disable the interrupt ring buffer 101 * 102 * @adev: amdgpu_device pointer 103 * 104 * Disable the interrupt ring buffer (NAVI10). 105 */ 106 static void navi10_ih_disable_interrupts(struct amdgpu_device *adev) 107 { 108 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 109 110 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 111 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 112 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 113 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 114 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 115 return; 116 } 117 } else { 118 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 119 } 120 121 /* set rptr, wptr to 0 */ 122 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 123 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 124 adev->irq.ih.enabled = false; 125 adev->irq.ih.rptr = 0; 126 127 if (adev->irq.ih1.ring_size) { 128 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 129 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 130 RB_ENABLE, 0); 131 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 132 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 133 ih_rb_cntl)) { 134 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 135 return; 136 } 137 } else { 138 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 139 } 140 /* set rptr, wptr to 0 */ 141 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 142 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 143 adev->irq.ih1.enabled = false; 144 adev->irq.ih1.rptr = 0; 145 } 146 147 if (adev->irq.ih2.ring_size) { 148 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 149 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 150 RB_ENABLE, 0); 151 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 152 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 153 ih_rb_cntl)) { 154 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 155 return; 156 } 157 } else { 158 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 159 } 160 /* set rptr, wptr to 0 */ 161 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 162 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 163 adev->irq.ih2.enabled = false; 164 adev->irq.ih2.rptr = 0; 165 } 166 167 } 168 169 static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 170 { 171 int rb_bufsz = order_base_2(ih->ring_size / 4); 172 173 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 174 MC_SPACE, ih->use_bus_addr ? 1 : 4); 175 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 176 WPTR_OVERFLOW_CLEAR, 1); 177 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 178 WPTR_OVERFLOW_ENABLE, 1); 179 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 180 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 181 * value is written to memory 182 */ 183 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 184 WPTR_WRITEBACK_ENABLE, 1); 185 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 186 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 187 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 188 189 return ih_rb_cntl; 190 } 191 192 static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 193 { 194 u32 ih_doorbell_rtpr = 0; 195 196 if (ih->use_doorbell) { 197 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 198 IH_DOORBELL_RPTR, OFFSET, 199 ih->doorbell_index); 200 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 201 IH_DOORBELL_RPTR, 202 ENABLE, 1); 203 } else { 204 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 205 IH_DOORBELL_RPTR, 206 ENABLE, 0); 207 } 208 return ih_doorbell_rtpr; 209 } 210 211 static void navi10_ih_reroute_ih(struct amdgpu_device *adev) 212 { 213 uint32_t tmp; 214 215 /* Reroute to IH ring 1 for VMC */ 216 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12); 217 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 218 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 219 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 220 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 221 222 /* Reroute IH ring 1 for UMC */ 223 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B); 224 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 225 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 226 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 227 } 228 229 /** 230 * navi10_ih_irq_init - init and enable the interrupt ring 231 * 232 * @adev: amdgpu_device pointer 233 * 234 * Allocate a ring buffer for the interrupt controller, 235 * enable the RLC, disable interrupts, enable the IH 236 * ring buffer and enable it (NAVI). 237 * Called at device load and reume. 238 * Returns 0 for success, errors for failure. 239 */ 240 static int navi10_ih_irq_init(struct amdgpu_device *adev) 241 { 242 struct amdgpu_ih_ring *ih = &adev->irq.ih; 243 u32 ih_rb_cntl, ih_chicken; 244 u32 tmp; 245 246 /* disable irqs */ 247 navi10_ih_disable_interrupts(adev); 248 249 adev->nbio.funcs->ih_control(adev); 250 251 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 252 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); 253 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); 254 255 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 256 ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 257 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 258 !!adev->irq.msi_enabled); 259 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 260 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 261 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 262 return -ETIMEDOUT; 263 } 264 } else { 265 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 266 } 267 navi10_ih_reroute_ih(adev); 268 269 if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) { 270 if (ih->use_bus_addr) { 271 switch (adev->asic_type) { 272 case CHIP_SIENNA_CICHLID: 273 case CHIP_NAVY_FLOUNDER: 274 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid); 275 ih_chicken = REG_SET_FIELD(ih_chicken, 276 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 277 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken); 278 break; 279 default: 280 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 281 ih_chicken = REG_SET_FIELD(ih_chicken, 282 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 283 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 284 break; 285 } 286 } 287 } 288 289 /* set the writeback address whether it's enabled or not */ 290 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 291 lower_32_bits(ih->wptr_addr)); 292 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 293 upper_32_bits(ih->wptr_addr) & 0xFFFF); 294 295 /* set rptr, wptr to 0 */ 296 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 297 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 298 299 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, 300 navi10_ih_doorbell_rptr(ih)); 301 302 adev->nbio.funcs->ih_doorbell_range(adev, ih->use_doorbell, 303 ih->doorbell_index); 304 305 ih = &adev->irq.ih1; 306 if (ih->ring_size) { 307 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); 308 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, 309 (ih->gpu_addr >> 40) & 0xff); 310 311 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 312 ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 313 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 314 WPTR_OVERFLOW_ENABLE, 0); 315 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 316 RB_FULL_DRAIN_ENABLE, 1); 317 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 318 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 319 ih_rb_cntl)) { 320 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 321 return -ETIMEDOUT; 322 } 323 } else { 324 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 325 } 326 /* set rptr, wptr to 0 */ 327 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 328 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 329 330 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, 331 navi10_ih_doorbell_rptr(ih)); 332 } 333 334 ih = &adev->irq.ih2; 335 if (ih->ring_size) { 336 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); 337 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, 338 (ih->gpu_addr >> 40) & 0xff); 339 340 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 341 ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 342 343 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 344 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 345 ih_rb_cntl)) { 346 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 347 return -ETIMEDOUT; 348 } 349 } else { 350 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 351 } 352 /* set rptr, wptr to 0 */ 353 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 354 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 355 356 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, 357 navi10_ih_doorbell_rptr(ih)); 358 } 359 360 361 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 362 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 363 CLIENT18_IS_STORM_CLIENT, 1); 364 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 365 366 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 367 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 368 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 369 370 pci_set_master(adev->pdev); 371 372 /* enable interrupts */ 373 navi10_ih_enable_interrupts(adev); 374 375 return 0; 376 } 377 378 /** 379 * navi10_ih_irq_disable - disable interrupts 380 * 381 * @adev: amdgpu_device pointer 382 * 383 * Disable interrupts on the hw (NAVI10). 384 */ 385 static void navi10_ih_irq_disable(struct amdgpu_device *adev) 386 { 387 navi10_ih_disable_interrupts(adev); 388 389 /* Wait and acknowledge irq */ 390 mdelay(1); 391 } 392 393 /** 394 * navi10_ih_get_wptr - get the IH ring buffer wptr 395 * 396 * @adev: amdgpu_device pointer 397 * 398 * Get the IH ring buffer wptr from either the register 399 * or the writeback memory buffer (NAVI10). Also check for 400 * ring buffer overflow and deal with it. 401 * Returns the value of the wptr. 402 */ 403 static u32 navi10_ih_get_wptr(struct amdgpu_device *adev, 404 struct amdgpu_ih_ring *ih) 405 { 406 u32 wptr, reg, tmp; 407 408 wptr = le32_to_cpu(*ih->wptr_cpu); 409 410 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 411 goto out; 412 413 if (ih == &adev->irq.ih) 414 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 415 else if (ih == &adev->irq.ih1) 416 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 417 else if (ih == &adev->irq.ih2) 418 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 419 else 420 BUG(); 421 422 wptr = RREG32_NO_KIQ(reg); 423 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 424 goto out; 425 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 426 427 /* When a ring buffer overflow happen start parsing interrupt 428 * from the last not overwritten vector (wptr + 32). Hopefully 429 * this should allow us to catch up. 430 */ 431 tmp = (wptr + 32) & ih->ptr_mask; 432 dev_warn(adev->dev, "IH ring buffer overflow " 433 "(0x%08X, 0x%08X, 0x%08X)\n", 434 wptr, ih->rptr, tmp); 435 ih->rptr = tmp; 436 437 if (ih == &adev->irq.ih) 438 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 439 else if (ih == &adev->irq.ih1) 440 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 441 else if (ih == &adev->irq.ih2) 442 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 443 else 444 BUG(); 445 446 tmp = RREG32_NO_KIQ(reg); 447 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 448 WREG32_NO_KIQ(reg, tmp); 449 out: 450 return (wptr & ih->ptr_mask); 451 } 452 453 /** 454 * navi10_ih_decode_iv - decode an interrupt vector 455 * 456 * @adev: amdgpu_device pointer 457 * 458 * Decodes the interrupt vector at the current rptr 459 * position and also advance the position. 460 */ 461 static void navi10_ih_decode_iv(struct amdgpu_device *adev, 462 struct amdgpu_ih_ring *ih, 463 struct amdgpu_iv_entry *entry) 464 { 465 /* wptr/rptr are in bytes! */ 466 u32 ring_index = ih->rptr >> 2; 467 uint32_t dw[8]; 468 469 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 470 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 471 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 472 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 473 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 474 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 475 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 476 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 477 478 entry->client_id = dw[0] & 0xff; 479 entry->src_id = (dw[0] >> 8) & 0xff; 480 entry->ring_id = (dw[0] >> 16) & 0xff; 481 entry->vmid = (dw[0] >> 24) & 0xf; 482 entry->vmid_src = (dw[0] >> 31); 483 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 484 entry->timestamp_src = dw[2] >> 31; 485 entry->pasid = dw[3] & 0xffff; 486 entry->pasid_src = dw[3] >> 31; 487 entry->src_data[0] = dw[4]; 488 entry->src_data[1] = dw[5]; 489 entry->src_data[2] = dw[6]; 490 entry->src_data[3] = dw[7]; 491 492 /* wptr/rptr are in bytes! */ 493 ih->rptr += 32; 494 } 495 496 /** 497 * navi10_ih_irq_rearm - rearm IRQ if lost 498 * 499 * @adev: amdgpu_device pointer 500 * 501 */ 502 static void navi10_ih_irq_rearm(struct amdgpu_device *adev, 503 struct amdgpu_ih_ring *ih) 504 { 505 uint32_t reg_rptr = 0; 506 uint32_t v = 0; 507 uint32_t i = 0; 508 509 if (ih == &adev->irq.ih) 510 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 511 else if (ih == &adev->irq.ih1) 512 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 513 else if (ih == &adev->irq.ih2) 514 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 515 else 516 return; 517 518 /* Rearm IRQ / re-write doorbell if doorbell write is lost */ 519 for (i = 0; i < MAX_REARM_RETRY; i++) { 520 v = RREG32_NO_KIQ(reg_rptr); 521 if ((v < ih->ring_size) && (v != ih->rptr)) 522 WDOORBELL32(ih->doorbell_index, ih->rptr); 523 else 524 break; 525 } 526 } 527 528 /** 529 * navi10_ih_set_rptr - set the IH ring buffer rptr 530 * 531 * @adev: amdgpu_device pointer 532 * 533 * Set the IH ring buffer rptr. 534 */ 535 static void navi10_ih_set_rptr(struct amdgpu_device *adev, 536 struct amdgpu_ih_ring *ih) 537 { 538 if (ih->use_doorbell) { 539 /* XXX check if swapping is necessary on BE */ 540 *ih->rptr_cpu = ih->rptr; 541 WDOORBELL32(ih->doorbell_index, ih->rptr); 542 543 if (amdgpu_sriov_vf(adev)) 544 navi10_ih_irq_rearm(adev, ih); 545 } else if (ih == &adev->irq.ih) { 546 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 547 } else if (ih == &adev->irq.ih1) { 548 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); 549 } else if (ih == &adev->irq.ih2) { 550 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); 551 } 552 } 553 554 /** 555 * navi10_ih_self_irq - dispatch work for ring 1 and 2 556 * 557 * @adev: amdgpu_device pointer 558 * @source: irq source 559 * @entry: IV with WPTR update 560 * 561 * Update the WPTR from the IV and schedule work to handle the entries. 562 */ 563 static int navi10_ih_self_irq(struct amdgpu_device *adev, 564 struct amdgpu_irq_src *source, 565 struct amdgpu_iv_entry *entry) 566 { 567 uint32_t wptr = cpu_to_le32(entry->src_data[0]); 568 569 switch (entry->ring_id) { 570 case 1: 571 *adev->irq.ih1.wptr_cpu = wptr; 572 schedule_work(&adev->irq.ih1_work); 573 break; 574 case 2: 575 *adev->irq.ih2.wptr_cpu = wptr; 576 schedule_work(&adev->irq.ih2_work); 577 break; 578 default: break; 579 } 580 return 0; 581 } 582 583 static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = { 584 .process = navi10_ih_self_irq, 585 }; 586 587 static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 588 { 589 adev->irq.self_irq.num_types = 0; 590 adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs; 591 } 592 593 static int navi10_ih_early_init(void *handle) 594 { 595 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 596 597 navi10_ih_set_interrupt_funcs(adev); 598 navi10_ih_set_self_irq_funcs(adev); 599 return 0; 600 } 601 602 static int navi10_ih_sw_init(void *handle) 603 { 604 int r; 605 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 606 bool use_bus_addr; 607 608 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 609 &adev->irq.self_irq); 610 611 if (r) 612 return r; 613 614 /* use gpu virtual address for ih ring 615 * until ih_checken is programmed to allow 616 * use bus address for ih ring by psp bl */ 617 use_bus_addr = 618 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true; 619 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 620 if (r) 621 return r; 622 623 adev->irq.ih.use_doorbell = true; 624 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 625 626 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 627 if (r) 628 return r; 629 630 adev->irq.ih1.use_doorbell = true; 631 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 632 633 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 634 if (r) 635 return r; 636 637 adev->irq.ih2.use_doorbell = true; 638 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 639 640 r = amdgpu_irq_init(adev); 641 642 return r; 643 } 644 645 static int navi10_ih_sw_fini(void *handle) 646 { 647 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 648 649 amdgpu_irq_fini(adev); 650 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 651 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 652 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 653 654 return 0; 655 } 656 657 static int navi10_ih_hw_init(void *handle) 658 { 659 int r; 660 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 661 662 r = navi10_ih_irq_init(adev); 663 if (r) 664 return r; 665 666 return 0; 667 } 668 669 static int navi10_ih_hw_fini(void *handle) 670 { 671 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 672 673 navi10_ih_irq_disable(adev); 674 675 return 0; 676 } 677 678 static int navi10_ih_suspend(void *handle) 679 { 680 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 681 682 return navi10_ih_hw_fini(adev); 683 } 684 685 static int navi10_ih_resume(void *handle) 686 { 687 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 688 689 return navi10_ih_hw_init(adev); 690 } 691 692 static bool navi10_ih_is_idle(void *handle) 693 { 694 /* todo */ 695 return true; 696 } 697 698 static int navi10_ih_wait_for_idle(void *handle) 699 { 700 /* todo */ 701 return -ETIMEDOUT; 702 } 703 704 static int navi10_ih_soft_reset(void *handle) 705 { 706 /* todo */ 707 return 0; 708 } 709 710 static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev, 711 bool enable) 712 { 713 uint32_t data, def, field_val; 714 715 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 716 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 717 field_val = enable ? 0 : 1; 718 data = REG_SET_FIELD(data, IH_CLK_CTRL, 719 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 720 data = REG_SET_FIELD(data, IH_CLK_CTRL, 721 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 722 data = REG_SET_FIELD(data, IH_CLK_CTRL, 723 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 724 data = REG_SET_FIELD(data, IH_CLK_CTRL, 725 DYN_CLK_SOFT_OVERRIDE, field_val); 726 data = REG_SET_FIELD(data, IH_CLK_CTRL, 727 REG_CLK_SOFT_OVERRIDE, field_val); 728 if (def != data) 729 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 730 } 731 732 return; 733 } 734 735 static int navi10_ih_set_clockgating_state(void *handle, 736 enum amd_clockgating_state state) 737 { 738 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 739 740 navi10_ih_update_clockgating_state(adev, 741 state == AMD_CG_STATE_GATE); 742 return 0; 743 } 744 745 static int navi10_ih_set_powergating_state(void *handle, 746 enum amd_powergating_state state) 747 { 748 return 0; 749 } 750 751 static void navi10_ih_get_clockgating_state(void *handle, u32 *flags) 752 { 753 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 754 755 if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL)) 756 *flags |= AMD_CG_SUPPORT_IH_CG; 757 758 return; 759 } 760 761 static const struct amd_ip_funcs navi10_ih_ip_funcs = { 762 .name = "navi10_ih", 763 .early_init = navi10_ih_early_init, 764 .late_init = NULL, 765 .sw_init = navi10_ih_sw_init, 766 .sw_fini = navi10_ih_sw_fini, 767 .hw_init = navi10_ih_hw_init, 768 .hw_fini = navi10_ih_hw_fini, 769 .suspend = navi10_ih_suspend, 770 .resume = navi10_ih_resume, 771 .is_idle = navi10_ih_is_idle, 772 .wait_for_idle = navi10_ih_wait_for_idle, 773 .soft_reset = navi10_ih_soft_reset, 774 .set_clockgating_state = navi10_ih_set_clockgating_state, 775 .set_powergating_state = navi10_ih_set_powergating_state, 776 .get_clockgating_state = navi10_ih_get_clockgating_state, 777 }; 778 779 static const struct amdgpu_ih_funcs navi10_ih_funcs = { 780 .get_wptr = navi10_ih_get_wptr, 781 .decode_iv = navi10_ih_decode_iv, 782 .set_rptr = navi10_ih_set_rptr 783 }; 784 785 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 786 { 787 if (adev->irq.ih_funcs == NULL) 788 adev->irq.ih_funcs = &navi10_ih_funcs; 789 } 790 791 const struct amdgpu_ip_block_version navi10_ih_ip_block = 792 { 793 .type = AMD_IP_BLOCK_TYPE_IH, 794 .major = 5, 795 .minor = 0, 796 .rev = 0, 797 .funcs = &navi10_ih_ip_funcs, 798 }; 799