clk: tegra: clk-dfll: Add suspend and resume support

This patch implements DFLL suspend and resume operation.

During system suspend entry, CPU clock will switch CPU to safe
clock source of PLLP and

clk: tegra: clk-dfll: Add suspend and resume support

This patch implements DFLL suspend and resume operation.

During system suspend entry, CPU clock will switch CPU to safe
clock source of PLLP and disables DFLL clock output.

DFLL driver suspend confirms DFLL disable state and errors out on
being active.

DFLL is re-initialized during the DFLL driver resume as it goes
through complete reset during suspend entry.

Acked-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

show more ...

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174

Based on 1 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of th

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174

Based on 1 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation this program is
distributed in the hope that it will be useful but without any
warranty without even the implied warranty of merchantability or
fitness for a particular purpose see the gnu general public license
for more details

extracted by the scancode license scanner the SPDX license identifier

GPL-2.0-only

has been chosen to replace the boilerplate/reference in 655 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

show more ...

clk: tegra: dfll: CVB calculation alignment with the regulator

The CVB table contains calibration data for the CPU DFLL based on
process characterization. The regulator step and offset parameters de

clk: tegra: dfll: CVB calculation alignment with the regulator

The CVB table contains calibration data for the CPU DFLL based on
process characterization. The regulator step and offset parameters depend
on the regulator supplying vdd-cpu, not on the specific Tegra SKU.

When using a PWM controlled regulator, the voltage step and offset are
determined by the regulator type in use. This is specified in DT. When
using an I2C controlled regulator, we can retrieve them from CPU regulator
Then pass this information to the CVB table calculation function.

Based on the work done of "Peter De Schrijver <pdeschrijver@nvidia.com>"
and "Alex Frid <afrid@nvidia.com>".

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

show more ...

clk: tegra: dfll: Fix drvdata overwriting issue

Both tegra124-dfll and clk-dfll are using platform_set_drvdata
to set drvdata of the exact same pdev while they use different
pointers for the drvdata

clk: tegra: dfll: Fix drvdata overwriting issue

Both tegra124-dfll and clk-dfll are using platform_set_drvdata
to set drvdata of the exact same pdev while they use different
pointers for the drvdata. Once the drvdata has been overwritten
by tegra124-dfll, clk-dfll will never get its td pointer as it
expects.

Since tegra124-dfll merely needs its soc pointer in its remove
function, this patch fixes the bug by removing the overwriting
in the tegra124-dfll file and letting the tegra_dfll_unregister
return an soc pointer for it.

Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

show more ...

clk: tegra: dfll: Properly clean up on failure and removal

Upon failure to probe the DFLL, the OPP table will not be cleaned up
properly. Fix this and while at it make sure the OPP table will also b

clk: tegra: dfll: Properly clean up on failure and removal

Upon failure to probe the DFLL, the OPP table will not be cleaned up
properly. Fix this and while at it make sure the OPP table will also be
cleared upon driver removal.

Signed-off-by: Thierry Reding <treding@nvidia.com>

show more ...

clk: tegra: dfll: Reference CVB table instead of copying data

Instead of copying parts of the CVB table into a separate structure,
keep track of the selected CVB table and directly reference data fr

clk: tegra: dfll: Reference CVB table instead of copying data

Instead of copying parts of the CVB table into a separate structure,
keep track of the selected CVB table and directly reference data from
it.

Signed-off-by: Thierry Reding <treding@nvidia.com>

show more ...

clk: tegra: dfll: Update kerneldoc

The kerneldoc for struct tegra_dfll_soc_data is stale. Update it to
match the current structure definition.

Signed-off-by: Thierry Reding <treding@nvidia.com>

clk: tegra: Add Tegra124 DFLL clocksource platform driver

Add basic platform driver support for the fast CPU cluster DFLL
clocksource found on Tegra124 SoCs. This small driver selects the
appropriat

clk: tegra: Add Tegra124 DFLL clocksource platform driver

Add basic platform driver support for the fast CPU cluster DFLL
clocksource found on Tegra124 SoCs. This small driver selects the
appropriate Tegra124-specific characterization data and integration
code. It relies on the DFLL common code to do most of the work.

Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: Michael Turquette <mturquette@linaro.org>
[treding@nvidia.com: move setup code into ->probe()]
Signed-off-by: Thierry Reding <treding@nvidia.com>

show more ...

clk: tegra: Add library for the DFLL clock source (open-loop mode)

Add shared code to support the Tegra DFLL clocksource in open-loop
mode. This root clocksource is present on the Tegra124 SoCs. The

clk: tegra: Add library for the DFLL clock source (open-loop mode)

Add shared code to support the Tegra DFLL clocksource in open-loop
mode. This root clocksource is present on the Tegra124 SoCs. The
DFLL is the intended primary clock source for the fast CPU cluster.

This code is very closely based on a patch by Paul Walmsley from
December (http://comments.gmane.org/gmane.linux.ports.tegra/15273),
which in turn comes from the internal driver by originally created
by Aleksandr Frid <afrid@nvidia.com>.

Subsequent patches will add support for closed loop mode and drivers
for the Tegra124 fast CPU cluster DFLL devices, which rely on this
code.

Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

show more ...

clk: tegra: clk-dfll: Add suspend and resume support

This patch implements DFLL suspend and resume operation.

During system suspend entry, CPU clock will switch CPU to safe
cloc

clk: tegra: clk-dfll: Add suspend and resume support

This patch implements DFLL suspend and resume operation.

During system suspend entry, CPU clock will switch CPU to safe
clock source of PLLP and disables DFLL clock output.

DFLL driver suspend confirms DFLL disable state and errors out on
being active.

DFLL is re-initialized during the DFLL driver resume as it goes
through complete reset during suspend entry.

Acked-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

show more ...

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174

Based on 1 normalized pattern(s):

this program is free software you can redistribute it and or modify
it u

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174

Based on 1 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation this program is
distributed in the hope that it will be useful but without any
warranty without even the implied warranty of merchantability or
fitness for a particular purpose see the gnu general public license
for more details

extracted by the scancode license scanner the SPDX license identifier

GPL-2.0-only

has been chosen to replace the boilerplate/reference in 655 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

show more ...

clk: tegra: dfll: CVB calculation alignment with the regulator

The CVB table contains calibration data for the CPU DFLL based on
process characterization. The regulator step and offset p

clk: tegra: dfll: CVB calculation alignment with the regulator

The CVB table contains calibration data for the CPU DFLL based on
process characterization. The regulator step and offset parameters depend
on the regulator supplying vdd-cpu, not on the specific Tegra SKU.

When using a PWM controlled regulator, the voltage step and offset are
determined by the regulator type in use. This is specified in DT. When
using an I2C controlled regulator, we can retrieve them from CPU regulator
Then pass this information to the CVB table calculation function.

Based on the work done of "Peter De Schrijver <pdeschrijver@nvidia.com>"
and "Alex Frid <afrid@nvidia.com>".

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

show more ...

clk: tegra: dfll: Fix drvdata overwriting issue

Both tegra124-dfll and clk-dfll are using platform_set_drvdata
to set drvdata of the exact same pdev while they use different
pointers

clk: tegra: dfll: Fix drvdata overwriting issue

Both tegra124-dfll and clk-dfll are using platform_set_drvdata
to set drvdata of the exact same pdev while they use different
pointers for the drvdata. Once the drvdata has been overwritten
by tegra124-dfll, clk-dfll will never get its td pointer as it
expects.

Since tegra124-dfll merely needs its soc pointer in its remove
function, this patch fixes the bug by removing the overwriting
in the tegra124-dfll file and letting the tegra_dfll_unregister
return an soc pointer for it.

Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

show more ...

clk: tegra: dfll: Properly clean up on failure and removal

Upon failure to probe the DFLL, the OPP table will not be cleaned up
properly. Fix this and while at it make sure the OPP table

clk: tegra: dfll: Properly clean up on failure and removal

Upon failure to probe the DFLL, the OPP table will not be cleaned up
properly. Fix this and while at it make sure the OPP table will also be
cleared upon driver removal.

Signed-off-by: Thierry Reding <treding@nvidia.com>

show more ...

clk: tegra: dfll: Reference CVB table instead of copying data

Instead of copying parts of the CVB table into a separate structure,
keep track of the selected CVB table and directly refer

clk: tegra: dfll: Reference CVB table instead of copying data

Instead of copying parts of the CVB table into a separate structure,
keep track of the selected CVB table and directly reference data from
it.

Signed-off-by: Thierry Reding <treding@nvidia.com>

show more ...

clk: tegra: dfll: Update kerneldoc

The kerneldoc for struct tegra_dfll_soc_data is stale. Update it to
match the current structure definition.

Signed-off-by: Thierry Reding <tre

clk: tegra: dfll: Update kerneldoc

The kerneldoc for struct tegra_dfll_soc_data is stale. Update it to
match the current structure definition.

Signed-off-by: Thierry Reding <treding@nvidia.com>

show more ...

clk: tegra: Add Tegra124 DFLL clocksource platform driver

Add basic platform driver support for the fast CPU cluster DFLL
clocksource found on Tegra124 SoCs. This small driver selects th

clk: tegra: Add Tegra124 DFLL clocksource platform driver

Add basic platform driver support for the fast CPU cluster DFLL
clocksource found on Tegra124 SoCs. This small driver selects the
appropriate Tegra124-specific characterization data and integration
code. It relies on the DFLL common code to do most of the work.

Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: Michael Turquette <mturquette@linaro.org>
[treding@nvidia.com: move setup code into ->probe()]
Signed-off-by: Thierry Reding <treding@nvidia.com>

show more ...

clk: tegra: Add library for the DFLL clock source (open-loop mode)

Add shared code to support the Tegra DFLL clocksource in open-loop
mode. This root clocksource is present on the Tegra1

clk: tegra: Add library for the DFLL clock source (open-loop mode)

Add shared code to support the Tegra DFLL clocksource in open-loop
mode. This root clocksource is present on the Tegra124 SoCs. The
DFLL is the intended primary clock source for the fast CPU cluster.

This code is very closely based on a patch by Paul Walmsley from
December (http://comments.gmane.org/gmane.linux.ports.tegra/15273),
which in turn comes from the internal driver by originally created
by Aleksandr Frid <afrid@nvidia.com>.

Subsequent patches will add support for closed loop mode and drivers
for the Tegra124 fast CPU cluster DFLL devices, which rely on this
code.

Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

show more ...