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Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4 |
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| #
63370298 |
| 22-Jun-2023 |
Fabrizio Castro <fabrizio.castro.jz@renesas.com> |
clk: renesas: r9a09g011: Add CSI related clocks
The Renesas RZ/V2M SoC comes with 6 CSI IPs (CSI0, CSI1, CSI2
CSI3, CSI4, and CSI5), however Linux is only allowed control
of CSI0 and CSI4.
CSI0 shar
clk: renesas: r9a09g011: Add CSI related clocks
The Renesas RZ/V2M SoC comes with 6 CSI IPs (CSI0, CSI1, CSI2
CSI3, CSI4, and CSI5), however Linux is only allowed control
of CSI0 and CSI4.
CSI0 shares its reset and PCLK lines with CSI1, CSI2, and CSI3.
CSI4 shares its reset and PCLK lines with CSI5.
This commit adds support for the relevant clocks.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230622113341.657842-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Revision tags: v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13 |
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| #
d969103a |
| 13-Dec-2022 |
Phil Edworthy <phil.edworthy@renesas.com> |
clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries
Add SDHI/eMMC clock/reset entries to CPG driver.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Geert Uytterhoe
clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries
Add SDHI/eMMC clock/reset entries to CPG driver.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20221213230129.549968-2-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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| #
5edf5b51 |
| 12-Dec-2022 |
Biju Das <biju.das.jz@bp.renesas.com> |
clk: renesas: r9a09g011: Add USB clock and reset entries
Add USB clock and reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+r
clk: renesas: r9a09g011: Add USB clock and reset entries
Add USB clock and reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20221212172804.1277751-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Revision tags: v6.1, v6.0.12 |
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| #
d459f557 |
| 05-Dec-2022 |
Biju Das <biju.das.jz@bp.renesas.com> |
clk: renesas: r9a09g011: Add TIM clock and reset entries
Add Compare-Match Timer (TIM) clock and reset entries to CPG
driver.
The TIM IP on the RZ/V2M comes with 32 channels, but the ISP has
full c
clk: renesas: r9a09g011: Add TIM clock and reset entries
Add Compare-Match Timer (TIM) clock and reset entries to CPG
driver.
The TIM IP on the RZ/V2M comes with 32 channels, but the ISP has
full control of channels 0 to 7, and channels 24 to 31. Therefore
Linux is only allowed to use channels 8 to 23.
The TIM has shared peripheral clock with other modules, so mark it
as critical clock.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20221205145955.391526-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Revision tags: v6.0.11, v6.0.10, v5.15.80 |
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| #
868695e4 |
| 24-Nov-2022 |
Biju Das <biju.das.jz@bp.renesas.com> |
clk: renesas: r9a09g011: Add PWM clock and reset entries
Add PWM{8..14} clock and reset entries to CPG driver.
The PWM IP on the RZ/V2M comes with 16 channels, but the ISP has
full control of chann
clk: renesas: r9a09g011: Add PWM clock and reset entries
Add PWM{8..14} clock and reset entries to CPG driver.
The PWM IP on the RZ/V2M comes with 16 channels, but the ISP has
full control of channels 0 to 7, and channel 15, therefore Linux
is only allowed to use channels 8 to 14.
The PWM channel 15 shares apb clock and reset with PWM{8..14}.
The reset is deasserted by the bootloader/ISP.
Add PWM{8..14} clocks to CPG driver and mark apb clock as
critical clock, so that the apb clock will be always on.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20221124191643.3193423-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Revision tags: v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62 |
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| #
425e9e04 |
| 19-Aug-2022 |
Phil Edworthy <phil.edworthy@renesas.com> |
clk: renesas: r9a09g011: Add IIC clock and reset entries
Add IIC groups clock and reset entries to CPG driver.
IIC Group A consists of IIC0 and IIC1. IIC Group B consists of
IIC2 and IIC3. To confus
clk: renesas: r9a09g011: Add IIC clock and reset entries
Add IIC groups clock and reset entries to CPG driver.
IIC Group A consists of IIC0 and IIC1. IIC Group B consists of
IIC2 and IIC3. To confuse things, IIC_PCLK0 is used by group A
and IIC_PCLK1 is used by group B.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Link: https://lore.kernel.org/r/20220819193944.337599-2-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Revision tags: v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18 |
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| #
efded37b |
| 18-May-2022 |
Phil Edworthy <phil.edworthy@renesas.com> |
clk: renesas: r9a09g011: Add WDT clock and reset entries
Add WDT0 clock and reset entries to CPG driver.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Link: https://lore.kernel.org/r/202
clk: renesas: r9a09g011: Add WDT clock and reset entries
Add WDT0 clock and reset entries to CPG driver.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Link: https://lore.kernel.org/r/20220518150105.48167-1-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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| #
e55c4481 |
| 18-May-2022 |
Phil Edworthy <phil.edworthy@renesas.com> |
clk: renesas: r9a09g011: Add PFC clock and reset entries
Add PFC clock/reset entries to CPG driver.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.ma
clk: renesas: r9a09g011: Add PFC clock and reset entries
Add PFC clock/reset entries to CPG driver.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220518135208.39885-1-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Revision tags: v5.15.41, v5.15.40, v5.15.39, v5.15.38 |
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| #
23426d1b |
| 04-May-2022 |
Phil Edworthy <phil.edworthy@renesas.com> |
clk: renesas: r9a09g011: Add eth clock and reset entries
Add ethernet clock/reset entries to CPG driver.
Note that the AXI and CHI clocks are both enabled and disabled using
the same register bit.
clk: renesas: r9a09g011: Add eth clock and reset entries
Add ethernet clock/reset entries to CPG driver.
Note that the AXI and CHI clocks are both enabled and disabled using
the same register bit.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220504145454.71287-2-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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| #
1dd65bb0 |
| 03-May-2022 |
Phil Edworthy <phil.edworthy@renesas.com> |
clk: renesas: Add RZ/V2M support using the rzg2l driver
The Renesas RZ/V2M SoC is very similar to RZ/G2L, though it doesn't have
any CLK_MON registers.
Signed-off-by: Phil Edworthy <phil.edworthy@r
clk: renesas: Add RZ/V2M support using the rzg2l driver
The Renesas RZ/V2M SoC is very similar to RZ/G2L, though it doesn't have
any CLK_MON registers.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220503115557.53370-11-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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